On Mon, 2016-01-25 at 12:44 +, Lee Jones wrote:
> On Sat, 23 Jan 2016, Antoine Tenart wrote:
>
> > The GPIO base address is read from the GPIOBASE register. The first
> > bit must be cleared as it can be hardwired to 1 to represent the i/o
> > space. Other bits are either containing the base
On Mon, 2016-01-25 at 12:44 +, Lee Jones wrote:
> On Sat, 23 Jan 2016, Antoine Tenart wrote:
>
> > The GPIO base address is read from the GPIOBASE register. The first
> > bit must be cleared as it can be hardwired to 1 to represent the i/o
> > space. Other bits are either containing the base
> > Can you give more background on your hardware and firmware setup?
>
> Unfortunately I cannot :( The system isn't "mine" per se. It is (as the
> dumps show) IBM's.
Can you look at the IBM manual and see info about which chipsets are used, and
how they are connected?
> Are there
>
> >
> > >>> Then why do they [have two devices specified]?
> > >>
> > >> Because the vendor didn't/forgot to hide one from the kernel in BIOS --
> > >> hence FW_BUG.
> > >
> > > If only one is useful, why have the second one in the first place?
> >
> > That's just it -- it shouldn't have been
Then why do they [have two devices specified]?
Because the vendor didn't/forgot to hide one from the kernel in BIOS --
hence FW_BUG.
If only one is useful, why have the second one in the first place?
That's just it -- it shouldn't have been exposed (again, according to
Can you give more background on your hardware and firmware setup?
Unfortunately I cannot :( The system isn't mine per se. It is (as the
dumps show) IBM's.
Can you look at the IBM manual and see info about which chipsets are used, and
how they are connected?
Are there
physically two
The original bitmask of 0x10 was incorrect and would result in a write
to a reserved read-only bit instead of enabling the ACPI I/O
region. Update it to the proper value of 0x80.
Signed-off-by: Peter Tyser
Tested-by: Rajat Jain
Cc: Guenter Roeck
Cc: James Ralston
Cc: Samuel Ortiz
Cc: Lee
Future chipsets will use different register layouts that don't map
cleanly to the lpc_ich_cfg fields. Remove the lpc_ich_cfg struct and
add explicit fields to the higher level lpc_ich_priv structure.
This change should have no functional impact.
Signed-off-by: Peter Tyser
Tested-by: Rajat Jain
t;Power
Management Configuration Base Address" register resides at the same
address is Avoton/Bay Trail.
To differentiate these newer chipsets create a new v3 iTCO version and
update the MFD driver to support them.
Signed-off-by: Peter Tyser
Tested-by: Rajat Jain
Cc: Guenter Roeck
Cc: James Ral
The register layout of the Avoton is compatible with the iTCO v3
register layout.
Signed-off-by: Peter Tyser
Tested-by: Rajat Jain
Cc: Guenter Roeck
Cc: James Ralston
Cc: Samuel Ortiz
Cc: Lee Jones
Cc: Wim Van Sebroeck
Cc: linux-watch...@vger.kernel.org
---
drivers/mfd/lpc_ich.c |2
in TCO_STS was removed
- The NO_REBOOT bit is in the PMC area instead of GCS
Update the driver to support the above changes and bump the version to
1.11.
Signed-off-by: Peter Tyser
Tested-by: Rajat Jain
Cc: Guenter Roeck
Cc: James Ralston
Cc: Samuel Ortiz
Cc: Lee Jones
Cc: Wim Van Sebroeck
Cc
This patch adds the LPC Controller Device IDs for Watchdog and GPIO for
the Intel Bay Trail Atom SoC.
Signed-off-by: Peter Tyser
Cc: Guenter Roeck
Cc: James Ralston
Cc: Samuel Ortiz
Cc: Lee Jones
---
drivers/mfd/lpc_ich.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff
The NM10's GPIO is compatible with ICH v7 GPIO.
Signed-off-by: Peter Tyser
Tested-by: Dan Weinlader
Cc: Guenter Roeck
Cc: James Ralston
Cc: Samuel Ortiz
Cc: Lee Jones
---
drivers/mfd/lpc_ich.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mfd/lpc_ich.c b
Some chipsets don't currently have GPIO support enabled. For these
chipsets don't go through the process of initializing the GPIO region.
Make the same change for the watchdog initialization for chipsets which
may not enable the WDT in the future.
Signed-off-by: Peter Tyser
Tested-by: Rajat
Some chipsets don't currently have GPIO support enabled. For these
chipsets don't go through the process of initializing the GPIO region.
Make the same change for the watchdog initialization for chipsets which
may not enable the WDT in the future.
Signed-off-by: Peter Tyser pty...@xes-inc.com
The NM10's GPIO is compatible with ICH v7 GPIO.
Signed-off-by: Peter Tyser pty...@xes-inc.com
Tested-by: Dan Weinlader d...@vs-networks.com
Cc: Guenter Roeck li...@roeck-us.net
Cc: James Ralston james.d.rals...@intel.com
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Lee Jones lee.jo...@linaro.org
This patch adds the LPC Controller Device IDs for Watchdog and GPIO for
the Intel Bay Trail Atom SoC.
Signed-off-by: Peter Tyser pty...@xes-inc.com
Cc: Guenter Roeck li...@roeck-us.net
Cc: James Ralston james.d.rals...@intel.com
Cc: Samuel Ortiz sa...@linux.intel.com
Cc: Lee Jones lee.jo
in TCO_STS was removed
- The NO_REBOOT bit is in the PMC area instead of GCS
Update the driver to support the above changes and bump the version to
1.11.
Signed-off-by: Peter Tyser pty...@xes-inc.com
Tested-by: Rajat Jain rajatj...@juniper.net
Cc: Guenter Roeck li...@roeck-us.net
Cc: James Ralston
The register layout of the Avoton is compatible with the iTCO v3
register layout.
Signed-off-by: Peter Tyser pty...@xes-inc.com
Tested-by: Rajat Jain rajatj...@juniper.net
Cc: Guenter Roeck li...@roeck-us.net
Cc: James Ralston james.d.rals...@intel.com
Cc: Samuel Ortiz sa...@linux.intel.com
Cc
is Avoton/Bay Trail.
To differentiate these newer chipsets create a new v3 iTCO version and
update the MFD driver to support them.
Signed-off-by: Peter Tyser pty...@xes-inc.com
Tested-by: Rajat Jain rajatj...@juniper.net
Cc: Guenter Roeck li...@roeck-us.net
Cc: James Ralston james.d.rals
Future chipsets will use different register layouts that don't map
cleanly to the lpc_ich_cfg fields. Remove the lpc_ich_cfg struct and
add explicit fields to the higher level lpc_ich_priv structure.
This change should have no functional impact.
Signed-off-by: Peter Tyser pty...@xes-inc.com
The original bitmask of 0x10 was incorrect and would result in a write
to a reserved read-only bit instead of enabling the ACPI I/O
region. Update it to the proper value of 0x80.
Signed-off-by: Peter Tyser pty...@xes-inc.com
Tested-by: Rajat Jain rajatj...@juniper.net
Cc: Guenter Roeck li
On 01/23/2014 12:50 AM, Guenter Roeck wrote:
> Hi folks,
>
> we are seeing an odd problem with kernel version 3.13 running on Mohan Peak
> with an Avoton 8-core CPU. The kernel boots to the login prompt and then
> freezes silently within a few seconds.
>
> The problem disappears if we revert
On 01/23/2014 12:50 AM, Guenter Roeck wrote:
Hi folks,
we are seeing an odd problem with kernel version 3.13 running on Mohan Peak
with an Avoton 8-core CPU. The kernel boots to the login prompt and then
freezes silently within a few seconds.
The problem disappears if we revert patch
Hi Jean,
On Tue, 2013-03-05 at 09:06 +0100, Jean Delvare wrote:
> Stop checking for pin availability in get functions. These functions
> can be called repeatedly, so checking every time is bad for
> performance.
>
> Instead, check at pin request time. This only happens once, and we can
> let the
Hi Jean,
On Tue, 2013-03-05 at 09:06 +0100, Jean Delvare wrote:
Stop checking for pin availability in get functions. These functions
can be called repeatedly, so checking every time is bad for
performance.
Instead, check at pin request time. This only happens once, and we can
let the
On Fri, 2013-02-08 at 17:33 -0800, James Ralston wrote:
> This patch adds the Watchdog Timer Device IDs for the Intel Wellsburg PCH
I don't have the Wellsburg documentation handy to verify the PCI device
ID values, but it looks good otherwise.
Acked-by: Peter Tyser
--
To unsubscribe f
On Fri, 2013-02-08 at 17:33 -0800, James Ralston wrote:
This patch adds the Watchdog Timer Device IDs for the Intel Wellsburg PCH
I don't have the Wellsburg documentation handy to verify the PCI device
ID values, but it looks good otherwise.
Acked-by: Peter Tyser pty...@xes-inc.com
On Sun, 2012-12-16 at 21:31 +0100, Jean Delvare wrote:
> As reported by CONFIG_DEBUG_SPINLOCK=y.
>
> Signed-off-by: Jean Delvare
> Cc: Peter Tyser
> Cc: Grant Likely
> Cc: Linus Walleij
> Cc: sta...@vger.kernel.org [v3.5+]
> ---
Acked-by: Peter Tyser
--
To unsubscr
On Sun, 2012-12-16 at 21:31 +0100, Jean Delvare wrote:
As reported by CONFIG_DEBUG_SPINLOCK=y.
Signed-off-by: Jean Delvare kh...@linux-fr.org
Cc: Peter Tyser pty...@xes-inc.com
Cc: Grant Likely grant.lik...@secretlab.ca
Cc: Linus Walleij linus.wall...@linaro.org
Cc: sta...@vger.kernel.org
om mfd_remove_devices_fn before processing the device.
>
> Signed-off-by: Charles Keepax
> Reviewed-by: Mark Brown
> Signed-off-by: Samuel Ortiz
Tested-by: Peter Tyser
Looks good to me.
Best,
Peter
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel&
...@opensource.wolfsonmicro.com
Signed-off-by: Samuel Ortiz sa...@linux.intel.com
Tested-by: Peter Tyser pty...@xes-inc.com
Looks good to me.
Best,
Peter
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Thanks for reporting the issue!
On Fri, 2012-11-09 at 14:19 +0100, Paul Bolle wrote:
> 0) I can trigger a NULL pointer dereference if I remove the lpc_ich
> module. This seems to only happen if I remove it for the second time
> (ie, remove the module, insert it and remove it again). This happens
Thanks for reporting the issue!
On Fri, 2012-11-09 at 14:19 +0100, Paul Bolle wrote:
0) I can trigger a NULL pointer dereference if I remove the lpc_ich
module. This seems to only happen if I remove it for the second time
(ie, remove the module, insert it and remove it again). This happens
Hi Miles,
On Thu, 2012-10-04 at 10:14 -0400, Miles Lane wrote:
> ACPI Warning: 0x0828-0x082f SystemIO conflicts
> with Region \PMIO 1 (20120711/utaddress-251)
> ACPI: If an ACPI driver is available for this device, you should use
> it instead of the native driver
> ACPI
Hi Miles,
On Thu, 2012-10-04 at 10:14 -0400, Miles Lane wrote:
ACPI Warning: 0x0828-0x082f SystemIO conflicts
with Region \PMIO 1 (20120711/utaddress-251)
ACPI: If an ACPI driver is available for this device, you should use
it instead of the native driver
ACPI
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