06, 2018 at 01:47:47PM +0200, Philipp Rossak wrote:
On 04.09.2018 18:46, Emmanuel Vadot wrote:
+ /* Data cells */
+ thermal_calibration: calib@234 {
+ reg = <0x234 0x8>;
+ };
You are declaring 8 bytes of calibratio
:19, Kyle Evans wrote:
On Thu, Apr 19, 2018 at 10:13 AM, Icenowy Zheng <icen...@aosc.io> wrote:
于 2018年4月19日 GMT+08:00 下午11:11:22, Kyle Evans <kev...@freebsd.org> 写到:
On Mon, Jan 29, 2018 at 6:03 AM, Philipp Rossak <embe...@gmail.com>
wrote:
On 29.01.2018 10:52, Maxime Ripa
:19, Kyle Evans wrote:
On Thu, Apr 19, 2018 at 10:13 AM, Icenowy Zheng wrote:
于 2018年4月19日 GMT+08:00 下午11:11:22, Kyle Evans 写到:
On Mon, Jan 29, 2018 at 6:03 AM, Philipp Rossak
wrote:
On 29.01.2018 10:52, Maxime Ripard wrote:
On Mon, Jan 29, 2018 at 12:29:17AM +0100, Philipp Rossak wrote
On 13.02.2018 13:29, Philipp Rossak wrote:
This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip
On 13.02.2018 13:29, Philipp Rossak wrote:
This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip
On 19.02.2018 09:10, Maxime Ripard wrote:
On Sat, Feb 17, 2018 at 03:22:35PM +0100, Philipp Rossak wrote:
Right now the performance govenor is the default frequency govenor on
sunxi devices. This causes some general problems.
When the cpu is idle the cpu runs with its maximum frequency
On 19.02.2018 09:10, Maxime Ripard wrote:
On Sat, Feb 17, 2018 at 03:22:35PM +0100, Philipp Rossak wrote:
Right now the performance govenor is the default frequency govenor on
sunxi devices. This causes some general problems.
When the cpu is idle the cpu runs with its maximum frequency
d clk output support")
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Changes in v4:
* add more information to the comment
Changes in v3:
* add information when the bug appeared
* make the comment more clear
Changes in v2:
* add tag Fixes: ... t
d clk output support")
Signed-off-by: Philipp Rossak
---
Changes in v4:
* add more information to the comment
Changes in v3:
* add information when the bug appeared
* make the comment more clear
Changes in v2:
* add tag Fixes: ... to commit message
* a
On 16.02.2018 14:15, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 9:07 PM, Maxime Ripard
wrote:
On Fri, Feb 16, 2018 at 12:10:18PM +0800, Chen-Yu Tsai wrote:
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
On 16.02.2018 14:15, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 9:07 PM, Maxime Ripard
wrote:
On Fri, Feb 16, 2018 at 12:10:18PM +0800, Chen-Yu Tsai wrote:
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index
frequency govenor to ondemand mode
and reduce the temperature when the cpu is idle and activate the thermal
throtteling.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig
frequency govenor to ondemand mode
and reduce the temperature when the cpu is idle and activate the thermal
throtteling.
Signed-off-by: Philipp Rossak
---
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs
nment. Now the system crashes as div_ops tries
to look up a nonexistent table.
Reported-by: Philipp Rossak <embe...@gmail.com>
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Cc: <sta...@vger.kernel.org>
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Tested
nment. Now the system crashes as div_ops tries
to look up a nonexistent table.
Reported-by: Philipp Rossak
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Cc:
Signed-off-by: Chen-Yu Tsai
Tested-by: Philipp Rossak
---
Philipp, can you give this a test and report if this
On 16.02.2018 13:59, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 8:49 PM, Philipp Rossak <embe...@gmail.com> wrote:
On 16.02.2018 05:10, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 1:53 AM, Philipp Rossak <embe...@gmail.com> wrote:
On 15.02.2018 15:11, Maxime Ripard wrot
On 16.02.2018 13:59, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 8:49 PM, Philipp Rossak wrote:
On 16.02.2018 05:10, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 1:53 AM, Philipp Rossak wrote:
On 15.02.2018 15:11, Maxime Ripard wrote:
On Wed, Feb 14, 2018 at 02:56:12PM +0100
On 16.02.2018 05:10, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 1:53 AM, Philipp Rossak <embe...@gmail.com> wrote:
On 15.02.2018 15:11, Maxime Ripard wrote:
On Wed, Feb 14, 2018 at 02:56:12PM +0100, Philipp Rossak wrote:
This patch fixes a bug, that prevents the Allwinne
On 16.02.2018 05:10, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 1:53 AM, Philipp Rossak wrote:
On 15.02.2018 15:11, Maxime Ripard wrote:
On Wed, Feb 14, 2018 at 02:56:12PM +0100, Philipp Rossak wrote:
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from
On 15.02.2018 15:11, Maxime Ripard wrote:
On Wed, Feb 14, 2018 at 02:56:12PM +0100, Philipp Rossak wrote:
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot.
The bug is there since v4.16-rc1 and appeared after the clk branch was
merged.
Out
On 15.02.2018 15:11, Maxime Ripard wrote:
On Wed, Feb 14, 2018 at 02:56:12PM +0100, Philipp Rossak wrote:
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot.
The bug is there since v4.16-rc1 and appeared after the clk branch was
merged.
Out
On 15.02.2018 10:08, Maxime Ripard wrote:
On Wed, Feb 14, 2018 at 03:10:23PM +0100, Philipp Rossak wrote:
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.
Regards
On 15.02.2018 10:08, Maxime Ripard wrote:
On Wed, Feb 14, 2018 at 03:10:23PM +0100, Philipp Rossak wrote:
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.
Regards
properties on the mmc0 and mmc2
node to use the allready existent regulators.
We can now remove the sunxi-common-regulators.dtsi include since we
don't need it anymore.
Fixes: 7daa21370075 ("ARM: dts: sunxi: Add regulators for Sinovoip
BPI-M2")
Signed-off-by: Philipp Rossak <embe
properties on the mmc0 and mmc2
node to use the allready existent regulators.
We can now remove the sunxi-common-regulators.dtsi include since we
don't need it anymore.
Fixes: 7daa21370075 ("ARM: dts: sunxi: Add regulators for Sinovoip
BPI-M2")
Signed-off-by: Philipp Rossak
---
arch/ar
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 51e6f1d21c32..fb34f32502cf 10064
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 51e6f1d21c32..fb34f32502cf 100644
--- a/arch/arm/boot/dts/
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.
Regards,
Philipp
Changes since v1:
* squashed commit 1 and 3
* fix wrong mmc regulator
Philipp Rossak
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.
Regards,
Philipp
Changes since v1:
* squashed commit 1 and 3
* fix wrong mmc regulator
Philipp Rossak
d clk output support")
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Changes in v3:
* add information when the bug appeared
* make the comment more clear
Changes in v2:
* add tag Fixes: ... to commit message
* add comment to if statement why we are
d clk output support")
Signed-off-by: Philipp Rossak
---
Changes in v3:
* add information when the bug appeared
* make the comment more clear
Changes in v2:
* add tag Fixes: ... to commit message
* add comment to if statement why we are doing this check
drive
On 13.02.2018 14:44, Chen-Yu Tsai wrote:
On Tue, Feb 13, 2018 at 9:32 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
On Tue, Feb 13, 2018 at 01:14:14PM +0100, Philipp Rossak wrote:
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot. You ca
On 13.02.2018 14:44, Chen-Yu Tsai wrote:
On Tue, Feb 13, 2018 at 9:32 PM, Maxime Ripard
wrote:
On Tue, Feb 13, 2018 at 01:14:14PM +0100, Philipp Rossak wrote:
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot. You can find the shortend trace below
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak
Reviewed-by: Andi Shyti
Acked-by: Sean Young
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/su
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
1 file changed, 13 insertions(+)
diff
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a27e21d 100644
--- a/arch/arm
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak
Acked-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t
to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
media: dt: bindings: Update binding documentation for sunxi IR
controller
arm: dts: sun8i: a83t: Add the cir pin for the A83T
arm: dts: sun8i: a83t: Add
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <
to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
media: dt: bindings: Update binding documentation for sunxi IR
controller
arm: dts: sun8i: a83t: Add the cir pin for the A83T
arm: dts: sun8i: a83t: Add
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak
Acked-by: Maxime Ripard
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
1
if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.
The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198
Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")
Signed-off-by: Philipp Rossak <embe...@gmail.com>
--
if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.
The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198
Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")
Signed-off-by: Philipp Rossak
---
Changes in v2:
On 13.02.2018 03:59, Chen-Yu Tsai wrote:
On Tue, Feb 13, 2018 at 9:25 AM, Philipp Rossak <embe...@gmail.com> wrote:
On 12.02.2018 19:21, Philipp Rossak wrote:
Hey,
When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I
On 13.02.2018 03:59, Chen-Yu Tsai wrote:
On Tue, Feb 13, 2018 at 9:25 AM, Philipp Rossak wrote:
On 12.02.2018 19:21, Philipp Rossak wrote:
Hey,
When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I could capture this log
On 12.02.2018 19:21, Philipp Rossak wrote:
Hey,
When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I could capture this log: [1].
After reverting those 5 commits from Chen-Yu I was able to boot again:
clk: sunxi-ng
On 12.02.2018 19:21, Philipp Rossak wrote:
Hey,
When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I could capture this log: [1].
After reverting those 5 commits from Chen-Yu I was able to boot again:
clk: sunxi-ng
if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.
The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
drivers/rtc/rtc-ac100.c | 7 ++-
1 file changed, 6 insertions
if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.
The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198
Signed-off-by: Philipp Rossak
---
drivers/rtc/rtc-ac100.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff
Hey,
When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I could capture this log: [1].
After reverting those 5 commits from Chen-Yu I was able to boot again:
clk: sunxi-ng: Support fixed post-dividers on NM style clocks
Hey,
When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I could capture this log: [1].
After reverting those 5 commits from Chen-Yu I was able to boot again:
clk: sunxi-ng: Support fixed post-dividers on NM style clocks
On 30.01.2018 18:46, Philipp Rossak wrote:
This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip
On 30.01.2018 18:46, Philipp Rossak wrote:
This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip
Am Freitag, den 09.02.2018, 18:52 +0100 schrieb Philipp Rossak:
> This patch updates the vmmc-supply properties on the mmc0 and mmc2
> node to use the allready existent regulators.
> We can now remove the sunxi-common-regulators.dtsi include since we
> don't need it anymore.
>
Am Freitag, den 09.02.2018, 18:52 +0100 schrieb Philipp Rossak:
> This patch updates the vmmc-supply properties on the mmc0 and mmc2
> node to use the allready existent regulators.
> We can now remove the sunxi-common-regulators.dtsi include since we
> don't need it anymore.
>
Am Sonntag, den 11.02.2018, 10:55 +0300 schrieb Sergey Suloev:
> On 02/11/2018 01:07 AM, Philipp Rossak wrote:
> >
> >
> > On 10.02.2018 22:08, Sergey Suloev wrote:
> > > On 02/11/2018 12:01 AM, Philipp Rossak wrote:
> > > > Hey Sergey,
> >
Am Sonntag, den 11.02.2018, 10:55 +0300 schrieb Sergey Suloev:
> On 02/11/2018 01:07 AM, Philipp Rossak wrote:
> >
> >
> > On 10.02.2018 22:08, Sergey Suloev wrote:
> > > On 02/11/2018 12:01 AM, Philipp Rossak wrote:
> > > > Hey Sergey,
> >
Hey,
When I boot my A83T I get the following bootlog [1].
After some debugging, I found out that the function call:
clk_hw_get_num_parents() returns 2. After a look in the devicetree I
found out that this value should be 1, since we only have one parent
clock [3].
Setting the variable
Hey,
When I boot my A83T I get the following bootlog [1].
After some debugging, I found out that the function call:
clk_hw_get_num_parents() returns 2. After a look in the devicetree I
found out that this value should be 1, since we only have one parent
clock [3].
Setting the variable
On 10.02.2018 22:08, Sergey Suloev wrote:
On 02/11/2018 12:01 AM, Philipp Rossak wrote:
Hey Sergey,
Thanks for mentioning, but I think the problem has nothing to do with
those patches. I tested them with the v4.15.0 Kernel since this is the
last stable release and we are right now
On 10.02.2018 22:08, Sergey Suloev wrote:
On 02/11/2018 12:01 AM, Philipp Rossak wrote:
Hey Sergey,
Thanks for mentioning, but I think the problem has nothing to do with
those patches. I tested them with the v4.15.0 Kernel since this is the
last stable release and we are right now
is
not booting (I can't see any uart output).
Thanks,
Philipp
On 10.02.2018 14:56, Sergey Suloev wrote:
On 02/09/2018 08:52 PM, Philipp Rossak wrote:
This patchseries fixes the bananapi m1 devicetree, to be able to boot
again.
The first two patches update/improve the devicetree and the last patch
is
not booting (I can't see any uart output).
Thanks,
Philipp
On 10.02.2018 14:56, Sergey Suloev wrote:
On 02/09/2018 08:52 PM, Philipp Rossak wrote:
This patchseries fixes the bananapi m1 devicetree, to be able to boot
again.
The first two patches update/improve the devicetree and the last patch
This patch updates the vmmc-supply properties on the mmc0 and mmc2
node to use the allready existent regulators.
We can now remove the sunxi-common-regulators.dtsi include since we
don't need it anymore.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun6i-a31s-si
This patch updates the vmmc-supply properties on the mmc0 and mmc2
node to use the allready existent regulators.
We can now remove the sunxi-common-regulators.dtsi include since we
don't need it anymore.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 5
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.
Regards,
Philipp
Philipp Rossak (3):
arm: dts: sun6i: a31s: bpi-m2: update mmc supply nodes
arm: dts: sun6i: a31s
: 3,3V, powers the audio
* reg_dldo1: 3,0V, powers the RTL8211E
* reg_dldo2: 2,8V, powers the analog part of the csi
* reg_dldo3: 3,3V, powers misc
* reg_eldo1: 1,8V, powers the csi
* reg_ldo_io1:1,8V, powers the gpio
* reg_dc5ldo: needs to be always on
Signed-off-by: Philipp Rossak <e
The eldoin is supplied from the dcdc1 regulator. The N_VBUSEN pin is
connected to an external power regulator (SY6280AAC).
With this commit we update the pmic binding properties to support
those features.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun6i-a31s-si
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.
Regards,
Philipp
Philipp Rossak (3):
arm: dts: sun6i: a31s: bpi-m2: update mmc supply nodes
arm: dts: sun6i: a31s
: 3,3V, powers the audio
* reg_dldo1: 3,0V, powers the RTL8211E
* reg_dldo2: 2,8V, powers the analog part of the csi
* reg_dldo3: 3,3V, powers misc
* reg_eldo1: 1,8V, powers the csi
* reg_ldo_io1:1,8V, powers the gpio
* reg_dc5ldo: needs to be always on
Signed-off-by: Philipp Rossak
---
arch
The eldoin is supplied from the dcdc1 regulator. The N_VBUSEN pin is
connected to an external power regulator (SY6280AAC).
With this commit we update the pmic binding properties to support
those features.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2
/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
struct thermal_zone_device *tzd;
@@ -561,6 +569,9 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
struct resource *mem;
void __iomem
/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
struct thermal_zone_device *tzd;
@@ -561,6 +569,9 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
struct resource *mem;
void __iomem
On 31.01.2018 20:23, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:12AM +0100, Philipp Rossak wrote:
This patch adds support for the H3 ths sensor.
The H3 supports interrupts. The interrupt is configured to update the
the sensor values every second. The calibration data
On 31.01.2018 20:23, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:12AM +0100, Philipp Rossak wrote:
This patch adds support for the H3 ths sensor.
The H3 supports interrupts. The interrupt is configured to update the
the sensor values every second. The calibration data
On 31.01.2018 20:07, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:11AM +0100, Philipp Rossak wrote:
This patch rewors the driver to support interrupts for the thermal part
of the sensor.
This is only available for the newer sensor (currently H3 and A83T).
The interrupt
On 31.01.2018 20:07, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:11AM +0100, Philipp Rossak wrote:
This patch rewors the driver to support interrupts for the thermal part
of the sensor.
This is only available for the newer sensor (currently H3 and A83T).
The interrupt
On 31.01.2018 19:42, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:09AM +0100, Philipp Rossak wrote:
For adding newer sensor some basic rework of the code is necessary.
This patch reworks the driver to be able to handle more than one
thermal sensor. Newer SoC like the A80
On 31.01.2018 19:42, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:09AM +0100, Philipp Rossak wrote:
For adding newer sensor some basic rework of the code is necessary.
This patch reworks the driver to be able to handle more than one
thermal sensor. Newer SoC like the A80
On 31.01.2018 18:51, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:07AM +0100, Philipp Rossak wrote:
For adding newer sensor some basic rework of the code is necessary.
This commit reworks the code and allows the sampling start/end code and
the position of value readout
On 31.01.2018 18:51, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:07AM +0100, Philipp Rossak wrote:
For adding newer sensor some basic rework of the code is necessary.
This commit reworks the code and allows the sampling start/end code and
the position of value readout
On 31.01.2018 18:40, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:04AM +0100, Philipp Rossak wrote:
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC
On 31.01.2018 18:40, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:04AM +0100, Philipp Rossak wrote:
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak
Acked-by: Maxime Ripard
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
1
to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
media: dt: bindings: Update binding documentation for sunxi IR
controller
arm: dts: sun8i: a83t: Add the cir pin for the A83T
arm: dts: sun8i: a83t: Add
to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
media: dt: bindings: Update binding documentation for sunxi IR
controller
arm: dts: sun8i: a83t: Add the cir pin for the A83T
arm: dts: sun8i: a83t: Add
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a27e21d 100644
--- a/arch/arm
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
1 file changed, 13 insertions(+)
diff
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak
Reviewed-by: Andi Shyti
Acked-by: Sean Young
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...
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