On Saturday 24 August 2013 01:15 AM, Colin Cross wrote:
Calling cpuidle_enter_state is expected to return with interrupts
enabled, but interrupts must be disabled before starting the
ready loop synchronization stage. Call local_irq_disable after
each call to cpuidle_enter_state for the safe
On Saturday 24 August 2013 01:15 AM, Colin Cross wrote:
Calling cpuidle_enter_state is expected to return with interrupts
enabled, but interrupts must be disabled before starting the
ready loop synchronization stage. Call local_irq_disable after
each call to cpuidle_enter_state for the safe
On Thursday 01 August 2013 02:34 AM, Stephen Warren wrote:
On 07/31/2013 11:42 AM, Tuomas Tynkkynen wrote:
The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.
On Thursday 01 August 2013 02:34 AM, Stephen Warren wrote:
On 07/31/2013 11:42 AM, Tuomas Tynkkynen wrote:
The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.
not implement these APIs in DFLL clock driver itself and pass RST
address register to driver?
The reset assert/de-assert functions at least might be worth exposing
using the new generic module reset API. I believe Prashant Gaikwad is
working on converting the Tegra clock driver to be a module
On Tuesday 28 May 2013 08:46 PM, Stephen Warren wrote:
On 05/27/2013 01:40 AM, Prashant Gaikwad wrote:
Use common of_clk_init() function for clocks initialization.
Mike,
Please merge this patch in your tree.
Thanks,
PrashantG
Acked-by: Stephen Warren
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On Tuesday 28 May 2013 08:46 PM, Stephen Warren wrote:
On 05/27/2013 01:40 AM, Prashant Gaikwad wrote:
Use common of_clk_init() function for clocks initialization.
Mike,
Please merge this patch in your tree.
Thanks,
PrashantG
Acked-by: Stephen Warren swar...@nvidia.com
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already ;-)
Why not implement these APIs in DFLL clock driver itself and pass RST
address register to driver?
The reset assert/de-assert functions at least might be worth exposing
using the new generic module reset API. I believe Prashant Gaikwad is
working on converting the Tegra clock driver
Use common of_clk_init() function for clocks initialization.
Signed-off-by: Prashant Gaikwad
---
Included initialization for T114 in V2.
---
arch/arm/mach-tegra/common.c |4 ++--
drivers/clk/tegra/clk-tegra114.c |3 ++-
drivers/clk/tegra/clk-tegra20.c |3 ++-
drivers/clk
Use common of_clk_init() function for clocks initialization.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
Included initialization for T114 in V2.
---
arch/arm/mach-tegra/common.c |4 ++--
drivers/clk/tegra/clk-tegra114.c |3 ++-
drivers/clk/tegra/clk-tegra20.c |3
Use common of_clk_init() function for clocks initialization.
Signed-off-by: Prashant Gaikwad
---
Stephen, if T114 clock series is not going to make in 3.10 then I would
like Mike to take this patch. If T114 clock series makes it then I have
to rebase this patch on top of it.
---
arch/arm/mach
Register cdev1 and cdev2 peripheral clocks.
Signed-off-by: Prashant Gaikwad
---
drivers/clk/tegra/clk-tegra30.c | 18 ++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 0681935..0e362ea
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad
---
Stephen, tested this patch on Ventana and Cardhu, please verify if
I am not missing any platform which uses cdev1/cdev2.
---
.../bindings/clock/nvidia,tegra20-car.txt |4 ++--
arch/arm
On Wednesday 03 April 2013 07:49 PM, Peter De Schrijver wrote:
On Mon, Mar 25, 2013 at 12:15:47PM +0100, Prashant Gaikwad wrote:
On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider
On Wednesday 03 April 2013 07:49 PM, Peter De Schrijver wrote:
On Mon, Mar 25, 2013 at 12:15:47PM +0100, Prashant Gaikwad wrote:
On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
Stephen, tested this patch on Ventana and Cardhu, please verify if
I am not missing any platform which uses cdev1/cdev2.
---
.../bindings/clock/nvidia,tegra20-car.txt
Register cdev1 and cdev2 peripheral clocks.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
drivers/clk/tegra/clk-tegra30.c | 18 ++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index
Use common of_clk_init() function for clocks initialization.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
Stephen, if T114 clock series is not going to make in 3.10 then I would
like Mike to take this patch. If T114 clock series makes it then I have
to rebase this patch on top
Mike,
Please merge this patch.
Thanks & Regards,
PrashantG
On Wednesday 20 March 2013 05:30 PM, Prashant Gaikwad wrote:
Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types ins
On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.
Signed-off-by: Peter De Schrijver
---
+ 263 cclk_lp
+ 264 dfll_ref
+ 265 dfll_soc
+
Peter,
Please remove following
On Monday 25 March 2013 03:45 PM, Peter De Schrijver wrote:
On Fri, Mar 22, 2013 at 04:48:11PM +0100, Stephen Warren wrote:
On 03/22/2013 05:54 AM, Peter De Schrijver wrote:
The PLL code relies on udelay() which is not available when CCF is
initialized. Hence we can't enable any PLL during
On Monday 25 March 2013 03:45 PM, Peter De Schrijver wrote:
On Fri, Mar 22, 2013 at 04:48:11PM +0100, Stephen Warren wrote:
On 03/22/2013 05:54 AM, Peter De Schrijver wrote:
The PLL code relies on udelay() which is not available when CCF is
initialized. Hence we can't enable any PLL during
On Friday 22 March 2013 06:09 PM, Peter De Schrijver wrote:
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
snip
+ 263 cclk_lp
+ 264 dfll_ref
+ 265 dfll_soc
+
Peter,
Mike,
Please merge this patch.
Thanks Regards,
PrashantG
On Wednesday 20 March 2013 05:30 PM, Prashant Gaikwad wrote:
Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead
e-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.
Signed-off-by: Prashant Gaikwad
---
Changes from V2:
- Move clk_ops inside clk_composite instead of dynamically allocation.
---
drivers/clk/Makefile |1 +
drivers/c
the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
Changes from V2:
- Move clk_ops inside clk_composite instead of dynamically allocation.
---
drivers/clk/Makefile |1 +
drivers
On Wednesday 13 March 2013 10:00 PM, Tomasz Figa wrote:
Hi Prashant,
On Thursday 28 of February 2013 11:20:31 Stephen Warren wrote:
On 02/28/2013 12:58 AM, Prashant Gaikwad wrote:
On Wednesday 06 February 2013 03:36 PM, Tomasz Figa wrote:
On Wednesday 06 of February 2013 08:34:32 Prashant
On Wednesday 13 March 2013 10:00 PM, Tomasz Figa wrote:
Hi Prashant,
On Thursday 28 of February 2013 11:20:31 Stephen Warren wrote:
On 02/28/2013 12:58 AM, Prashant Gaikwad wrote:
On Wednesday 06 February 2013 03:36 PM, Tomasz Figa wrote:
On Wednesday 06 of February 2013 08:34:32 Prashant
On Wednesday 06 February 2013 03:36 PM, Tomasz Figa wrote:
On Wednesday 06 of February 2013 08:34:32 Prashant Gaikwad wrote:
On Tuesday 05 February 2013 03:45 PM, Tomasz Figa wrote:
Hi Prashant,
Thank you for your patch. Please see some comments inline.
On Monday 04 of February 2013 13:41:22
On Wednesday 06 February 2013 03:36 PM, Tomasz Figa wrote:
On Wednesday 06 of February 2013 08:34:32 Prashant Gaikwad wrote:
On Tuesday 05 February 2013 03:45 PM, Tomasz Figa wrote:
Hi Prashant,
Thank you for your patch. Please see some comments inline.
On Monday 04 of February 2013 13:41:22
branch for me to merge, obviously after 3.9-rc1 is out.
Thanks.
Prashant, could you provide a review/ack for this series too.
For the series
Reviewed-by: Prashant Gaikwad
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branch for me to merge, obviously after 3.9-rc1 is out.
Thanks.
Prashant, could you provide a review/ack for this series too.
For the series
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
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On Thursday 07 February 2013 10:07 PM, Peter De Schrijver wrote:
The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.
Signed-off-by: Peter De Schrijver
Reviewed-by: Prashant Gaikwad
---
drivers/clk/tegra/clk-tegra20.c | 11
On Thursday 07 February 2013 10:00 PM, Peter De Schrijver wrote:
cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within
clk-tegra30.c. Declare them static to avoid namespace polution.
Signed-off-by: Peter De Schrijver
Reviewed-by: Prashant Gaikwad
---
drivers/clk
On Thursday 07 February 2013 09:54 PM, Peter De Schrijver wrote:
Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
actually used by the code. Fixed with this patch.
Signed-off-by: Peter De Schrijver
Reviewed-by: Prashant Gaikwad
---
drivers/clk/tegra/clk
On Thursday 07 February 2013 09:54 PM, Peter De Schrijver wrote:
Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
actually used by the code. Fixed with this patch.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
Reviewed-by: Prashant Gaikwad pgaik
On Thursday 07 February 2013 10:00 PM, Peter De Schrijver wrote:
cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within
clk-tegra30.c. Declare them static to avoid namespace polution.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
Reviewed-by: Prashant
On Thursday 07 February 2013 10:07 PM, Peter De Schrijver wrote:
The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
On Wednesday 06 February 2013 11:40 AM, Hiroshi Doyu wrote:
Prashant Gaikwad wrote @ Wed, 6 Feb 2013 03:55:00 +0100:
No, clk_ops depends on the clocks you are using. There could be a clock
with mux and gate while another one with mux and div.
You are right. What about the following? We don't
On Wednesday 06 February 2013 11:40 AM, Hiroshi Doyu wrote:
Prashant Gaikwad pgaik...@nvidia.com wrote @ Wed, 6 Feb 2013 03:55:00 +0100:
No, clk_ops depends on the clocks you are using. There could be a clock
with mux and gate while another one with mux and div.
You are right. What about
On Tuesday 05 February 2013 08:35 PM, Thierry Reding wrote:
Commit 85a1819 (clk: sunxi: Use common of_clk_init() function) removed
the source file but didn't update the Makefile, therefore causing the
build to break on Allwinner A1X SoCs.
Signed-off-by: Thierry Reding
Thanks Thierry!!
---
On Tuesday 05 February 2013 03:45 PM, Tomasz Figa wrote:
Hi Prashant,
Thank you for your patch. Please see some comments inline.
On Monday 04 of February 2013 13:41:22 Prashant Gaikwad wrote:
Not all clocks are required to be decomposed into basic clock
types but at the same time want to use
On Tuesday 05 February 2013 03:52 PM, Hiroshi Doyu wrote:
Prashant Gaikwad wrote @ Tue, 5 Feb 2013 09:33:41 +0100:
The members of "clk_composite_ops" seems to be always assigned
statically. Istead of dynamically allocating/assigning, can't we just
have "clk_composite_ops"
On Monday 04 February 2013 03:07 PM, Hiroshi Doyu wrote:
Hi Prashant,
Prashant Gaikwad wrote @ Mon, 4 Feb 2013 09:11:22 +0100:
+struct clk *clk_register_composite(struct device *dev, const char *name,
+ const char **parent_names, int num_parents
On Monday 04 February 2013 03:07 PM, Hiroshi Doyu wrote:
Hi Prashant,
Prashant Gaikwad pgaik...@nvidia.com wrote @ Mon, 4 Feb 2013 09:11:22 +0100:
+struct clk *clk_register_composite(struct device *dev, const char *name,
+ const char **parent_names, int num_parents
On Tuesday 05 February 2013 03:52 PM, Hiroshi Doyu wrote:
Prashant Gaikwad pgaik...@nvidia.com wrote @ Tue, 5 Feb 2013 09:33:41 +0100:
The members of clk_composite_ops seems to be always assigned
statically. Istead of dynamically allocating/assigning, can't we just
have clk_composite_ops
On Tuesday 05 February 2013 03:45 PM, Tomasz Figa wrote:
Hi Prashant,
Thank you for your patch. Please see some comments inline.
On Monday 04 of February 2013 13:41:22 Prashant Gaikwad wrote:
Not all clocks are required to be decomposed into basic clock
types but at the same time want to use
On Tuesday 05 February 2013 08:35 PM, Thierry Reding wrote:
Commit 85a1819 (clk: sunxi: Use common of_clk_init() function) removed
the source file but didn't update the Makefile, therefore causing the
build to break on Allwinner A1X SoCs.
Signed-off-by: Thierry Reding
On Monday 04 February 2013 08:04 PM, Peter De Schrijver wrote:
On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote:
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
...
+ /* xusb_hs_src */
+ val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
+ val
On Monday 04 February 2013 08:02 PM, Peter De Schrijver wrote:
On Mon, Feb 04, 2013 at 07:06:47AM +0100, Prashant Gaikwad wrote:
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
...
-static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll
e-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.
Signed-off-by: Prashant Gaikwad
---
Changes from V1:
- 2nd patch dropped as the concept is acked by Mike.
- Fixed comments from Stephen.
---
drivers/clk/Makefile |1 +
drive
the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
Changes from V1:
- 2nd patch dropped as the concept is acked by Mike.
- Fixed comments from Stephen.
---
drivers/clk/Makefile
On Monday 04 February 2013 08:02 PM, Peter De Schrijver wrote:
On Mon, Feb 04, 2013 at 07:06:47AM +0100, Prashant Gaikwad wrote:
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
...
-static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll
On Monday 04 February 2013 08:04 PM, Peter De Schrijver wrote:
On Mon, Feb 04, 2013 at 08:08:55AM +0100, Prashant Gaikwad wrote:
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
...
+ /* xusb_hs_src */
+ val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
+ val
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Signed-off-by: Peter De Schrijver
---
Reviewed-by: Prashant Gaikwad
drivers/clk/tegra/clk.c |1 +
drivers/clk/tegra/clk.h |7 +++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/tegra
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Implement most clocks for Tegra114. The super clocks for the CPU complex
are still missing and will be implemented in a future version.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/Makefile |1 +
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Add references to tegra_car clocks for the basic device nodes.
Signed-off-by: Peter De Schrijver
---
Reviewed-by: Prashant Gaikwad
arch/arm/boot/dts/tegra114.dtsi |7 ++-
1 files changed, 6 insertions(+), 1
GRA_PERIPH_NO_RESET BIT(0)
#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
#define TEGRA_PERIPH_ON_APB BIT(2)
+#define TEGRA_PERIPH_WAR_1005168 BIT(3)
Comment for this flag, otherwise
Reviewed-by: Prashant Gaikwad
void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
ex
On Saturday 02 February 2013 01:10 AM, Rhyland Klein wrote:
On 2/1/2013 5:18 AM, Peter De Schrijver wrote:
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: Peter De Schrijver
---
drivers/clk/tegra/clk-pll.c |
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: Peter De Schrijver
---
Looks good to me.
Reviewed-by: Prashant
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver
---
Looks good to me.
Reviewed-by: Prashant Gaikwad
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver
---
Looks good to me.
Reviewed-by: Prashant Gaikwad
drivers/clk/tegra/clk-pll.c | 15
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.
The following changes were done:
* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.
The following changes were done:
* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
Looks good to me.
Reviewed-by: Prashant Gaikwad pgaik
-by: Prashant Gaikwad pgaik...@nvidia.com
drivers/clk/tegra/clk-pll.c | 38 --
drivers/clk/tegra/clk-tegra20.c |7 +++
drivers/clk/tegra/clk-tegra30.c |7 +++
drivers/clk/tegra/clk.h | 13 +
4 files changed, 59 insertions
.
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
drivers/clk/tegra/clk-periph.c | 11 ++-
drivers/clk/tegra/clk-tegra20.c |2 +-
drivers/clk/tegra/clk-tegra30.c |2 +-
drivers/clk/tegra/clk.h |9 ++---
4 files changed, 14 insertions(+), 10 deletions
On Saturday 02 February 2013 01:10 AM, Rhyland Klein wrote:
On 2/1/2013 5:18 AM, Peter De Schrijver wrote:
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
TEGRA_PERIPH_NO_RESET BIT(0)
#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
#define TEGRA_PERIPH_ON_APB BIT(2)
+#define TEGRA_PERIPH_WAR_1005168 BIT(3)
Comment for this flag, otherwise
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Add references to tegra_car clocks for the basic device nodes.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
arch/arm/boot/dts/tegra114.dtsi |7 ++-
1
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Implement most clocks for Tegra114. The super clocks for the CPU complex
are still missing and will be implemented in a future version.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/Makefile
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
Reviewed-by: Prashant Gaikwad pgaik...@nvidia.com
drivers/clk/tegra/clk.c |1 +
drivers/clk/tegra/clk.h |7 +++
2 files changed, 8 insertions(+), 0
On Friday 25 January 2013 10:14 AM, Stephen Warren wrote:
On 01/24/2013 04:57 PM, Mike Turquette wrote:
Quoting Stephen Warren (2013-01-24 11:32:37)
On 01/24/2013 11:20 AM, Mike Turquette wrote:
Quoting Prashant Gaikwad (2013-01-04 18:44:48)
On Friday 04 January 2013 10:00 PM, Stephen Warren
On Friday 25 January 2013 10:14 AM, Stephen Warren wrote:
On 01/24/2013 04:57 PM, Mike Turquette wrote:
Quoting Stephen Warren (2013-01-24 11:32:37)
On 01/24/2013 11:20 AM, Mike Turquette wrote:
Quoting Prashant Gaikwad (2013-01-04 18:44:48)
On Friday 04 January 2013 10:00 PM, Stephen Warren
these clocks.
This binding is only useful for Tegra20; the set of clocks that exists on
Tegra30 is sufficiently different to merit its own binding.
Signed-off-by: Stephen Warren
Acked-by: Simon Glass
[pgaikwad: Added mux clk ids and sorted CAR node]
Signed-off-by: Prashant Gaikwad
---
.../bindings
Add tegra20 clock support based on common clock framework.
Signed-off-by: Prashant Gaikwad
---
drivers/clk/tegra/Makefile |2 +
drivers/clk/tegra/clk-tegra20.c | 1255 +++
drivers/clk/tegra/clk.h |6 +
3 files changed, 1263 insertions
tegra_cpu_car_ops struct is going to be accessed from drivers/clk/tegra.
Move the tegra_cpu_car_ops to include/linux/clk/tegra.h.
Signed-off-by: Prashant Gaikwad
---
arch/arm/mach-tegra/clock.c|2 +-
arch/arm/mach-tegra/cpuidle-tegra30.c |2 +-
arch
of mach/clk.h
Signed-off-by: Prashant Gaikwad
---
arch/arm/mach-tegra/board-dt-tegra20.c | 30 -
arch/arm/mach-tegra/board-dt-tegra30.c | 31 --
arch/arm/mach-tegra/clock.c| 19 -
arch/arm/mach-tegra/common.c | 44
The device tree binding models Tegra30 CAR (Clock And Reset)
as a single monolithic clock provider.
Signed-off-by: Prashant Gaikwad
---
.../bindings/clock/nvidia,tegra30-car.txt | 262
arch/arm/boot/dts/tegra30.dtsi |6 +
2 files changed
.
Fixed some issues reported by Joseph Lo.
Added function to read chip id revision register.
Changes from v1:
Rebased on linux-next for 20121224.
Prashant Gaikwad (8):
ARM: tegra: Add function to read chipid
clk: tegra: Add tegra specific clocks
arm: tegra: Move tegra_cpu_car.h to linux/clk
Add function to read chip id from APB MISC registers. This function
will also get called from clock driver to flush write operations on
apb bus.
Signed-off-by: Prashant Gaikwad
---
arch/arm/mach-tegra/fuse.c |8 +++-
include/linux/tegra-soc.h | 22 ++
2 files
On Friday 11 January 2013 01:23 AM, Josh Cartwright wrote:
* PGP Signed by an unknown key
On Fri, Jan 04, 2013 at 12:30:52PM +0530, Prashant Gaikwad wrote:
Modify of_clk_init function so that it will determine which
driver to initialize based on device tree instead of each driver
registering
On Friday 11 January 2013 01:23 AM, Josh Cartwright wrote:
* PGP Signed by an unknown key
On Fri, Jan 04, 2013 at 12:30:52PM +0530, Prashant Gaikwad wrote:
Modify of_clk_init function so that it will determine which
driver to initialize based on device tree instead of each driver
registering
.
Fixed some issues reported by Joseph Lo.
Added function to read chip id revision register.
Changes from v1:
Rebased on linux-next for 20121224.
Prashant Gaikwad (8):
ARM: tegra: Add function to read chipid
clk: tegra: Add tegra specific clocks
arm: tegra: Move tegra_cpu_car.h to linux/clk
Add function to read chip id from APB MISC registers. This function
will also get called from clock driver to flush write operations on
apb bus.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
arch/arm/mach-tegra/fuse.c |8 +++-
include/linux/tegra-soc.h | 22
The device tree binding models Tegra30 CAR (Clock And Reset)
as a single monolithic clock provider.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
.../bindings/clock/nvidia,tegra30-car.txt | 262
arch/arm/boot/dts/tegra30.dtsi |6
of mach/clk.h
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
arch/arm/mach-tegra/board-dt-tegra20.c | 30 -
arch/arm/mach-tegra/board-dt-tegra30.c | 31 --
arch/arm/mach-tegra/clock.c| 19 -
arch/arm/mach-tegra/common.c
tegra_cpu_car_ops struct is going to be accessed from drivers/clk/tegra.
Move the tegra_cpu_car_ops to include/linux/clk/tegra.h.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
arch/arm/mach-tegra/clock.c|2 +-
arch/arm/mach-tegra/cpuidle-tegra30.c
Add tegra20 clock support based on common clock framework.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
drivers/clk/tegra/Makefile |2 +
drivers/clk/tegra/clk-tegra20.c | 1255 +++
drivers/clk/tegra/clk.h |6 +
3 files changed
]
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
.../bindings/clock/nvidia,tegra20-car.txt | 205
arch/arm/boot/dts/tegra20.dtsi |6 +
2 files changed, 211 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree
On Friday 04 January 2013 09:55 PM, Stephen Warren wrote:
On 01/03/2013 10:51 PM, Prashant Gaikwad wrote:
Convert clk out to composite clock type which removes
the mux clock.
Signed-off-by: Prashant Gaikwad
---
This patch is rebased on ccf-rework for Tegra patch series. It is just to show
how
On Saturday 05 January 2013 03:48 AM, Stephen Boyd wrote:
On 01/03/13 21:51, Prashant Gaikwad wrote:
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f0b269a..baf7608 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -2,7 +2,8 @@
obj-$(CONFIG_HAVE_CLK
On Friday 04 January 2013 10:00 PM, Stephen Warren wrote:
On 01/04/2013 12:00 AM, Prashant Gaikwad wrote:
Use common of_clk_init() function for clocks initialization.
drivers/clk/tegra/clk-tegra20.c |3 ++-
drivers/clk/tegra/clk-tegra30.c |3 ++-
Oh, so this series is written
Configlink clock information is added to device tree. Get the clocks
using device node. Remove AUXDATA.
Signed-off-by: Prashant Gaikwad
---
sound/soc/tegra/tegra30_ahub.c | 14 ++
1 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/sound/soc/tegra/tegra30_ahub.c b
With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.
Signed-off-by: Prashant Gaikwad
---
drivers/clk/tegra/clk-tegra30.c | 34 --
1 files changed, 0 insertions(+), 34 deletions(-)
diff --git
Remove AUXDATA as clocks are initialized from device node.
Signed-off-by: Prashant Gaikwad
---
arch/arm/mach-tegra/board-dt-tegra30.c | 31 +--
1 files changed, 1 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c
b/arch/arm/mach
Add clock information to device nodes.
Signed-off-by: Prashant Gaikwad
---
arch/arm/boot/dts/tegra30.dtsi | 52 +++-
1 files changed, 51 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index
With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.
Signed-off-by: Prashant Gaikwad
---
drivers/clk/tegra/clk-tegra20.c | 17 -
1 files changed, 0 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/tegra
Remove AUXDATA as clock are initialized from device node.
Signed-off-by: Prashant Gaikwad
---
arch/arm/mach-tegra/board-dt-tegra20.c | 24
1 files changed, 0 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c
b/arch/arm/mach-tegra
Add clock information to device nodes.
Signed-off-by: Prashant Gaikwad
---
Tested on Ventana (Tegra20) and Cardhu (Tegra30).
This series depends on ccf-rework patch series.
---
arch/arm/boot/dts/tegra20.dtsi | 41
1 files changed, 41 insertions(+), 0
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