Re: [PATCH] KVM: LAPIC: Level-sensitive interrupts are not support for LINT1

ver.). > This patch avoids the software too fool to set the level-sensitive trigger > mode > to LVT LINT1 register. The software should see the value it writes, though, so the current behavior is better. Do we hit a KVM bug if the software uses APIC_LVT_LEVEL_TRIGGER? Thanks. > Cc: Paolo Bo

Re: [PATCH v2 4/4] KVM: LAPIC: Don't silently accept bad vectors

2017-10-13 19:36+0200, Radim Krčmář: > 2017-10-13 09:17+0800, Wanpeng Li: > > 2017-10-04 22:44 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > > 2017-10-04 22:16+0800, Wanpeng Li: > > >> 2017-10-04 20:01 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>:

Re: [PATCH v2 4/4] KVM: LAPIC: Don't silently accept bad vectors

2017-10-13 19:36+0200, Radim Krčmář: > 2017-10-13 09:17+0800, Wanpeng Li: > > 2017-10-04 22:44 GMT+08:00 Radim Krčmář : > > > 2017-10-04 22:16+0800, Wanpeng Li: > > >> 2017-10-04 20:01 GMT+08:00 Radim Krčmář : > > >> > 2017-10-04 15:56+0800, Wanpeng

Re: [PATCH v2 4/4] KVM: LAPIC: Don't silently accept bad vectors

2017-10-13 09:17+0800, Wanpeng Li: > 2017-10-04 22:44 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > 2017-10-04 22:16+0800, Wanpeng Li: > >> 2017-10-04 20:01 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > >> > 2017-10-04 15:56+0800, Wanpeng Li: >

Re: [PATCH v2 4/4] KVM: LAPIC: Don't silently accept bad vectors

2017-10-13 09:17+0800, Wanpeng Li: > 2017-10-04 22:44 GMT+08:00 Radim Krčmář : > > 2017-10-04 22:16+0800, Wanpeng Li: > >> 2017-10-04 20:01 GMT+08:00 Radim Krčmář : > >> > 2017-10-04 15:56+0800, Wanpeng Li: > >> >> 2017-10-04 1:53 GMT+08:00 Radim Krčm

Re: [PATCH v3 1/2] KVM: X86: Processor States following Reset or INIT

2017-10-11 08:39+0800, Wanpeng Li: > 2017-10-11 2:55 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > 2017-10-09 15:51-0700, Wanpeng Li: > >> From: Wanpeng Li <wanpeng...@hotmail.com> > >> > >> - XCR0 is reset to 1 by RESET but not INIT > >&

Re: [PATCH v3 1/2] KVM: X86: Processor States following Reset or INIT

2017-10-11 08:39+0800, Wanpeng Li: > 2017-10-11 2:55 GMT+08:00 Radim Krčmář : > > 2017-10-09 15:51-0700, Wanpeng Li: > >> From: Wanpeng Li > >> > >> - XCR0 is reset to 1 by RESET but not INIT > >> - XSS is zeroed by both RESET and INIT > >>

Re: [PATCH] KVM: SVM: unconditionally wake up VCPU on IOMMU interrupt

gt; > In practice it's safe because spin_lock has full-barrier semantics on x86, > but don't be too clever. > > Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> > --- Reviewed-by: Radim Krčmář <rkrc...@redhat.com>

Re: [PATCH] KVM: SVM: unconditionally wake up VCPU on IOMMU interrupt

gt; > In practice it's safe because spin_lock has full-barrier semantics on x86, > but don't be too clever. > > Signed-off-by: Paolo Bonzini > --- Reviewed-by: Radim Krčmář

Re: [PATCH] KVM: x86: extend usage of RET_MMIO_PF_* constants

u32 error_code, > out_unlock: > spin_unlock(>kvm->mmu_lock); > kvm_release_pfn_clean(pfn); > - return 0; > + return RET_PF_EMULATE; A direct conversion would return RET_PF_RETRY, is this some optimization? Apart from that, Reviewed-by: Radim Krčmář <rkrc...@redhat.com> Thanks.

Re: [PATCH] KVM: x86: extend usage of RET_MMIO_PF_* constants

rror_code, > out_unlock: > spin_unlock(>kvm->mmu_lock); > kvm_release_pfn_clean(pfn); > - return 0; > + return RET_PF_EMULATE; A direct conversion would return RET_PF_RETRY, is this some optimization? Apart from that, Reviewed-by: Radim Krčmář Thanks.

Re: [PATCH] KVM: SVM: limit kvm_handle_page_fault to #PF handling

e VMX > does in handle_ept_violation and handle_ept_misconfig. > > Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> > --- And we also drop the unneeded pv async_pf switch, Reviewed-by: Radim Krčmář <rkrc...@redhat.com>

Re: [PATCH] KVM: SVM: limit kvm_handle_page_fault to #PF handling

e VMX > does in handle_ept_violation and handle_ept_misconfig. > > Signed-off-by: Paolo Bonzini > --- And we also drop the unneeded pv async_pf switch, Reviewed-by: Radim Krčmář

Re: [PATCH v3 1/2] KVM: X86: Processor States following Reset or INIT

ding to SDM. > > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > Cc: Jim Mattson <jmatt...@google.com> > Signed-off-by: Wanpeng Li <wanpeng...@hotmail.com> > --- > v2 -> v3: > * fix null pointer deference > * fi

Re: [PATCH v3 1/2] KVM: X86: Processor States following Reset or INIT

2017-10-09 15:51-0700, Wanpeng Li: > From: Wanpeng Li > > - XCR0 is reset to 1 by RESET but not INIT > - XSS is zeroed by both RESET and INIT > - BNDCFGU, BND0-BND3, BNDCFGS are zeroed by both RESET and INIT > > This patch does this according to SDM. > > Cc: Paolo

[GIT PULL] KVM fixes for v4.14-rc4

Linus, The following changes since commit 9e66317d3c92ddaab330c125dfe9d06eee268aff: Linux 4.14-rc3 (2017-10-01 14:54:54 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/virt/kvm/kvm tags/for-linus for you to fetch changes up to

[GIT PULL] KVM fixes for v4.14-rc4

Linus, The following changes since commit 9e66317d3c92ddaab330c125dfe9d06eee268aff: Linux 4.14-rc3 (2017-10-01 14:54:54 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/virt/kvm/kvm tags/for-linus for you to fetch changes up to

[PATCH 1/3] KVM: x86: handle 0 write to TSC_DEADLINE MSR

0 should disable the timer, but start_hv_timer will recognize it as an expired timer instead. Signed-off-by: Radim Krčmář <rkrc...@redhat.com> --- arch/x86/kvm/lapic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 2c9e88

[PATCH 1/3] KVM: x86: handle 0 write to TSC_DEADLINE MSR

0 should disable the timer, but start_hv_timer will recognize it as an expired timer instead. Signed-off-by: Radim Krčmář --- arch/x86/kvm/lapic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 2c9e88a82738..39c1ae11ce1d 100644

[PATCH 0/3] KVM: x86: fix restart_apic_timer

Various bugs that incorrectly injected a timer interrupt. Going to work on kvm-unit-tests for this too. Radim Krčmář (3): KVM: x86: handle 0 write to TSC_DEADLINE MSR KVM: x86: really disarm lapic timer when clearing TMICT KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch

[PATCH 2/3] KVM: x86: really disarm lapic timer when clearing TMICT

preemption timer only looks at tscdeadline and could inject already disarmed timer. Signed-off-by: Radim Krčmář <rkrc...@redhat.com> --- arch/x86/kvm/lapic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 39c1ae

[PATCH 0/3] KVM: x86: fix restart_apic_timer

Various bugs that incorrectly injected a timer interrupt. Going to work on kvm-unit-tests for this too. Radim Krčmář (3): KVM: x86: handle 0 write to TSC_DEADLINE MSR KVM: x86: really disarm lapic timer when clearing TMICT KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch

[PATCH 2/3] KVM: x86: really disarm lapic timer when clearing TMICT

preemption timer only looks at tscdeadline and could inject already disarmed timer. Signed-off-by: Radim Krčmář --- arch/x86/kvm/lapic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 39c1ae11ce1d..96ade848ae0b 100644

[PATCH] KVM: x86: remove X86_LOCAL_APIC #ifdefs

f478e1219ea1 ("KVM: add X86_LOCAL_APIC dependency") made only the defined path possible. Signed-off-by: Radim Krčmář <rkrc...@redhat.com> --- arch/x86/kvm/svm.c | 5 + arch/x86/kvm/vmx.c | 3 +-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/svm.

[PATCH] KVM: x86: remove X86_LOCAL_APIC #ifdefs

f478e1219ea1 ("KVM: add X86_LOCAL_APIC dependency") made only the defined path possible. Signed-off-by: Radim Krčmář --- arch/x86/kvm/svm.c | 5 + arch/x86/kvm/vmx.c | 3 +-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/s

[PATCH 3/3] KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch

Our routines look at tscdeadline and period when deciding state of a timer. The timer is disarmed when switching between TSC deadline and other modes, so we should set everything to disarmed state. Signed-off-by: Radim Krčmář <rkrc...@redhat.com> --- arch/x86/kvm/lapic.c | 4 +++-

[PATCH 3/3] KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch

Our routines look at tscdeadline and period when deciding state of a timer. The timer is disarmed when switching between TSC deadline and other modes, so we should set everything to disarmed state. Signed-off-by: Radim Krčmář --- arch/x86/kvm/lapic.c | 4 +++- 1 file changed, 3 insertions

Re: [PATCH v8] KVM: LAPIC: Apply change to TDCR right away to the timer

on to APIC timer to so that a change to the > divide configuration would be reflected in the value of the counter and > when the next interrupt is triggered. > > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > Sig

Re: [PATCH v8] KVM: LAPIC: Apply change to TDCR right away to the timer

the > divide configuration would be reflected in the value of the counter and > when the next interrupt is triggered. > > Cc: Paolo Bonzini > Cc: Radim Krčmář > Signed-off-by: Wanpeng Li > --- > arch/x86/kvm/lapic.c | 31 +-- > 1 file

Re: [PATCH v6 2/3] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

2017-10-06 15:17+0200, Radim Krčmář: > 2017-10-05 18:54-0700, Wanpeng Li: > > From: Wanpeng Li <wanpeng...@hotmail.com> > > > > If we take TSC-deadline mode timer out of the picture, the Intel SDM > > does not say that the timer is disable when the timer mode is

Re: [PATCH v6 2/3] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

2017-10-06 15:17+0200, Radim Krčmář: > 2017-10-05 18:54-0700, Wanpeng Li: > > From: Wanpeng Li > > > > If we take TSC-deadline mode timer out of the picture, the Intel SDM > > does not say that the timer is disable when the timer mode is change, > > either from o

Re: [PATCH v8] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-06 16:51+0200, Paolo Bonzini: > On 06/10/2017 16:38, Wanpeng Li wrote: > > + now = ktime_get(); > > + remaining = ktime_sub(apic->lapic_timer.target_expiration, now); > > Still need to compare against zero here. I guess Radim can do it. I added the expression from v7 while applying,

Re: [PATCH v8] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-06 16:51+0200, Paolo Bonzini: > On 06/10/2017 16:38, Wanpeng Li wrote: > > + now = ktime_get(); > > + remaining = ktime_sub(apic->lapic_timer.target_expiration, now); > > Still need to compare against zero here. I guess Radim can do it. I added the expression from v7 while applying,

Re: [PATCH v5 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-06 22:03+0800, Wanpeng Li: > 2017-10-06 21:03 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > 2017-10-06 07:14+0800, Wanpeng Li: > >> 2017-10-06 2:14 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > >> > 2017-10-05 07:35-0700, Wanpeng Li: > &

Re: [PATCH v5 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-06 22:03+0800, Wanpeng Li: > 2017-10-06 21:03 GMT+08:00 Radim Krčmář : > > 2017-10-06 07:14+0800, Wanpeng Li: > >> 2017-10-06 2:14 GMT+08:00 Radim Krčmář : > >> > 2017-10-05 07:35-0700, Wanpeng Li: > >> >> From: Wanpeng Li > >>

Re: [PATCH v6 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-06 21:59+0800, Wanpeng Li: > 2017-10-06 21:14 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > 2017-10-05 18:54-0700, Wanpeng Li: > >> From: Wanpeng Li <wanpeng...@hotmail.com> > >> > >> The description in the Intel SDM of how the divide conf

Re: [PATCH v6 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-06 21:59+0800, Wanpeng Li: > 2017-10-06 21:14 GMT+08:00 Radim Krčmář : > > 2017-10-05 18:54-0700, Wanpeng Li: > >> From: Wanpeng Li > >> > >> The description in the Intel SDM of how the divide configuration > >> register is used: "Th

Re: [PATCH v6 2/3] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

ion > written in the Intel SDM. > > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > Signed-off-by: Wanpeng Li <wanpeng...@hotmail.com> > --- > arch/x86/kvm/lapic.c | 8 ++-- > 1 file changed, 6 insertions(+), 2 deletio

Re: [PATCH v6 2/3] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

the counter should restard counting > down from TMICT (so periodic mode) or stop counting (if one-shot mode). > > This patch is based on observation of the behavior of the APIC timer on > baremetal as well as check that they does not go against the description > written in the In

Re: [PATCH v6 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

on to APIC timer to so that a change to the > divide configuration would be reflected in the value of the counter and > when the next interrupt is triggered. > > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > Signed-off-by: Wanpeng Li <wan

Re: [PATCH v6 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

the > divide configuration would be reflected in the value of the counter and > when the next interrupt is triggered. > > Cc: Paolo Bonzini > Cc: Radim Krčmář > Signed-off-by: Wanpeng Li > --- > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c >

Re: [PATCH v5 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-06 07:14+0800, Wanpeng Li: > 2017-10-06 2:14 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > 2017-10-05 07:35-0700, Wanpeng Li: > >> From: Wanpeng Li <wanpeng...@hotmail.com> > >> + remaining = ktime_sub(apic-&g

Re: [PATCH v5 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-06 07:14+0800, Wanpeng Li: > 2017-10-06 2:14 GMT+08:00 Radim Krčmář : > > 2017-10-05 07:35-0700, Wanpeng Li: > >> From: Wanpeng Li > >> + remaining = ktime_sub(apic->lapic_timer.target_expiration, > >> now); > >&

Re: [PATCH] kvm/x86: Avoid async PF to end RCU read-side critical section early in PREEMPT=n kernel

2017-10-06 09:33+0800, Boqun Feng: > On Tue, Oct 03, 2017 at 02:11:08PM +, Paolo Bonzini wrote: > > I'd prefer a slight change in subject and topic: > > > > --- 8< > > Subject: [PATCH] kvm/x86: Avoid async PF preempting the kernel incorrectly > > > > Currently, in

Re: [PATCH] kvm/x86: Avoid async PF to end RCU read-side critical section early in PREEMPT=n kernel

2017-10-06 09:33+0800, Boqun Feng: > On Tue, Oct 03, 2017 at 02:11:08PM +, Paolo Bonzini wrote: > > I'd prefer a slight change in subject and topic: > > > > --- 8< > > Subject: [PATCH] kvm/x86: Avoid async PF preempting the kernel incorrectly > > > > Currently, in

Re: [PATCH v5 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

on to APIC timer to so that a change to the > divide configuration would be reflected in the value of the counter and > when the next interrupt is triggered. > > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > Signed-off-by: Wanpeng Li <wan

Re: [PATCH v5 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

the > divide configuration would be reflected in the value of the counter and > when the next interrupt is triggered. > > Cc: Paolo Bonzini > Cc: Radim Krčmář > Signed-off-by: Wanpeng Li > --- > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > @@ -1474,

Re: [PATCH v2] tools/kvm_stat: Add Python 3 support to kvm_stat

2017-10-04 03:08+, Jeremy Cline: > Make kvm_stat support Python 3 by changing the use of "print" to a > function rather than a statement, switching from "iteritems" and > "iterkeys" (removed in Python 3) to "items" and "keys" respectively, > and decoding bytes to strings when dealing with

Re: [PATCH v2] tools/kvm_stat: Add Python 3 support to kvm_stat

2017-10-04 03:08+, Jeremy Cline: > Make kvm_stat support Python 3 by changing the use of "print" to a > function rather than a statement, switching from "iteritems" and > "iterkeys" (removed in Python 3) to "items" and "keys" respectively, > and decoding bytes to strings when dealing with

Re: [PATCH] KVM: add X86_LOCAL_APIC dependency

2017-10-04 12:28+0200, Arnd Bergmann: > The rework of the posted interrupt handling broke building without > support for the local APIC: > > ERROR: "boot_cpu_physical_apicid" [arch/x86/kvm/kvm-intel.ko] undefined! > > That configuration is probably not particularly useful anyway, so > we can

Re: [PATCH] KVM: add X86_LOCAL_APIC dependency

2017-10-04 12:28+0200, Arnd Bergmann: > The rework of the posted interrupt handling broke building without > support for the local APIC: > > ERROR: "boot_cpu_physical_apicid" [arch/x86/kvm/kvm-intel.ko] undefined! > > That configuration is probably not particularly useful anyway, so > we can

Re: [PATCH v3 2/3] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

ion > written in the Intel SDM. > > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > Signed-off-by: Wanpeng Li <wanpeng...@hotmail.com> > --- > arch/x86/kvm/lapic.c | 45 +++-- > 1 f

Re: [PATCH v3 2/3] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

the counter should restard counting > down from TMICT (so periodic mode) or stop counting (if one-shot mode). > > This patch is based on observation of the behavior of the APIC timer on > baremetal as well as check that they does not go against the description > written in the In

Re: [PATCH v2 4/4] KVM: LAPIC: Don't silently accept bad vectors

2017-10-04 22:16+0800, Wanpeng Li: > 2017-10-04 20:01 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > 2017-10-04 15:56+0800, Wanpeng Li: > >> 2017-10-04 1:53 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > >> > 2017-09-28 18:04-0700, Wanpeng L

Re: [PATCH v2 4/4] KVM: LAPIC: Don't silently accept bad vectors

2017-10-04 22:16+0800, Wanpeng Li: > 2017-10-04 20:01 GMT+08:00 Radim Krčmář : > > 2017-10-04 15:56+0800, Wanpeng Li: > >> 2017-10-04 1:53 GMT+08:00 Radim Krčmář : > >> > 2017-09-28 18:04-0700, Wanpeng Li: > >> >> @@ -946,6 +965,11 @@ static int __ap

Re: [PATCH v2 2/4] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

2017-10-04 09:46+0800, Wanpeng Li: > 2017-10-04 1:06 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > 2017-09-28 18:04-0700, Wanpeng Li: > >> From: Wanpeng Li <wanpeng...@hotmail.com> > >> > >> If we take TSC-deadline mode timer out of the picture

Re: [PATCH v2 2/4] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

2017-10-04 09:46+0800, Wanpeng Li: > 2017-10-04 1:06 GMT+08:00 Radim Krčmář : > > 2017-09-28 18:04-0700, Wanpeng Li: > >> From: Wanpeng Li > >> > >> If we take TSC-deadline mode timer out of the picture, the Intel SDM > >> does not say that the t

Re: [PATCH v2 1/4] KVM: LAPIC: Fix lapic timer mode transition

2017-10-04 09:45+0800, Wanpeng Li: > 2017-10-04 1:05 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > 2017-09-28 18:04-0700, Wanpeng Li: > >> From: Wanpeng Li <wanpeng...@hotmail.com> > >> > >> SDM 10.5.4.1 TSC-Deadline Mode mentioned that &qu

Re: [PATCH v2 1/4] KVM: LAPIC: Fix lapic timer mode transition

2017-10-04 09:45+0800, Wanpeng Li: > 2017-10-04 1:05 GMT+08:00 Radim Krčmář : > > 2017-09-28 18:04-0700, Wanpeng Li: > >> From: Wanpeng Li > >> > >> SDM 10.5.4.1 TSC-Deadline Mode mentioned that "Transitioning between > >> TSC-Deadline > >

Re: [PATCH v2 3/4] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-04 09:59+0800, Wanpeng Li: > 2017-10-04 1:28 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > 2017-09-28 18:04-0700, Wanpeng Li: > >> From: Wanpeng Li <wanpeng...@hotmail.com> > >> > >> The description in the Intel SDM of how the divide conf

Re: [PATCH v2 3/4] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-04 09:59+0800, Wanpeng Li: > 2017-10-04 1:28 GMT+08:00 Radim Krčmář : > > 2017-09-28 18:04-0700, Wanpeng Li: > >> From: Wanpeng Li > >> > >> The description in the Intel SDM of how the divide configuration > >> register is used: "Th

Re: [PATCH v2 4/4] KVM: LAPIC: Don't silently accept bad vectors

2017-10-04 15:56+0800, Wanpeng Li: > 2017-10-04 1:53 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>: > > 2017-09-28 18:04-0700, Wanpeng Li: > >> From: Wanpeng Li <wanpeng...@hotmail.com> > >> > >> Vectors 0-15 are reserved, and a physical LAPIC - upo

Re: [PATCH v2 4/4] KVM: LAPIC: Don't silently accept bad vectors

2017-10-04 15:56+0800, Wanpeng Li: > 2017-10-04 1:53 GMT+08:00 Radim Krčmář : > > 2017-09-28 18:04-0700, Wanpeng Li: > >> From: Wanpeng Li > >> > >> Vectors 0-15 are reserved, and a physical LAPIC - upon sending or > >> receiving one -

Re: [PATCH v2 4/4] KVM: LAPIC: Don't silently accept bad vectors

gt; > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > Signed-off-by: Wanpeng Li <wanpeng...@hotmail.com> > --- > arch/x86/kvm/lapic.c | 30 -- > 1 file changed, 28 insertions(+), 2 deletions(-) &

Re: [PATCH v2 4/4] KVM: LAPIC: Don't silently accept bad vectors

2017-09-28 18:04-0700, Wanpeng Li: > From: Wanpeng Li > > Vectors 0-15 are reserved, and a physical LAPIC - upon sending or > receiving one - would generate an APIC error instead of doing the > requested action. Make our emulation behave similarly. > > Cc: Paolo Bonzin

Re: [PATCH v2 3/4] KVM: LAPIC: Apply change to TDCR right away to the timer

on to APIC timer to so that a change to the > divide configuration would be reflected in the value of the counter and > when the next interrupt is triggered. > > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > Signed-off-by: Wanpeng Li <

Re: [PATCH v2 3/4] KVM: LAPIC: Apply change to TDCR right away to the timer

the > divide configuration would be reflected in the value of the counter and > when the next interrupt is triggered. > > Cc: Paolo Bonzini > Cc: Radim Krčmář > Signed-off-by: Wanpeng Li > --- Why do we need to do more than just restart the timer? The TMCCT should

Re: [PATCH v2 2/4] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

check that they does not go against the description > written in the Intel SDM. > > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > Signed-off-by: Wanpeng Li <wanpeng...@hotmail.com> > --- > arch/x86/kvm/lapic.c | 40

Re: [PATCH v2 2/4] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode

gainst the description > written in the Intel SDM. > > Cc: Paolo Bonzini > Cc: Radim Krčmář > Signed-off-by: Wanpeng Li > --- > arch/x86/kvm/lapic.c | 40 > 1 file changed, 28 insertions(+), 12 deletions(-) > > diff --git a/

Re: [PATCH v2 1/4] KVM: LAPIC: Fix lapic timer mode transition

timer are mutually exclusive. So we should also disarm when switching between one-shot and periodic. apic_update_lvtt() already has logic to determine whether the timer mode has changed and is the perfect place to clear APIC_TMICT. Thanks. > Cc: Paolo Bonzini <pbonz...@redhat.com> > C

Re: [PATCH v2 1/4] KVM: LAPIC: Fix lapic timer mode transition

So we should also disarm when switching between one-shot and periodic. apic_update_lvtt() already has logic to determine whether the timer mode has changed and is the perfect place to clear APIC_TMICT. Thanks. > Cc: Paolo Bonzini > Cc: Radim Krčmář > Signed-off-by: Wanpeng Li >

[GIT PULL] KVM fixes for v4.14-rc2

Linus, The following changes since commit 2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e: Linux 4.14-rc1 (2017-09-16 15:47:51 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/virt/kvm/kvm for-linus for you to fetch changes up to

[GIT PULL] KVM fixes for v4.14-rc2

Linus, The following changes since commit 2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e: Linux 4.14-rc1 (2017-09-16 15:47:51 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/virt/kvm/kvm for-linus for you to fetch changes up to

Re: [PATCH v2] KVM: async_pf: Fix #DF due to inject "Page not Present" and "Page Ready" exceptions simultaneously

> and shadow page table has already been fixed by "Page Ready" handler. > > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > Signed-off-by: Wanpeng Li <wanpeng...@hotmail.com> > --- > diff --git a/arch/x86/kvm

Re: [PATCH v2] KVM: async_pf: Fix #DF due to inject "Page not Present" and "Page Ready" exceptions simultaneously

currently just override them anyway, so we wouldn't regress. :) > This patch fixes it by clearing the queue for "Page not Present" if "Page > Ready" > occurs before the next vmentry since the GUP has already got the required > page > and shadow page table h

Re: [PATCH v2 3/3] KVM: SVM: Add irqchip_split() checks before enabling AVIC

2017-09-12 10:42-0500, Suravee Suthikulpanit: > SVM AVIC hardware accelerates guest write to APIC_EOI register > (for edge-trigger interrupt), which means it does not trap to KVM. > > So, only enable SVM AVIC only in split irqchip mode. > (e.g. launching qemu w/ option '-machine

Re: [PATCH v2 3/3] KVM: SVM: Add irqchip_split() checks before enabling AVIC

2017-09-12 10:42-0500, Suravee Suthikulpanit: > SVM AVIC hardware accelerates guest write to APIC_EOI register > (for edge-trigger interrupt), which means it does not trap to KVM. > > So, only enable SVM AVIC only in split irqchip mode. > (e.g. launching qemu w/ option '-machine

Re: [PATCH] KVM: x86: Remove .get_pkru() from kvm_x86_ops

2017-08-28 16:38+0200, Joerg Roedel: > From: Joerg Roedel > > The commit > > 9dd21e104bc ('KVM: x86: simplify handling of PKRU') > > removed all users and providers of that call-back, but > didn't remove it. Remove it now. > > Signed-off-by: Joerg Roedel

Re: [PATCH] KVM: x86: Remove .get_pkru() from kvm_x86_ops

2017-08-28 16:38+0200, Joerg Roedel: > From: Joerg Roedel > > The commit > > 9dd21e104bc ('KVM: x86: simplify handling of PKRU') > > removed all users and providers of that call-back, but > didn't remove it. Remove it now. > > Signed-off-by: Joerg Roedel > --- Applied, thanks.

Re: [RESEND][PATCH] kvm: x86: Do not handle MMIO request in fast_page_fault

2017-09-05 18:37+0800, changbin...@intel.com: > From: Changbin Du > > If it is a MMIO request, it should be handled by slow path. This patch > actually fixed below warning when mmu debug is enabled. > > WARNING: CPU: 5 PID: 2282 at arch/x86/kvm/mmu.c:226 >

Re: [RESEND][PATCH] kvm: x86: Do not handle MMIO request in fast_page_fault

2017-09-05 18:37+0800, changbin...@intel.com: > From: Changbin Du > > If it is a MMIO request, it should be handled by slow path. This patch > actually fixed below warning when mmu debug is enabled. > > WARNING: CPU: 5 PID: 2282 at arch/x86/kvm/mmu.c:226 > fast_page_fault+0x41b/0x520 > CPU: 5

Re: [PATCH] KVM: SVM: Do not issue virtual VMLOAD/VMSAVE supported-message

t; > Cc: Janakarajan Natarajan <janakarajan.natara...@amd.com> > Cc: Paolo Bonzini <pbonz...@redhat.com> > Cc: Radim Krčmář <rkrc...@redhat.com> > --- > arch/x86/kvm/svm.c | 5 + > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/arch/x86/kvm/svm.c b/a

Re: [PATCH] KVM: SVM: Do not issue virtual VMLOAD/VMSAVE supported-message

2017-09-05 19:06+0200, Borislav Petkov: > From: Borislav Petkov > > There's no need to issue that everytime during boot - we have the > /proc/cpuinfo flag for people and software to query. > > Signed-off-by: Borislav Petkov > Cc: Janakarajan Natarajan > Cc: Paolo Bon

[PATCH] KVM: x86: fix clang build

correctly. Turn it into BUG_ON if there are any more problems with this. Fixes: d6321d493319 ("KVM: x86: generalize guest_cpuid_has_ helpers") Reported-by: Dmitry Vyukov <dvyu...@google.com> Signed-off-by: Radim Krčmář <rkrc...@redhat.com> --- arch/x86/kvm/cpuid.h | 1 - 1 fi

[PATCH] KVM: x86: fix clang build

correctly. Turn it into BUG_ON if there are any more problems with this. Fixes: d6321d493319 ("KVM: x86: generalize guest_cpuid_has_ helpers") Reported-by: Dmitry Vyukov Signed-off-by: Radim Krčmář --- arch/x86/kvm/cpuid.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/kvm

Re: "KVM: x86: generalize guest_cpuid_has_ helpers" breaks clang

2017-09-12 17:54+0200, Dmitry Vyukov: > On Tue, Sep 12, 2017 at 5:51 PM, Dmitry Vyukov <dvyu...@google.com> wrote: >> On Tue, Sep 12, 2017 at 5:18 PM, Radim Krčmář <rkrc...@redhat.com> wrote: >>> 2017-09-12 16:42+0200, Dmitry Vyukov: >>>> Hi Radim, >>

Re: "KVM: x86: generalize guest_cpuid_has_ helpers" breaks clang

2017-09-12 17:54+0200, Dmitry Vyukov: > On Tue, Sep 12, 2017 at 5:51 PM, Dmitry Vyukov wrote: >> On Tue, Sep 12, 2017 at 5:18 PM, Radim Krčmář wrote: >>> 2017-09-12 16:42+0200, Dmitry Vyukov: >>>> Hi Radim, >>>> >>>> I've just noticed that y

Re: "KVM: x86: generalize guest_cpuid_has_ helpers" breaks clang

2017-09-12 16:42+0200, Dmitry Vyukov: > Hi Radim, > > I've just noticed that your commit "KVM: x86: generalize > guest_cpuid_has_ helpers" breaks clang build on this assert: > > static __always_inline struct cpuid_reg x86_feature_cpuid(unsigned > x86_feature) > { > unsigned x86_leaf =

Re: "KVM: x86: generalize guest_cpuid_has_ helpers" breaks clang

2017-09-12 16:42+0200, Dmitry Vyukov: > Hi Radim, > > I've just noticed that your commit "KVM: x86: generalize > guest_cpuid_has_ helpers" breaks clang build on this assert: > > static __always_inline struct cpuid_reg x86_feature_cpuid(unsigned > x86_feature) > { > unsigned x86_leaf =

Re: [PATCH 3/3] KVM: SVM: Add irqchip_split() checks before enabling AVIC

2017-09-12 01:59-0700, Suravee Suthikulpanit: > On 9/8/17 08:53, Radim Krčmář wrote: >> 2017-09-05 22:39-0500, Suravee Suthikulpanit: >> > SVM AVIC hardware accelerates guest write to APIC_EOI register >> > (for edge-trigger interrupt), which means it does not trap

Re: [PATCH 3/3] KVM: SVM: Add irqchip_split() checks before enabling AVIC

2017-09-12 01:59-0700, Suravee Suthikulpanit: > On 9/8/17 08:53, Radim Krčmář wrote: >> 2017-09-05 22:39-0500, Suravee Suthikulpanit: >> > SVM AVIC hardware accelerates guest write to APIC_EOI register >> > (for edge-trigger interrupt), which means it does not trap

Re: [PATCH 3/3] KVM: SVM: Add irqchip_split() checks before enabling AVIC

2017-09-05 22:39-0500, Suravee Suthikulpanit: > SVM AVIC hardware accelerates guest write to APIC_EOI register > (for edge-trigger interrupt), which means it does not trap to KVM. > > So, only enable SVM AVIC only in split irqchip mode. > (e.g. launching qemu w/ option '-machine

Re: [PATCH 3/3] KVM: SVM: Add irqchip_split() checks before enabling AVIC

2017-09-05 22:39-0500, Suravee Suthikulpanit: > SVM AVIC hardware accelerates guest write to APIC_EOI register > (for edge-trigger interrupt), which means it does not trap to KVM. > > So, only enable SVM AVIC only in split irqchip mode. > (e.g. launching qemu w/ option '-machine

[GIT PULL] First batch of KVM changes for v4.14

o spapr_tce_tables list KVM: PPC: Book3S HV: Fix case where HDEC is treated as 32-bit on POWER9 KVM: PPC: Book3S HV: Report storage key support to userspace Merge remote-tracking branch 'remotes/powerpc/topic/ppc-kvm' into kvm-ppc-next Radim Krčmář (7): KVM: x86: X86_FEATURE

[GIT PULL] First batch of KVM changes for v4.14

o spapr_tce_tables list KVM: PPC: Book3S HV: Fix case where HDEC is treated as 32-bit on POWER9 KVM: PPC: Book3S HV: Report storage key support to userspace Merge remote-tracking branch 'remotes/powerpc/topic/ppc-kvm' into kvm-ppc-next Radim Krčmář (7): KVM: x86: X86_FEATURE

[PATCH RFC v3 3/9] KVM: remember position in kvm->vcpus array

Signed-off-by: Radim Krčmář <rkrc...@redhat.com> --- include/linux/kvm_host.h | 11 +++ virt/kvm/kvm_main.c | 5 - 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 6882538eda32..a8ff956616d2

[PATCH RFC v3 3/9] KVM: remember position in kvm->vcpus array

Signed-off-by: Radim Krčmář --- include/linux/kvm_host.h | 11 +++ virt/kvm/kvm_main.c | 5 - 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 6882538eda32..a8ff956616d2 100644 --- a/include/linux

[PATCH RFC v3 9/9] KVM: split kvm->vcpus into chunks

This allows us to have high KVM_VCPU_MAX without wasting too much space with small guests. RCU is a viable alternative now that we do not have to protect the kvm_for_each_vcpu() loop. Suggested-by: David Hildenbrand <da...@redhat.com> Signed-off-by: Radim Krčmář <rkrc...@redhat.com&g

[PATCH RFC v3 9/9] KVM: split kvm->vcpus into chunks

This allows us to have high KVM_VCPU_MAX without wasting too much space with small guests. RCU is a viable alternative now that we do not have to protect the kvm_for_each_vcpu() loop. Suggested-by: David Hildenbrand Signed-off-by: Radim Krčmář --- arch/mips/kvm/mips.c | 2 +- arch/x86

[PATCH RFC v3 8/9] KVM: implement kvm_for_each_vcpu with a list

bit to cope with the loss when working with a range 0-n and most other places switched to vcpu->vcpus_idx. Signed-off-by: Radim Krčmář <rkrc...@redhat.com> --- arch/mips/kvm/mips.c| 4 +--- arch/powerpc/kvm/book3s_32_mmu.c| 3 +-- arch/powerpc/kvm/book3s_64_m

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