Re: [PATCH] phy: nxp-c45: add driver for tja1103

2021-04-13 Thread Radu Nicolae Pirea (NXP OSS)
On Mon, 2021-04-12 at 10:50 +0100, Russell King - ARM Linux admin wrote: > On Fri, Apr 09, 2021 at 09:41:06PM +0300, Radu Pirea (NXP OSS) wrote: > > +#define B100T1_PMAPMD_CTL  0x0834 > > +#define B100T1_PMAPMD_CONFIG_ENBIT(15) > > +#define B100T1_PMAPMD_MASTER  

Re: [PATCH] phy: nxp-c45: add driver for tja1103

2021-04-12 Thread Radu Nicolae Pirea (NXP OSS)
On Mon, 2021-04-12 at 16:23 +0200, Andrew Lunn wrote: > > It is purely a C45 device. > > > Even if the PHY will be based on the same IP or not, if it is a C45 > > PHY, it will be supported by this driver. We are not talking about > > 2 or > > 3 PHYs. This driver will support all future C45 PHYs.

Re: [PATCH] phy: nxp-c45: add driver for tja1103

2021-04-12 Thread Radu Nicolae Pirea (NXP OSS)
On Mon, 2021-04-12 at 14:57 +0200, Andrew Lunn wrote: > On Mon, Apr 12, 2021 at 01:02:07PM +0300, Radu Nicolae Pirea (NXP > OSS) wrote: > > On Fri, 2021-04-09 at 21:36 +0200, Andrew Lunn wrote: > > > On Fri, Apr 09, 2021 at 09:41:06PM +0300, Radu Pirea (NXP OSS) > >

Re: [PATCH] phy: nxp-c45: add driver for tja1103

2021-04-12 Thread Radu Nicolae Pirea (NXP OSS)
On Fri, 2021-04-09 at 21:36 +0200, Andrew Lunn wrote: > On Fri, Apr 09, 2021 at 09:41:06PM +0300, Radu Pirea (NXP OSS) wrote: > > Add driver for tja1103 driver and for future NXP C45 PHYs. > > So apart from c45 vs c22, how does this differ to nxp-tja11xx.c? > Do we really want two different

Re: [PATCH] phy: nxp-c45: add driver for tja1103

2021-04-12 Thread Radu Nicolae Pirea (NXP OSS)
On Fri, 2021-04-09 at 21:18 +0200, Heiner Kallweit wrote: > On 09.04.2021 20:41, Radu Pirea (NXP OSS) wrote: > > Add driver for tja1103 driver and for future NXP C45 PHYs. > > > > Signed-off-by: Radu Pirea (NXP OSS) > > > > --- > >  MAINTAINERS   |   6 + > >  drivers/net/phy/Kconfig  

Re: [Patch v9] driver/clk/clk-si5338: Add common clock framework driver for si5338

2019-05-31 Thread Radu Nicolae Pirea
Hi, @York I want to continue the work on this driver and I want to upstream it. Are you OK with this? I saw later improvement suggestions related to the bindings and I will make the changes. @all please look at my below comment about si5338_pll_round_rate function. On Fri, 2016-08-26 at 14:45

Re: [PATCH 3/3] spi: at91-usart: add DMA support

2018-11-23 Thread Radu Nicolae Pirea
On Wed, 2018-11-21 at 17:38 +, Robin Murphy wrote: > On 21/11/2018 11:27, Radu Pirea wrote: > > This patch adds support for DMA. Transfers are done with dma only > > if > > they are longer than 16 bytes in order to achieve a better > > performance. > > DMA setup introduces a little overhead

Re: [PATCH 3/3] spi: at91-usart: add DMA support

2018-11-23 Thread Radu Nicolae Pirea
On Wed, 2018-11-21 at 17:38 +, Robin Murphy wrote: > On 21/11/2018 11:27, Radu Pirea wrote: > > This patch adds support for DMA. Transfers are done with dma only > > if > > they are longer than 16 bytes in order to achieve a better > > performance. > > DMA setup introduces a little overhead

Re: [PATCH 2/3] dt-bindings: mfd: atmel-usart: add DMA bindings for SPI mode

2018-11-23 Thread Radu Nicolae Pirea
On Wed, 2018-11-21 at 10:41 -0600, Rob Herring wrote: > On Wed, Nov 21, 2018 at 5:29 AM Radu Pirea > wrote: > > The bindings for DMA are now common for both drivers of the USART > > IP. > > > > The node given as an example for USART in SPI mode has been updated > > in > > order to include DMA

Re: [PATCH 2/3] dt-bindings: mfd: atmel-usart: add DMA bindings for SPI mode

2018-11-23 Thread Radu Nicolae Pirea
On Wed, 2018-11-21 at 10:41 -0600, Rob Herring wrote: > On Wed, Nov 21, 2018 at 5:29 AM Radu Pirea > wrote: > > The bindings for DMA are now common for both drivers of the USART > > IP. > > > > The node given as an example for USART in SPI mode has been updated > > in > > order to include DMA

Re: [GIT PULL] Immutable branch between MFD, SPI and TTY due for the v4.20 merge window

2018-09-11 Thread Radu Nicolae Pirea
Hi Lee, Thank you for taking the patch series, but you didn't take the latest version(v12) :) On Mon, 2018-09-10 at 16:18 +0100, Lee Jones wrote: > Enjoy! > > The following changes since commit > 5b394b2ddf0347bef56e50c69a58773c94343ff3: > > Linux 4.19-rc1 (2018-08-26 14:11:59 -0700) > >

Re: [GIT PULL] Immutable branch between MFD, SPI and TTY due for the v4.20 merge window

2018-09-11 Thread Radu Nicolae Pirea
Hi Lee, Thank you for taking the patch series, but you didn't take the latest version(v12) :) On Mon, 2018-09-10 at 16:18 +0100, Lee Jones wrote: > Enjoy! > > The following changes since commit > 5b394b2ddf0347bef56e50c69a58773c94343ff3: > > Linux 4.19-rc1 (2018-08-26 14:11:59 -0700) > >

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-12-08 Thread Radu Nicolae Pirea
On 16.11.2017 12:45, Mark Brown wrote: On Wed, Nov 15, 2017 at 06:35:32PM +0200, Radu Pirea wrote: +#ifdef CONFIG_SOC_SAM_V4_V5 + /* +* On Atmel SoCs based on ARM9 cores, the data cache follows the VIVT +* model, hence the cache aliases issue can occur when buffers are +

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-12-08 Thread Radu Nicolae Pirea
On 16.11.2017 12:45, Mark Brown wrote: On Wed, Nov 15, 2017 at 06:35:32PM +0200, Radu Pirea wrote: +#ifdef CONFIG_SOC_SAM_V4_V5 + /* +* On Atmel SoCs based on ARM9 cores, the data cache follows the VIVT +* model, hence the cache aliases issue can occur when buffers are +

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-11-16 Thread Radu Nicolae Pirea
On 15.11.2017 21:01, Trent Piepho wrote: On Wed, 2017-11-15 at 18:35 +0200, Radu Pirea wrote: If the cache model is VIVT, DMA data transfers may not be valid and to ensure the validity of the data cache must be flushed and invalidated. Signed-off-by: Radu Pirea

Re: [RFC PATCH 2/2] spi: atmel: Fix DMA transfers data corruption

2017-11-16 Thread Radu Nicolae Pirea
On 15.11.2017 21:01, Trent Piepho wrote: On Wed, 2017-11-15 at 18:35 +0200, Radu Pirea wrote: If the cache model is VIVT, DMA data transfers may not be valid and to ensure the validity of the data cache must be flushed and invalidated. Signed-off-by: Radu Pirea +#ifdef CONFIG_SOC_SAM_V4_V5