The USB PHY provides the optimized for low power dissipation while active,
idle, or on standby.
Requires minimal external components, a single resistor, for best operation.
Supports 10/5-Gbps high-speed data transmission rates through 3-m USB 3.x cable
---
v2:
- Address Phillip's review
Hi Philipp,
Thanks for the review comments...
On 9/6/2020 8:14 pm, Philipp Zabel wrote:
+
+ for (i = 0; i < ARRAY_SIZE(CTL_RESETS); i++)
+ reset_control_deassert(resets[i]);
+ /* Need to wait at least 20us before de-assert the PHY */
+ usleep_range(20, 100);
Hi Philipp,
Thank you very much for review comments and your time...
On 9/6/2020 8:14 pm, Philipp Zabel wrote:
+
+ for (i = 0; i < ARRAY_SIZE(CTL_RESETS); i++) {
+ resets[i] = devm_reset_control_get(dev, CTL_RESETS[i]);
Please use devm_reset_control_get_exclusive()
From: Ramuthevar Vadivel Murugan
Add the dt-schema to support USB PHY on Intel LGM SoC
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/usb/intel,lgm-usb-phy.yaml | 53 ++
1 file changed, 53 insertions(+)
create mode 100644
From: Ramuthevar Vadivel Murugan
Add support for USB PHY on Intel LGM SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
drivers/usb/phy/Kconfig | 11 ++
drivers/usb/phy/Makefile | 1 +
drivers/usb/phy/phy-lgm-usb.c | 269 ++
3 files
The USB PHY provides the optimized for low power dissipation while active,
idle, or on standby.
Requires minimal external components, a single resistor, for best operation.
Supports 10/5-Gbps high-speed data transmission rates through 3-m USB 3.x cable
Ramuthevar Vadivel Murugan (2):
Hi,
On 8/6/2020 10:23 am, kernel test robot wrote:
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: af7b4801030c07637840191c69eb666917e4135d
commit: 9227942383307f97fa6992416f73af4a23ef972c phy: intel-lgm-emmc: Add
support for eMMC PHY
date: 5 months
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 99 ++
1 file changed, 99 insertions(+)
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
Hi Rob,
On 30/5/2020 3:31 am, Rob Herring wrote:
On Thu, May 28, 2020 at 11:39:28PM +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 93 ++
1 file changed, 93 insertions(+)
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 93 ++
1 file changed, 93 insertions(+)
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
Hi Rob,
On 28/5/2020 10:06 pm, Rob Herring wrote:
On Thu, 28 May 2020 13:12:10 +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 93 ++
1 file changed, 93 insertions(+)
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
Hi Rob,
Thank you very much for the review comments...
On 27/5/2020 4:43 am, Rob Herring wrote:
On Wed, May 20, 2020 at 08:06:20AM +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning
Hi Mark,
On 21/5/2020 8:37 pm, Mark Brown wrote:
On Thu, May 21, 2020 at 08:34:43PM +0800, Ramuthevar, Vadivel MuruganX wrote:
On 21/5/2020 8:20 pm, Mark Brown wrote:
I mean that any changes to the bindings ought to be split out into
separate patches, if there's multiple changes it may make
Hi Mark,
On 21/5/2020 8:20 pm, Mark Brown wrote:
On Thu, May 21, 2020 at 08:14:04PM +0800, Ramuthevar, Vadivel MuruganX wrote:
On 21/5/2020 6:56 pm, Mark Brown wrote:
That doesn't address either of the issues. The removal of the old
bindings and addition of the YAML ones needs
Hi Mark,
On 21/5/2020 6:56 pm, Mark Brown wrote:
On Thu, May 21, 2020 at 10:18:26AM +0800, Ramuthevar, Vadivel MuruganX wrote:
On 20/5/2020 8:43 pm, Mark Brown wrote:
On Wed, May 20, 2020 at 08:36:12PM +0800, Ramuthevar,Vadivel MuruganX wrote:
.../devicetree/bindings/mtd/cadence
Hi Mark,
Thank you for the review comments...
On 20/5/2020 8:43 pm, Mark Brown wrote:
On Wed, May 20, 2020 at 08:36:12PM +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add dt-bindings documentation for Cadence-QSPI controller to support
spi based flash memories
From: Ramuthevar Vadivel Murugan
Add dt-bindings documentation for Cadence-QSPI controller to support
spi based flash memories.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/cadence-quadspi.txt| 67 ---
.../devicetree/bindings/spi/cdns,qspi-nor.yaml
Hi Rob,
Thank you very much for the review comments...
On 20/5/2020 2:44 am, Rob Herring wrote:
On Tue, May 12, 2020 at 08:49:19AM +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add dt-bindings documentation for Cadence-QSPI controller to support
spi based
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 91 ++
1 file changed, 91 insertions(+)
Hi Rob,
On 19/5/2020 2:27 am, Rob Herring wrote:
On Thu, May 14, 2020 at 8:08 PM Ramuthevar, Vadivel MuruganX
wrote:
Hi Rob,
On 14/5/2020 8:57 pm, Rob Herring wrote:
On Wed, 13 May 2020 18:46:14 +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add YAML file
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 91 ++
1 file changed, 91 insertions(+)
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
Hi Arnd, Andy,
On 15/5/2020 10:30 pm, Arnd Bergmann wrote:
On Fri, May 15, 2020 at 4:25 PM Andy Shevchenko
wrote:
On Fri, May 15, 2020 at 4:48 PM kbuild test robot wrote:
sparse warnings: (new ones prefixed by >>)
drivers/mtd/nand/raw/intel-nand-controller.c:441:24: sparse: sparse:
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 91 ++
1 file changed, 91 insertions(+)
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
Hi Rob,
On 15/5/2020 10:08 am, Ramuthevar, Vadivel MuruganX wrote:
Hi Rob,
On 14/5/2020 8:57 pm, Rob Herring wrote:
On Wed, 13 May 2020 18:46:14 +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
Hi Rob,
On 14/5/2020 8:57 pm, Rob Herring wrote:
On Wed, 13 May 2020 18:46:14 +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel
Hi Rob,
Thank you for the review comments...
On 14/5/2020 9:03 pm, Rob Herring wrote:
On Wed, May 13, 2020 at 06:46:14PM +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain
Hi Andy,
On 13/5/2020 11:35 pm, Andy Shevchenko wrote:
On Wed, May 13, 2020 at 06:34:05PM +0300, Andy Shevchenko wrote:
On Wed, May 13, 2020 at 06:46:15PM +0800, Ramuthevar,Vadivel MuruganX wrote:
...
+static int ebu_nand_remove(struct platform_device *pdev)
+{
+ struct
Hi Andy,
On 13/5/2020 11:34 pm, Andy Shevchenko wrote:
On Wed, May 13, 2020 at 06:46:15PM +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 83 ++
1 file changed, 83 insertions(+)
Hi Rob,
Thank you for the review comments and your time...
On 11/5/2020 11:37 pm, Rob Herring wrote:
On Thu, May 07, 2020 at 08:15:36AM +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's
From: Ramuthevar Vadivel Murugan
Add dt-bindings documentation for Cadence-QSPI controller to support
spi based flash memories.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/cadence-quadspi.txt| 67 ---
.../devicetree/bindings/spi/cdns,qspi-nor.yaml
Hi Vignesh,
On 9/5/2020 2:54 am, Vignesh Raghavendra wrote:
Vadivel,
I have maintained the additional changes needed on top of this series
for Intel platform that were part of your v12 series here (needs cleanup):
https://github.com/r-vignesh/linux.git branch: cqspi-mig
Please use above
Hi Boris,
Thank you very much for the review comments and your time...
On 7/5/2020 2:48 pm, Boris Brezillon wrote:
> On Thu, 7 May 2020 14:38:52 +0800
> "Ramuthevar, Vadivel MuruganX"
> wrote:
>
>> Hi Boris,
>>
>>Thank you very much for the revie
Hi Boris,
Thank you very much for the review comments and your time...
On 7/5/2020 2:27 pm, Boris Brezillon wrote:
On Thu, 7 May 2020 14:13:42 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Thank you very much for the review comments and your time...
On 7/5/20
Hi Boris,
Thank you very much for the review comments and your time...
On 7/5/2020 1:28 pm, Boris Brezillon wrote:
On Thu, 7 May 2020 08:15:37 +0800
"Ramuthevar,Vadivel MuruganX"
wrote:
+ reg = readl(ebu_host->ebu + EBU_ADDR_SEL(ebu_host->cs_num));
+
Hi,
On 7/5/2020 8:22 am, Randy Dunlap wrote:
On 5/6/20 5:15 PM, Ramuthevar,Vadivel MuruganX wrote:
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index a80a46bb5b8b..a026bec28f39 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -457,6
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 85 ++
1 file changed, 85 insertions(+)
Hi Boris,
On 5/5/2020 3:00 pm, Boris Brezillon wrote:
Hello Vadivel,
On Tue, 5 May 2020 13:28:58 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
ebu_nand: ebu_nand@e0f0 {
compatible = "intel,lgm-ebu-nand";
reg
Hi Boris,
On 4/5/2020 4:58 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 16:50:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 4/5/2020 3:17 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 15:15:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Hi Boris,
On 4/5/2020 4:58 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 16:50:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 4/5/2020 3:17 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 15:15:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Hi Boris,
On 4/5/2020 3:17 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 15:15:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Thank you very much for the prompt review and suggestions...
On 4/5/2020 3:08 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 10:0
Hi Boris,
Thank you very much for the prompt review and suggestions...
On 4/5/2020 3:08 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 10:02:35 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 30/4/2020 9:01 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 14:36:00 +
Hi Boris,
On 30/4/2020 9:01 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 14:36:00 +0200
Boris Brezillon wrote:
On Thu, 30 Apr 2020 17:07:03 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
The question is, is it the same value we have in nand_pa or it is
different?
Hi Boris,
Thank you very much for the review comments and your time...
On 30/4/2020 9:01 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 14:36:00 +0200
Boris Brezillon wrote:
On Thu, 30 Apr 2020 17:07:03 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
The question is, is it the
Hi Boris,
Thank you very much for the review comments and giving inputs...
On 30/4/2020 8:36 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 17:07:03 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
The question is, is it the same value we have in nand_pa or it is
different?
Hi Boris,
On 30/4/2020 4:36 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 16:30:15 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
And now I'd like you to explain why 5 is the right value for that field
(I guess that has to do with the position of the CS/ALE/CLE pins).
5 : bit 26,
H Boris,
On 30/4/2020 4:21 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 15:50:30 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Thank you very much for keep reviewing the patches and more queries...
On 29/4/2020 11:31 pm, Boris Brezillon wrote:
On Wed, 29 Apr 202
Hi Boris,
Thank you very much for keep reviewing the patches and more queries...
On 29/4/2020 11:31 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 23:18:31 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 29/4/2020 10:48 pm, Boris Brezillon wrote:
On Wed, 29 Apr 202
Hi Boris,
Thank you very much for the review comments and your time...
On 29/4/2020 11:34 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 18:42:04 +0800
"Ramuthevar,Vadivel MuruganX"
wrote:
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash
Hi Boris,
On 29/4/2020 11:18 pm, Ramuthevar, Vadivel MuruganX wrote:
+ writel(lower_32_bits(ebu_host->cs[ebu_host->cs_num].nand_pa) |
+ EBU_ADDR_SEL_REGEN | EBU_ADDR_MASK,
+ ebu_host->ebu + EBU_ADDR_SEL(reg));
+
+ writel(EBU_MEM_BASE_CS_0 | EBU_
Hi Boris,
On 29/4/2020 10:48 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 22:33:37 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 29/4/2020 10:22 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
+
+#d
Hi Boris,
On 29/4/2020 10:22 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
+
+#define EBU_ADDR_SEL(n)(0x20 + (n) * 4)
+#define EBU_ADDR_MASK (5 << 4)
It's still unclear what ADDR_MASK is
Hi Boris,
Thank you very much for the review comments and your time...
On 29/4/2020 9:32 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 21:29:40 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Thank you very much for the review comments and your time..
On 29/4/20
Hi Boris,
Thank you very much for the review comments and your time..
On 29/4/2020 7:33 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar,Vadivel MuruganX"
wrote:
+#define NAND_WRITE_CMD (EBU_CON_CS_P_LOW | HSNAND_CLE_OFFS)
+#define NAND_
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
From: Ramuthevar Vadivel Murugan
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml| 61 ++
1 file changed, 61 insertions(+)
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
Hi Miquel,
On 28/4/2020 3:54 pm, Miquel Raynal wrote:
Do we have access to the spec or a register map? We could tell you very
quickly if it is worth the trouble. But I am pretty sure as well that
the controller supports more than 1 CS.
Got it, will update the changes to support multiple CS as
Hi Miquel,
On 28/4/2020 3:54 pm, Miquel Raynal wrote:
Hello,
"Ramuthevar, Vadivel MuruganX"
wrote on Tue, 28 Apr 2020
15:50:06 +0800:
Hi Miquel,
On 28/4/2020 3:40 pm, Miquel Raynal wrote:
Hi Vadivel MuruganX,
"Ramuthevar, Vadivel MuruganX"
wrote on Tue, 28 Apr
Hi Miquel,
On 28/4/2020 3:40 pm, Miquel Raynal wrote:
Hi Vadivel MuruganX,
"Ramuthevar, Vadivel MuruganX"
wrote on Tue, 28 Apr 2020
14:50:35 +0800:
Hi Boris,
On 28/4/2020 2:47 pm, Boris Brezillon wrote:
On Tue, 28 Apr 2020 14:40:58 +0800
"Ramuthevar, Vadivel MuruganX&q
Hi Boris,
On 28/4/2020 2:47 pm, Boris Brezillon wrote:
On Tue, 28 Apr 2020 14:40:58 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 28/4/2020 2:27 pm, Boris Brezillon wrote:
On Tue, 28 Apr 2020 14:17:30 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Miqu
From: Ramuthevar Vadivel Murugan
Add support for eMMC PHY on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
Reviewed-by: Andy Shevchenko
---
drivers/phy/Kconfig| 1 +
drivers/phy/Makefile | 1 +
drivers/phy/intel/Kconfig
From: Ramuthevar Vadivel Murugan
Add a YAML schema to use the host controller driver with the
eMMC PHY on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
---
.../bindings/phy/intel,lgm-emmc-phy.yaml | 63 ++
1 file changed, 63
Rebased to kernel verson 5.4
dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY
changes in v6:
- cobined comaptible strings
- added as contiguous and can be a single entry for reg properties
changes in v5:
- earlier Review-by tag given by Rob
- rework done with
From: Ramuthevar Vadivel Murugan
On Intel Lightning Mountain SoCs QSPI controller do not use auto-poll.
This patch disables auto polling when direct access mode is disabled
Signed-off-by: Ramuthevar Vadivel Murugan
---
drivers/mtd/spi-nor/cadence-quadspi.c | 22 ++
1 file
From: Ramuthevar Vadivel Murugan
On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).
This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfer.
Signed-off-by: Ramuthevar Vadivel Murugan
On Intel Lightning Mountain SoCs QSPI controller do not use auto-poll
and Direct Access Controller (DAC).
Thanks vignesh for your time to review the patch.
The following comments are addressed..
changes from v3:
- commit messages are updated in both the patches
- moved cqspi_disable_auto_poll()
Hi Vignesh,
Thank you for the review comments.
On 16/10/2019 4:40 PM, Vignesh Raghavendra wrote:
On 09/09/19 4:17 PM, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
On Intel's Lightning Mountain(LGM) SoC QSPI controller do not auto-poll.
This patch introduces
Hi Vignesh,
Thank you for the review comments.
On 16/10/2019 4:32 PM, Vignesh Raghavendra wrote:
On 09/09/19 4:17 PM, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
on Intel's Lightning Mountain(LGM) SoCs QSPI controller do not use
s/on/On
Agreed, will update
Hi Vignesh,
On 10/10/2019 12:18 PM, Vignesh Raghavendra wrote:
On 10/10/19 7:04 AM, Ramuthevar, Vadivel MuruganX wrote:
HI Vignesh,
On 17/9/2019 12:50 AM, Vignesh Raghavendra wrote:
Hi,
On 16/09/19 1:08 PM, Ramuthevar,Vadivel MuruganX wrote:
patch 1: Add YAML for cadence-qspi devicetree
HI Vignesh,
On 17/9/2019 12:50 AM, Vignesh Raghavendra wrote:
Hi,
On 16/09/19 1:08 PM, Ramuthevar,Vadivel MuruganX wrote:
patch 1: Add YAML for cadence-qspi devicetree cdocumentation.
patch 2: cadence-qspi controller driver to support QSPI-NAND flash
using existing spi-nand framework
Hi Andy,
On 9/10/2019 5:40 PM, Andy Shevchenko wrote:
On Wed, Oct 09, 2019 at 09:06:16AM +0800, Ramuthevar, Vadivel MuruganX wrote:
Hi Adrian,
Thank you for the Acked-by, will add *Acked-by* in the next-patch.
Please, stop top-posting.
Besides that, there is no need for next version
From: Ramuthevar Vadivel Murugan
The current arasan sdhci PHY configuration isn't compatible
with the PHY on Intel's LGM(Lightning Mountain) SoC devices.
Therefore, add a new compatible, to adapt the Intel's LGM
SDXC PHY with arasan-sdhc controller to configure the PHY.
Signed-off-by:
From: Ramuthevar Vadivel Murugan
Add a new compatible to use the sdhc-arasan host controller driver
with the SDXC PHY to support on Intel's Lightning Mountain(LGM) SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 17 +
The current arasan sdhci PHY configuration isn't compatible
with the PHY on Intel's LGM(Lightning Mountain) SoC devices.
Therefore, add a new compatible, to adapt the Intel's LGM
SDXC PHY with arasan-sdhc controller to configure the PHY.
Linux code base : V5.4-rc1
Ramuthevar Vadivel Murugan
Hi Rob,
On 18/9/2019 10:23 AM, Ramuthevar, Vadivel MuruganX wrote:
Hi Rob,
Thank you for the review comments.
On 17/9/2019 10:23 PM, Rob Herring wrote:
On Wed, Sep 04, 2019 at 01:53:43PM +0800, Ramuthevar,Vadivel MuruganX
wrote:
From: Ramuthevar Vadivel Murugan
Add a YAML schema to use
Hi Adrian,
On 3/10/2019 3:46 PM, Ramuthevar, Vadivel MuruganX wrote:
Hi Adrian,
Thank you for the comments.
On 3/10/2019 3:02 PM, Adrian Hunter wrote:
On 3/10/19 7:00 AM, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
The current arasan sdhci PHY configuration isn't
Hi Adrian,
Thank you for the comments.
On 3/10/2019 3:02 PM, Adrian Hunter wrote:
On 3/10/19 7:00 AM, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
The current arasan sdhci PHY configuration isn't compatible
with the PHY on Intel's LGM(Lightning Mountain) SoC devices
The current arasan sdhci PHY configuration isn't compatible
with the PHY on Intel's LGM(Lightning Mountain) SoC devices.
Therefore, add a new compatible, to adapt the Intel's LGM
SDXC PHY with arasan-sdhc controller to configure the PHY.
Linux code base : V5.4-rc1
Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan
Add a new compatible to use the sdhc-arasan host controller driver
with the eMMC PHY on Intel's Lightning Mountain(LGM) SoC.
Signed-off-by: Ramuthevar Vadivel Murugan
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 17 +
1 file
201 - 300 of 368 matches
Mail list logo
