pecific device power state, so in both cases it should be safe to call
_PTS before suspending, no?
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blow up the machine? Yuck.
Still don't like this approach. It seems like (partially) covering up
problems rather than solving them.
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.
Still don't like this approach. It seems like (partially) covering up
problems rather than solving them.
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, so in both cases it should be safe to call
_PTS before suspending, no?
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resume or
something? Anyway, I asked it to please stop doing that, and it
complied without even exploding (unlike crabby APICs).
Are we missing some logic to resync the TSCs after resume, or something?
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problems I'm aware
of are devices behind host bridges which can't receive/handle MMCONFIG
requests, in which case the problem would be bus-wide.
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problem, but if it couldn't be fixed, I think the only sane solution
would be to blacklist MMCONFIG support on that chipset.
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machine and not the real one..
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was removed since it was broken, so this
error shouldn't happen anymore.
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-893d-a6f2295b40c8/TW04015_WINHEC2004.ppt
I suspect that might require more Windows hacking skill and/or
motivation than one might be likely to find on this list, though :-)
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quote in reply to Robert Hancock), but as you point out, 9.3.2 says
the opposite.
So, 1.0 and 3.0 are very clear and rather different on this, and 2.0 is
contradictory (and I presume this is one of the points ACPI 3.0 set out to
clean up).
I will rescind my point on ACPI 2.0 - I don't know what
quote in reply to Robert Hancock), but as you point out, 9.3.2 says
the opposite.
So, 1.0 and 3.0 are very clear and rather different on this, and 2.0 is
contradictory (and I presume this is one of the points ACPI 3.0 set out to
clean up).
I will rescind my point on ACPI 2.0 - I don't know what
-893d-a6f2295b40c8/TW04015_WINHEC2004.ppt
I suspect that might require more Windows hacking skill and/or
motivation than one might be likely to find on this list, though :-)
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was removed since it was broken, so this
error shouldn't happen anymore.
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culprit in this case.
Yeah, and this is a PCI Express system not AGP, so it wouldn't load anyway.
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-space when sizing the bars of a device (I have some
traces of configuration-space-access taken on a window machine for one
of the PCI busses).
Good to know. There was some speculation that it did not.
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board specific. Looking at the DSDT for my A8N-SLI
Deluxe, that SMIP region is defined at 0x442E (and is reported as
reserved). This BIOS doesn't write there in the _PTS method like the
ones in the report apparently do though.
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at the DSDT for my A8N-SLI
Deluxe, that SMIP region is defined at 0x442E (and is reported as
reserved). This BIOS doesn't write there in the _PTS method like the
ones in the report apparently do though.
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-space when sizing the bars of a device (I have some
traces of configuration-space-access taken on a window machine for one
of the PCI busses).
Good to know. There was some speculation that it did not.
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.
Yeah, and this is a PCI Express system not AGP, so it wouldn't load anyway.
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=e18c985289ee356f06dbc953281a3c140a02fbb3
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More maj
verlap
problem, and likely Tony Camuso's patch or something like it, to disable
MMCONFIG accesses to devices behind certain broken host bridges). Once
that works, then this patch really serves no purpose.
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problem, and likely Tony Camuso's patch or something like it, to disable
MMCONFIG accesses to devices behind certain broken host bridges). Once
that works, then this patch really serves no purpose.
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=e18c985289ee356f06dbc953281a3c140a02fbb3
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Tony Camuso wrote:
Robert Hancock wrote:
First off, I would like to see confirmation from the horses's mouths
here (namely AMD, ServerWorks/Broadcom, and whoever else) that there
is no other way to get around this problem than disabling MMCONFIG for
accesses behind those chips.
I happen
hipsets so
that MSI would function, because the BIOS failed to set them up
properly. Are we sure there's not a similar BIOS configuration issue
that could ideally be fixed in the BIOS, or else fixed up in the kernel?
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function, because the BIOS failed to set them up
properly. Are we sure there's not a similar BIOS configuration issue
that could ideally be fixed in the BIOS, or else fixed up in the kernel?
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Tony Camuso wrote:
Robert Hancock wrote:
First off, I would like to see confirmation from the horses's mouths
here (namely AMD, ServerWorks/Broadcom, and whoever else) that there
is no other way to get around this problem than disabling MMCONFIG for
accesses behind those chips.
I happen
n from SMI. In that case it would be quite reasonable
for the BIOS to reserve that region to prevent another driver from
loading and trying to take conflicting control of the device. One has to
be careful before assuming that any such reservation is bogus.
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D K8 built-in northbridge). If this is not
sufficient, I would suggest expanding that mechanism instead of adding
all this new code.
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-in northbridge). If this is not
sufficient, I would suggest expanding that mechanism instead of adding
all this new code.
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. In that case it would be quite reasonable
for the BIOS to reserve that region to prevent another driver from
loading and trying to take conflicting control of the device. One has to
be careful before assuming that any such reservation is bogus.
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Karsten Wiese wrote:
Am Mittwoch, 19. Dezember 2007 schrieb Robert Hancock:
That seems fishy. What is your value of HZ and what is the timeout value
that was passed in the bad case?
HZ set to 250, timeout to 4ms.
Time spent in poll() taken by clock_gettime(CLOCK_MONOTONIC, )
before and after
ry can be pretty easily exhausted on machines
with lots of high memory.
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tions and relying
only on E820 would result in things really going blammo (like mappings
things over MMCONFIG tables for instance). So disabling it on modern
machines is really not an option. And if it's enabled, you likely
wouldn't hit the problem it tries to fix.
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ieces of information into one overall map like Linux
does, which would explain why it needs to reserve all physical RAM..
(As mentioned in another post, I would guess the BIOS is reserving that
memory range since it's the MMCONFIG aperture..)
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To e
there will have disastrous results. (This BIOS has an
MCFG table, though it looks like this Fedora kernel has MMCONFIG
disabled, so we can't tell what it actually contains.)
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or .Please anyone help
me
First off, why are you trying to do this and how. Without such details
it's impossible to answer this question.
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{
/* Infinite (< 0) or no (0) timeout */
timeout_jiffies = timeout_msecs;
That seems fishy. What is your value of HZ and what is the timeout value
that was passed in the bad case?
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anyone help
me
First off, why are you trying to do this and how. Without such details
it's impossible to answer this question.
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there will have disastrous results. (This BIOS has an
MCFG table, though it looks like this Fedora kernel has MMCONFIG
disabled, so we can't tell what it actually contains.)
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into one overall map like Linux
does, which would explain why it needs to reserve all physical RAM..
(As mentioned in another post, I would guess the BIOS is reserving that
memory range since it's the MMCONFIG aperture..)
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) or no (0) timeout */
timeout_jiffies = timeout_msecs;
That seems fishy. What is your value of HZ and what is the timeout value
that was passed in the bad case?
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in things really going blammo (like mappings
things over MMCONFIG tables for instance). So disabling it on modern
machines is really not an option. And if it's enabled, you likely
wouldn't hit the problem it tries to fix.
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exhausted on machines
with lots of high memory.
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Karsten Wiese wrote:
Am Mittwoch, 19. Dezember 2007 schrieb Robert Hancock:
That seems fishy. What is your value of HZ and what is the timeout value
that was passed in the bad case?
HZ set to 250, timeout to 4ms.
Time spent in poll() taken by clock_gettime(CLOCK_MONOTONIC, time)
before
were
they could only be flushed by a read, not a write) and PCI MMIO writes
are only guaranteed to flush by doing a read from that device, not by
other random port accesses. I suppose using the _p versions of port
accesses might happen to mask such problems on certain machines..
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, we might suspect
that there is compensating logic in either Windows ACPI code or some way
that windows "sets up" the machine.
You'd have to replace the iopl call to an equivalent one for Windows
(seems like NtSetInformationProcess(ProcessUserModeIOPL) might do what
you need).
suspect
that there is compensating logic in either Windows ACPI code or some way
that windows sets up the machine.
You'd have to replace the iopl call to an equivalent one for Windows
(seems like NtSetInformationProcess(ProcessUserModeIOPL) might do what
you need).
--
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be flushed by a read, not a write) and PCI MMIO writes
are only guaranteed to flush by doing a read from that device, not by
other random port accesses. I suppose using the _p versions of port
accesses might happen to mask such problems on certain machines..
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, and if it
runs the rest of the night at 400 without a self reboot or crash, I'll leave
it there.
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, and if it
runs the rest of the night at 400 without a self reboot or crash, I'll leave
it there.
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eproduce the failure, so it looks like a kernel issue to me.
With this part of strace output it seems like an obvious userspace bug
(calling fcntl on a -1 file descriptor). Could be some other change in
behavior or timing difference is triggering the bug,however.
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continues to occur repeatedly, you don't
have to worry about it.
Yes, if it didn't recur, was likely just a transient glitch.
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to occur repeatedly, you don't
have to worry about it.
Yes, if it didn't recur, was likely just a transient glitch.
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.
With this part of strace output it seems like an obvious userspace bug
(calling fcntl on a -1 file descriptor). Could be some other change in
behavior or timing difference is triggering the bug,however.
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decided that one
board always choked on an empty channel. Maybe it's not that and it's
just another case of the same issue where our resetting default timing
values on the controller before calling _GTM would choke the _GTM method?
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le to find a place to map all of the BARs.
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to map all of the BARs.
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decided that one
board always choked on an empty channel. Maybe it's not that and it's
just another case of the same issue where our resetting default timing
values on the controller before calling _GTM would choke the _GTM method?
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idge's decode window (with higher decode
priority than the MMCONFIG aperture, even)..
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d then executing inl/outl, etc. instructions directly.
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/outl, etc. instructions directly.
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More
priority than the MMCONFIG aperture, even)..
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think it is?
You are sure that this drive still works with older kernels using
drivers/ide, and that the hardware didn't break at some point, I assume?
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that this drive still works with older kernels using
drivers/ide, and that the hardware didn't break at some point, I assume?
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Tejun Heo wrote:
Robert Hancock wrote:
And you're quite right in your comment that we are often too quick to
blacklist hardware instead of looking into why it really is failing.
ACPI is one of those areas where we often just need to figure out how to
be bug-to-bug compatibile with what Windows
And you're quite right in your comment that we are often too quick to
blacklist hardware instead of looking into why it really is failing.
ACPI is one of those areas where we often just need to figure out how to
be bug-to-bug compatibile with what Windows is doing..
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34200 ctl 0x
bmdma 0x irq 316
ata4: SATA max UDMA/133 cmd 0xc2334280 ctl 0x
bmdma 0x00000000 irq 316
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0x irq 316
ata4: SATA max UDMA/133 cmd 0xc2334280 ctl 0x
bmdma 0x irq 316
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are often too quick to
blacklist hardware instead of looking into why it really is failing.
ACPI is one of those areas where we often just need to figure out how to
be bug-to-bug compatibile with what Windows is doing..
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Tejun Heo wrote:
Robert Hancock wrote:
And you're quite right in your comment that we are often too quick to
blacklist hardware instead of looking into why it really is failing.
ACPI is one of those areas where we often just need to figure out how to
be bug-to-bug compatibile with what Windows
Jeff Garzik wrote:
Robert Hancock wrote:
This fixes some problems with ATAPI devices on nForce4 controllers in
ADMA mode
on systems with memory located above 4GB. We need to delay setting the
64-bit
DMA mask until the PRD table and padding buffer are allocated so that
they don't
get
worked on the original Hitachi disk, but I've upgraded it to a
newer Samsung). I'd say if the drive returns command aborted on one of
these, we should just ignore that command and continue to the next one
without trying to retry or disabling the ACPI support entirely.
--
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on the original Hitachi disk, but I've upgraded it to a
newer Samsung). I'd say if the drive returns command aborted on one of
these, we should just ignore that command and continue to the next one
without trying to retry or disabling the ACPI support entirely.
--
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Jeff Garzik wrote:
Robert Hancock wrote:
This fixes some problems with ATAPI devices on nForce4 controllers in
ADMA mode
on systems with memory located above 4GB. We need to delay setting the
64-bit
DMA mask until the PRD table and padding buffer are allocated so that
they don't
get
shared IRQ.
*/
I assume that with old IDE this would use ide_cs.c, but I'm drawing a
blank on what modes that supports..
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ot; took about
15% of one cpu... I never bothered to check if that is the norm but i
suspect i'll be removing that feature as it seems to not play nice with
the kernel.
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those at the disk layer, like these
are saying it is, _after_ that error occurs:
Dec 7 04:08:13 chaos kernel: attempt to access beyond end of device
Dec 7 04:08:13 chaos kernel: sdb1: rw=0, want=29687515944, limit=33736437
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assume that with old IDE this would use ide_cs.c, but I'm drawing a
blank on what modes that supports..
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never bothered to check if that is the norm but i
suspect i'll be removing that feature as it seems to not play nice with
the kernel.
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these
are saying it is, _after_ that error occurs:
Dec 7 04:08:13 chaos kernel: attempt to access beyond end of device
Dec 7 04:08:13 chaos kernel: sdb1: rw=0, want=29687515944, limit=33736437
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o IO port
writes as fast as possible, then surely there's a better solution than
trying to stall the IOs by an arbitrary and hardware-dependent amount of
time, like udelay calls, etc. Does any remotely recent hardware even
need this?
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a better solution than
trying to stall the IOs by an arbitrary and hardware-dependent amount of
time, like udelay calls, etc. Does any remotely recent hardware even
need this?
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Guennadi Liakhovetski wrote:
On Tue, 4 Dec 2007, Robert Hancock wrote:
Guennadi Liakhovetski wrote:
I've got an old 2xP-II @ 400MHz Compaq AP400 system, which I'm still using.
It has many peculiarities, so, I wouldn't be surprised if the answer to my
questions would be "sorry, the pa
Guennadi Liakhovetski wrote:
On Tue, 4 Dec 2007, Robert Hancock wrote:
Guennadi Liakhovetski wrote:
I've got an old 2xP-II @ 400MHz Compaq AP400 system, which I'm still using.
It has many peculiarities, so, I wouldn't be surprised if the answer to my
questions would be sorry, the patient
fig.
How about disabling ACPI entirely, acpi=off on kernel command line? I
wouldn't be surprised to see a lot of ACPI stuff broken on an older
machine like that..
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think there theory is
that it's some other timing problem or some such, given the number of
drives across all makers which are reported to do this. I believe Tejun
is investigating?
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the context switch for.. I could be wrong though.
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Jeff Garzik wrote:
Robert Hancock wrote:
This fixes some problems with ATAPI devices on nForce4 controllers in
ADMA mode
on systems with memory located above 4GB. We need to delay setting the
64-bit
DMA mask until the PRD table and padding buffer are allocated so that
they don't
get
Jeff Garzik wrote:
Robert Hancock wrote:
This fixes some problems with ATAPI devices on nForce4 controllers in
ADMA mode
on systems with memory located above 4GB. We need to delay setting the
64-bit
DMA mask until the PRD table and padding buffer are allocated so that
they don't
get
the context switch for.. I could be wrong though.
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think there theory is
that it's some other timing problem or some such, given the number of
drives across all makers which are reported to do this. I believe Tejun
is investigating?
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try?
If needed can provide complete dmesg (with nohz=off or with
clocksource=tsc) and .config.
How about disabling ACPI entirely, acpi=off on kernel command line? I
wouldn't be surprised to see a lot of ACPI stuff broken on an older
machine like that..
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and thus be worthless in
a raid5 configuration.
Can anyone offer any insight here?
Thank you,
Justin.
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and thus be worthless in
a raid5 configuration.
Can anyone offer any insight here?
Thank you,
Justin.
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-triggered interrupt, an unhandled interrupt will keep interrupting
forever since nobody knows how to clear it (until we decide to disable
the IRQ entirely).
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-triggered interrupt, an unhandled interrupt will keep interrupting
forever since nobody knows how to clear it (until we decide to disable
the IRQ entirely).
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userspace, but then you have the same problem (and 10MB
is awfully big for vmalloc).
Is there a good reason why you have to be able to do this? There's
likely a better way.
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userspace, but then you have the same problem (and 10MB
is awfully big for vmalloc).
Is there a good reason why you have to be able to do this? There's
likely a better way.
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Robert Hancock Saskatoon, SK, Canada
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