mark all of RAM as cachable.
When the top memory starts being used with the bigmem kernel it causes a
major slowdown. Check for a BIOS update from Intel, first.
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Rajkumar S wrote:
On 10/24/07, Robert Hancock [EMAIL PROTECTED] wrote:
Rajkumar S wrote:
Hello,
I am using a Core 2 Duo E6750 CPU on an intel DG33FB mother board with
4GB Ram, running Debian Lenny.
Since the box has 4 GB ram I compiled a big mem kernel, but the
machine is very slow while
ikely you didn't enable whatever driver your system needs to
access the hard drive..
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whatever driver your system needs to
access the hard drive..
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r burn engine is differentiating
IDE and read-good-old-SCSI devices and handles them sometimes in a
different way, so this differenciation is really important for us.
-> How can I detect the real physical device type now?
I don't have a great answer off the top of my head..
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it's quite possible that
that part of the executable hasn't been loaded until something calls a
function within it.
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t doesn't support 64-bit.
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.
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More majordomo info at http://vger.kernel.org
it's quite possible that
that part of the executable hasn't been loaded until something calls a
function within it.
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is differentiating
IDE and read-good-old-SCSI devices and handles them sometimes in a
different way, so this differenciation is really important for us.
- How can I detect the real physical device type now?
I don't have a great answer off the top of my head..
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the real-time clock at all? Does the
tickless kernel effect this at all?
Thanks for any help you can lend,
Rick Niles.
Am I missing why you can't just use a normal kernel timer for this? You
shouldn't have to mess with the RTC or HPET directly..
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and
possibly find a workaround...
It doesn't make sense to use ioremap_nocache on RAM. It's only meant for
mapping MMIO memory regions on a device.
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Len Brown wrote:
On Tuesday 09 October 2007 20:01, Robert Hancock wrote:
Some people with certain Supermicro boards (at least the H8DCE, it
seems) have reported that the sata_nv driver fails to attach to some of
the controllers due to resource conflicts:
https://bugzilla.redhat.com
Len Brown wrote:
On Tuesday 09 October 2007 20:01, Robert Hancock wrote:
Some people with certain Supermicro boards (at least the H8DCE, it
seems) have reported that the sata_nv driver fails to attach to some of
the controllers due to resource conflicts:
https://bugzilla.redhat.com
and
possibly find a workaround...
It doesn't make sense to use ioremap_nocache on RAM. It's only meant for
mapping MMIO memory regions on a device.
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use the real-time clock at all? Does the
tickless kernel effect this at all?
Thanks for any help you can lend,
Rick Niles.
Am I missing why you can't just use a normal kernel timer for this? You
shouldn't have to mess with the RTC or HPET directly..
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now and lacking many bug fixes. It would be far better to
upgrade to 2.6 for SATA support.
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Jim Gifford wrote:
Robert Hancock wrote:
Jim Gifford wrote:
Here's the situation. I have a MSI KN8Neo-f motherboard with a
Seagate Barracuda 250 GB SATA drive. I have replaced this drive three
times in the last two weeks due to it failing. Now the only thing in
common is the use
Jim Gifford wrote:
Robert Hancock wrote:
Jim Gifford wrote:
Here's the situation. I have a MSI KN8Neo-f motherboard with a
Seagate Barracuda 250 GB SATA drive. I have replaced this drive three
times in the last two weeks due to it failing. Now the only thing in
common is the use
now and lacking many bug fixes. It would be far better to
upgrade to 2.6 for SATA support.
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computer.com/product/p_spec.asp?model=K8N_Neo4-F=mb
It has 2GB of Memory and a Nvidia PCI-E Graphics Adapter
I will work with any member of the lkml team to help isolate the issue,
the only issue is that when it locks up everything has to be written
down or photographed.
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e ACPI resource
reservations?
I wonder how Windows deals with this, if it even does on these boards?
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if they conflict with the ACPI resource
reservations?
I wonder how Windows deals with this, if it even does on these boards?
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/p_spec.asp?model=K8N_Neo4-Fclass=mb
It has 2GB of Memory and a Nvidia PCI-E Graphics Adapter
I will work with any member of the lkml team to help isolate the issue,
the only issue is that when it locks up everything has to be written
down or photographed.
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) or the target
(the chipset host bridge) decided to puke on for some reason. Possibly
parity errors?
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) or the target
(the chipset host bridge) decided to puke on for some reason. Possibly
parity errors?
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The
performance effects of setting this bit are limited to streaming stores
to the write-combining (WC) memory type, a case expected to rarely occur
in actual usage. No loss of performance occurs in the general case (WB
memory type).
This workaround must not be applied to processors prio
ernel gets marked as tainted when you load proprietary modules
because with no source code available there is no way to determine what
kind of badness the code may have done to break the kernel. Bug reports
from tainted kernels are generally given fairly little weight.
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marked as tainted when you load proprietary modules
because with no source code available there is no way to determine what
kind of badness the code may have done to break the kernel. Bug reports
from tainted kernels are generally given fairly little weight.
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Robert Hancock Saskatoon, SK
are limited to streaming stores
to the write-combining (WC) memory type, a case expected to rarely occur
in actual usage. No loss of performance occurs in the general case (WB
memory type).
This workaround must not be applied to processors prior to revision C0.
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Robert Hancock Saskatoon
Andrew Morton wrote:
libata-add-human-readable-error-value-decoding-v3.patch
I think I own this now. Will send to jgarzik then drop it if it doesn't
stick.
Another plug for this one, as the author. I really don't think one can
object to it, and it definitely seems useful.
--
Robert
Andrew Morton wrote:
libata-add-human-readable-error-value-decoding-v3.patch
I think I own this now. Will send to jgarzik then drop it if it doesn't
stick.
Another plug for this one, as the author. I really don't think one can
object to it, and it definitely seems useful.
--
Robert
D", "K2AOAJ0AHITACHI",
ATA_HORKAGE_NONCQ },
/* NCQ hard hangs device under heavier load, needs hard power cycle */
Are you sure this isn't just a bum drive? Looking at the SMART listing
that was posted, looks like it's had some uncorrectable sector read
erro
hard power cycle */
Are you sure this isn't just a bum drive? Looking at the SMART listing
that was posted, looks like it's had some uncorrectable sector read
errors in the event log..
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didn't set up the MTRRs to mark all
RAM as write-back. This results in the last bit of memory being
uncacheable and causes a major performance drop.
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didn't set up the MTRRs to mark all
RAM as write-back. This results in the last bit of memory being
uncacheable and causes a major performance drop.
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-time problems that we need this patch to fix, I would say
it should stay in.
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as this device is concerned? If
we are doing BAR sizing and moving the base address around, it's going
to cause problems if you try to access the device during this time
whether we disable decode or not.
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as this device is concerned? If
we are doing BAR sizing and moving the base address around, it's going
to cause problems if you try to access the device during this time
whether we disable decode or not.
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-time problems that we need this patch to fix, I would say
it should stay in.
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the body
does not support the Power Management feature set." Whereas TEST UNIT
READY is required for SCSI. It seems the SAT authors didn't consider
this case.
I assume we can tell from the identify data that the device doesn't
support power management and just fake success for TEST UNIT READY in
Management feature set. Whereas TEST UNIT
READY is required for SCSI. It seems the SAT authors didn't consider
this case.
I assume we can tell from the identify data that the device doesn't
support power management and just fake success for TEST UNIT READY in
this case?
--
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Yinghai Lu wrote:
On 9/22/07, Robert Hancock <[EMAIL PROTECTED]> wrote:
Thomas Gleixner wrote:
On Sat, 2007-09-22 at 10:28 -0600, Robert Hancock wrote:
Yinghai Lu wrote:
No!
MMCONFIG will not work with acpi=off any more.
I don't think this is unreasonable. The ACPI MCFG table is
Thomas Gleixner wrote:
On Sat, 2007-09-22 at 10:28 -0600, Robert Hancock wrote:
Yinghai Lu wrote:
No!
MMCONFIG will not work with acpi=off any more.
I don't think this is unreasonable. The ACPI MCFG table is how we are
supposed to learn about the area in the first place. If we can't get
Yinghai Lu wrote:
No!
MMCONFIG will not work with acpi=off any more.
I don't think this is unreasonable. The ACPI MCFG table is how we are
supposed to learn about the area in the first place. If we can't get the
table location via an approved mechanism, and can't validate it doesn't
Yinghai Lu wrote:
No!
MMCONFIG will not work with acpi=off any more.
I don't think this is unreasonable. The ACPI MCFG table is how we are
supposed to learn about the area in the first place. If we can't get the
table location via an approved mechanism, and can't validate it doesn't
Thomas Gleixner wrote:
On Sat, 2007-09-22 at 10:28 -0600, Robert Hancock wrote:
Yinghai Lu wrote:
No!
MMCONFIG will not work with acpi=off any more.
I don't think this is unreasonable. The ACPI MCFG table is how we are
supposed to learn about the area in the first place. If we can't get
Yinghai Lu wrote:
On 9/22/07, Robert Hancock [EMAIL PROTECTED] wrote:
Thomas Gleixner wrote:
On Sat, 2007-09-22 at 10:28 -0600, Robert Hancock wrote:
Yinghai Lu wrote:
No!
MMCONFIG will not work with acpi=off any more.
I don't think this is unreasonable. The ACPI MCFG table is how we
worse, not better, as it allows
more memory to be allocated for each socket. I should think you want to
adjust those values down, not up..
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worse, not better, as it allows
more memory to be allocated for each socket. I should think you want to
adjust those values down, not up..
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be feasible to delay it further.
Nevertheless, I think this is a rather ugly workaround for the
underlying problem.
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be feasible to delay it further.
Nevertheless, I think this is a rather ugly workaround for the
underlying problem.
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Benjamin Herrenschmidt wrote:
On Thu, 2007-09-13 at 21:32 -0600, Robert Hancock wrote:
If we do encounter other devices that choke on having the BAR
disabled
during probing then we can add additional quirk logic, but we haven't
run into anything like that yet.
Well... if the device needs
Ivan Kokshaysky wrote:
On Fri, Sep 14, 2007 at 05:53:58PM -0600, Robert Hancock wrote:
In the first one, Linus talks about a USB controller whose SMM code
chokes on the BAR being disabled. That explanation seems odd to me. If
it chokes on the BAR disabled, how doesn't it choke on the BAR being
Ivan Kokshaysky wrote:
On Fri, Sep 14, 2007 at 05:53:58PM -0600, Robert Hancock wrote:
In the first one, Linus talks about a USB controller whose SMM code
chokes on the BAR being disabled. That explanation seems odd to me. If
it chokes on the BAR disabled, how doesn't it choke on the BAR being
Benjamin Herrenschmidt wrote:
On Thu, 2007-09-13 at 21:32 -0600, Robert Hancock wrote:
If we do encounter other devices that choke on having the BAR
disabled
during probing then we can add additional quirk logic, but we haven't
run into anything like that yet.
Well... if the device needs
Yinghai Lu wrote:
On 9/14/07, Robert Hancock <[EMAIL PROTECTED]> wrote:
It's not impossible at all. In fact I'm quite sure (Jesse can confirm)
that in the case of the board he was using, it was an add-in graphics
card where he saw this problem.
The fact is that in the case of MMCONFIG o
Yinghai Lu wrote:
On 9/14/07, Robert Hancock [EMAIL PROTECTED] wrote:
It's not impossible at all. In fact I'm quite sure (Jesse can confirm)
that in the case of the board he was using, it was an add-in graphics
card where he saw this problem.
The fact is that in the case of MMCONFIG overlap
Ivan Kokshaysky wrote:
On Fri, Sep 14, 2007 at 08:30:59AM -0600, Robert Hancock wrote:
Do you have an example of specific hardware that exhibits this problem?
Well, first two results of google search for "disable bar when sizing":
http://lkml.org/lkml/2002/12/21/95
http://lkml.org
Ivan Kokshaysky wrote:
On Thu, Sep 13, 2007 at 09:32:42PM -0600, Robert Hancock wrote:
Disabling the BAR decoding does not mean disabling the device (aside
from the one group of host bridge that apparently disables CPU to RAM
access, whose designers were apparently on crack when they read
Ivan Kokshaysky wrote:
On Thu, Sep 13, 2007 at 09:32:42PM -0600, Robert Hancock wrote:
Disabling the BAR decoding does not mean disabling the device (aside
from the one group of host bridge that apparently disables CPU to RAM
access, whose designers were apparently on crack when they read
Ivan Kokshaysky wrote:
On Fri, Sep 14, 2007 at 08:30:59AM -0600, Robert Hancock wrote:
Do you have an example of specific hardware that exhibits this problem?
Well, first two results of google search for disable bar when sizing:
http://lkml.org/lkml/2002/12/21/95
http://lkml.org/lkml/2002
r devices that choke on having the BAR disabled
during probing then we can add additional quirk logic, but we haven't
run into anything like that yet.
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the hardware less.
If this is an MCP51 chipset, adma=0 will make no difference since that
chipset does not support ADMA in the first place.
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the hardware less.
If this is an MCP51 chipset, adma=0 will make no difference since that
chipset does not support ADMA in the first place.
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the BAR disabled
during probing then we can add additional quirk logic, but we haven't
run into anything like that yet.
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as been reserved
Which I very much doubt it should be doing, the BIOS doesn't need to
reserve PCI BAR ranges in the ACPI tables. This sounds like a BIOS bug.
You might want to check for an update from Supermicro.
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lt
states.) Theoretically one could track the TSC between different CPUs
running at different clock speeds, etc. and across halts, but it doesn't
really seem worth the trouble, especially in cases like AMD multi-CPU
where the TSC can't be trusted across CPUs anyway.
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or contradict?
I don't know any controller that works in this way. This would greatly
increase CPU overhead since the CPU would need to perform this CRC
calculation.
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or contradict?
I don't know any controller that works in this way. This would greatly
increase CPU overhead since the CPU would need to perform this CRC
calculation.
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. and across halts, but it doesn't
really seem worth the trouble, especially in cases like AMD multi-CPU
where the TSC can't be trusted across CPUs anyway.
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Which I very much doubt it should be doing, the BIOS doesn't need to
reserve PCI BAR ranges in the ACPI tables. This sounds like a BIOS bug.
You might want to check for an update from Supermicro.
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eueing, but it's disabled.
ata_piix does not support NCQ. You have to use AHCI mode for that.
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, but it's disabled.
ata_piix does not support NCQ. You have to use AHCI mode for that.
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he same checks that access_ok does.
I'm not aware of any code in the kernel that does userspace-to-userspace
copies directly. Likely because there's rarely a need for it?
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does.
I'm not aware of any code in the kernel that does userspace-to-userspace
copies directly. Likely because there's rarely a need for it?
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between the motherboard and the drive. I
suspect this is something that the system manufacturer has to validate
works properly, more than any hard and fast limit.
For a normal desktop PC, it would be far better to just use an 80-wire
cable.
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between the motherboard and the drive. I
suspect this is something that the system manufacturer has to validate
works properly, more than any hard and fast limit.
For a normal desktop PC, it would be far better to just use an 80-wire
cable.
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pplication when there is a lot of memory swapped out.
Normally mlockall is what is used in this sort of situation, that way it
doesn't force all swapped data in for every app. It's possible that
calling this with lots of swapped pages in the app at the time may have
the same problem though.
circumstances is this actually happening? What are these
functions that are being called?
Normally things are set up such that this isn't a problem, i.e. if
module A depends on module B, module A can't load until module B is
finished loading.
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sugggested disabling the
write-back cache on some Smart Array controllers as a workaround because
it reduced performance in applications that did large bulk writes.
Presumably they are planning on releasing some updated firmware that
fixes this eventually..
--
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it reduced performance in applications that did large bulk writes.
Presumably they are planning on releasing some updated firmware that
fixes this eventually..
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circumstances is this actually happening? What are these
functions that are being called?
Normally things are set up such that this isn't a problem, i.e. if
module A depends on module B, module A can't load until module B is
finished loading.
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when there is a lot of memory swapped out.
Normally mlockall is what is used in this sort of situation, that way it
doesn't force all swapped data in for every app. It's possible that
calling this with lots of swapped pages in the app at the time may have
the same problem though.
--
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this intentionally.
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More maj
Matthew Wilcox wrote:
On Sun, Aug 26, 2007 at 06:55:42AM -0600, Matthew Wilcox wrote:
On Sat, Aug 25, 2007 at 10:24:57PM -0600, Robert Hancock wrote:
We've already got a patch for this in Greg's PCI tree, hopefully it
should go in for 2.6.24.
I haven't seen it. I guess it wasn't sent
Matthew Wilcox wrote:
On Sun, Aug 26, 2007 at 06:55:42AM -0600, Matthew Wilcox wrote:
On Sat, Aug 25, 2007 at 10:24:57PM -0600, Robert Hancock wrote:
We've already got a patch for this in Greg's PCI tree, hopefully it
should go in for 2.6.24.
I haven't seen it. I guess it wasn't sent
this intentionally.
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More majordomo info at http
like you have some CONFIG_IDE options enabled in your kernel
configuration that result in drivers/ide trying to drive part or all of
that controller, preventing libata from doing so. Likely the easiest
thing to do is just set CONFIG_IDE=n entirely..
--
Robert Hancock Saskatoon, SK, Canada
Matthew Wilcox wrote:
This patch, loosely based on a patch from Robert Hancock, which was in
turn based on a patch from Jesse Barnes, fixes a boot-time hang on my
shiny new PC. The 'conflict' mentioned in the patch in my case happens
to be between mmconfig and the graphics card, but it could
Matthew Wilcox wrote:
This patch, loosely based on a patch from Robert Hancock, which was in
turn based on a patch from Jesse Barnes, fixes a boot-time hang on my
shiny new PC. The 'conflict' mentioned in the patch in my case happens
to be between mmconfig and the graphics card, but it could
in your kernel
configuration that result in drivers/ide trying to drive part or all of
that controller, preventing libata from doing so. Likely the easiest
thing to do is just set CONFIG_IDE=n entirely..
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Robert Hancock Saskatoon, SK, Canada
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drive is reporting an error on a write to the disc. It's not
an error code in the MMC5 standard, though, so presumably it's a
vendor-specific error code.
Not sure why it would be writing to the disc though.. Maybe if the disc
is mounted read-write it is doing last-access-time updates or something?
--
drive, bad SATA cable, insufficient
power, etc.) or maybe this is another drive with broken NCQ..
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Robert Hancock Saskatoon, SK, Canada
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dware" on it, or something like that. Mount/unmount doesn't
really indicate whether the device is in use in Linux, though, since it
can still be potentially accessed even when the device isn't mounted.
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Robert Hancock Saskatoon, SK, Canada
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on it, or something like that. Mount/unmount doesn't
really indicate whether the device is in use in Linux, though, since it
can still be potentially accessed even when the device isn't mounted.
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Robert Hancock Saskatoon, SK, Canada
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drive, bad SATA cable, insufficient
power, etc.) or maybe this is another drive with broken NCQ..
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Robert Hancock Saskatoon, SK, Canada
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?
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sed to be used to
provide entropy, however in later kernels this was taken out as it was
thought unsafe, since an attacker could detect or control the timing of
these packets and thus determine the contents of the entropy pool.
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Robert Hancock Saskatoon, SK, Canada
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to be used to
provide entropy, however in later kernels this was taken out as it was
thought unsafe, since an attacker could detect or control the timing of
these packets and thus determine the contents of the entropy pool.
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Robert Hancock Saskatoon, SK, Canada
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