On 2020-11-05 08:31, Markus Reichl wrote:
Hi Marek,
on rk3399 the proposed ordering [1] is according to base address in DT.
FWIW, note that in RK3399's case the SoC itself provides no logical
numbering to follow - the pin groups are named "EMMC", "SDIO0" and
"SDMMC0" in the datasheet, while
he rest of the diff from v4 looks OK to me. Good catch on
the affinity hint in put_irq - looks like that was my bug from the
original proof-of-concept implementation :)
With those last two nits above fixed,
Reviewed-by: Robin Murphy
Cheers,
Robin.
+#include
+#inc
On 2020-11-04 14:15, Markus Bauer wrote:
Remove error messages that might confuse users when error is just -517 /
-EPROBE_DEFER.
[...]
imx-dwmac 30bf.ethernet: Cannot register the MDIO bus
imx-dwmac 30bf.ethernet: stmmac_dvr_probe: MDIO bus (id: 0) registration
failed
[...]
FYI we ha
On 2020-11-04 11:15, Markus Reichl wrote:
Hi Heiko,
Am 04.11.20 um 11:51 schrieb Heiko Stübner:
Hi Markus,
Am Mittwoch, 4. November 2020, 10:49:45 CET schrieb Markus Reichl:
Recently introduced async probe on mmc devices can shuffle block IDs.
Pin them to fixed values to ease booting in eviro
On 2020-11-04 08:14, Maxime Ripard wrote:
Hi Christoph,
On Tue, Nov 03, 2020 at 10:55:38AM +0100, Christoph Hellwig wrote:
Linux 5.10-rc1 switched from having a single dma offset in struct device
to a set of DMA ranges, and introduced a new helper to set them,
dma_direct_set_offset.
This in fa
On 2020-11-03 17:56, John Garry wrote:
To summarize, the issue is that as time goes by, the CPU rcache and
depot
rcache continue to grow. As such, IOVA RB tree access time also
continues
to grow.
Hi Robin,
I'm struggling to see how this is not simply indicative of a leak
originating elsew
On 2020-10-26 17:31, John Garry wrote:
Leizhen reported some time ago that IOVA performance may degrade over time
[0], but unfortunately his solution to fix this problem was not given
attention.
To summarize, the issue is that as time goes by, the CPU rcache and depot
rcache continue to grow. As
On 2020-11-03 14:31, John Garry wrote:
On 03/11/2020 12:35, Robin Murphy wrote:
On 2020-09-30 08:44, vji...@codeaurora.org wrote:
From: Vijayanand Jitta
When ever an iova alloc request fails we free the iova
ranges present in the percpu iova rcaches and then retry
but the global iova rcache
own in the middle of the loops so nothing can reasonably be
factored out :(
Reviewed-by: Robin Murphy
Signed-off-by: Vijayanand Jitta
---
drivers/iommu/iova.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/iommu/iova.c b/drivers/iommu/iova.c
index c3a1a8
On 2020-09-27 07:34, Lu Baolu wrote:
Combining the sg segments exposes a bug in the Intel i915 driver which
causes visual artifacts and the screen to freeze. This is most likely
because of how the i915 handles the returned list. It probably doesn't
respect the returned value specifying the number
On 2020-11-03 07:49, Qinglang Miao wrote:
Fix the missing clk_disable_unprepare() of info->pclk
before return from rockchip_saradc_resume in the error
handling case when fails to prepare and enable info->clk.
Fixes: 44d6f2ef94f9 ("iio: adc: add driver for Rockchip saradc")
Signed-off-by: Qinglan
On 2020-11-02 18:22, Robin Murphy wrote:
On 2020-11-02 17:14, Jordan Crouse wrote:
Every Qcom Adreno GPU has an embedded SMMU for its own use. These
devices depend on unique features such as split pagetables,
different stall/halt requirements and other settings. Identify them
with a compatible
On 2020-11-02 17:14, Jordan Crouse wrote:
Every Qcom Adreno GPU has an embedded SMMU for its own use. These
devices depend on unique features such as split pagetables,
different stall/halt requirements and other settings. Identify them
with a compatible string so that they can be identified in th
On 2020-11-02 17:14, Jordan Crouse wrote:
From: Rob Clark
For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
pending translations are not terminated on iova fault. Otherwise
a terminated CP read could hang the GPU by returning invalid
command-stream data.
Signed-off-by: Rob Cla
ontext bank 0
outright in cfg_probe, then just swizzle cbndx/irptndx at this point
once everything else has proven that this is to be the One Special
Domain. I guess this way at least you don't have to intervene in
domain_free, but by the same token that means you never get to clean up
the d
On 2020-10-30 01:02, John Stultz wrote:
On Wed, Oct 28, 2020 at 7:51 AM Robin Murphy wrote:
Hmm, perhaps I'm missing something here, but even if the config options
*do* line up, what prevents arm-smmu probing before qcom-scm and
dereferencing NULL in qcom_scm_qsmmu500_wait_safe_toggle() b
On 2020-10-29 13:07, Ezequiel Garcia wrote:
Hello Adrian,
On Mon, 2020-10-12 at 23:59 +0300, Adrian Ratiu wrote:
Dear all,
This series introduces a regmap infrastructure for the Hantro driver
which is used to compensate for different HW-revision register layouts.
To justify it h264 decoding ca
On 2020-10-29 13:19, yukuai (C) wrote:
On 2020/10/29 18:08, Robin Murphy wrote:
On 2020-10-29 09:22, Yu Kuai wrote:
If of_find_device_by_node() failed in rk_iommu_of_xlate(), null pointer
dereference will be triggered. Thus return error code if
of_find_device_by_node() failed.
How can that
On 2020-10-29 07:42, Coiby Xu wrote:
SET_SYSTEM_SLEEP_PM_OPS has already took good care of CONFIG_PM_CONFIG.
I don't see anything in the !CONFIG_PM_CONFIG side of
SET_SYSTEM_SLEEP_PM_OPS() that prevents unused function warnings for the
callbacks - does this change depend on some other patch o
On 2020-10-29 09:22, Yu Kuai wrote:
If of_find_device_by_node() failed in sun50i_iommu_of_xlate(), null
pointer dereference will be triggered. Thus return error code if
of_find_device_by_node() failed.
Again, by what means can that ever actually happen?
Robin.
Fixes: 4100b8c229b3("iommu: Add
On 2020-10-29 09:22, Yu Kuai wrote:
If of_find_device_by_node() failed in rk_iommu_of_xlate(), null pointer
dereference will be triggered. Thus return error code if
of_find_device_by_node() failed.
How can that happen? (Given that ".suppress_bind_attrs = true")
Robin.
Fixes: 5fd577c3eac3("io
On 2020-10-28 13:51, Will Deacon wrote:
On Tue, Oct 27, 2020 at 10:53:47PM -0700, John Stultz wrote:
On Mon, Jul 13, 2020 at 1:41 PM Will Deacon wrote:
On Fri, Jul 10, 2020 at 03:21:53PM -0700, John Stultz wrote:
On Fri, Jul 10, 2020 at 12:54 AM Will Deacon wrote:
On Thu, Jul 09, 2020 at 08
On 2020-10-26 18:54, Jordan Crouse wrote:
This is an extension to the series [1] to enable the System Cache (LLC) for
Adreno a6xx targets.
GPU targets with an MMU-500 attached have a slightly different process for
enabling system cache. Use the compatible string on the IOMMU phandle
to see if an
On 2020-10-23 19:23, Tuan Phan wrote:
On Oct 23, 2020, at 6:43 AM, Robin Murphy wrote:
On 2020-10-22 22:46, Tuan Phan wrote:
[...]
+#define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \
+ attr)->cfg) >> lo) & GENMASK(hi - lo, 0))
As per the bu
Offering DMA_PERNUMA_CMA to non-NUMA configs is pointless.
Signed-off-by: Robin Murphy
---
kernel/dma/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig
index c99de4a21458..964b74c9b7e3 100644
--- a/kernel/dma/Kconfig
+++ b
On 2020-10-26 07:41, Yong Wu wrote:
On Fri, 2020-10-23 at 15:10 +0100, Robin Murphy wrote:
On 2020-09-30 08:06, Yong Wu wrote:
The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
(4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
34bit.
Signed-off-by: Yong
On 2020-10-23 06:57, chao hao wrote:
On Wed, 2020-10-21 at 17:55 +0100, Robin Murphy wrote:
On 2020-10-19 12:30, Chao Hao wrote:
MTK_IOMMU driver writes one page entry and does tlb flush at a time
currently. More optimal would be to aggregate the writes and flush
BUS buffer in the end
On 2020-09-30 08:06, Yong Wu wrote:
The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
(4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
34bit.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 13 ++---
drivers/iommu/mtk_iommu.c
On 2020-10-22 22:46, Tuan Phan wrote:
[...]
+#define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \
+ attr)->cfg) >> lo) & GENMASK(hi - lo, 0))
As per the buildbot report, GENMASK_ULL() would be appropriate when the other
side is a u64 (although either way this does look a
On 2020-10-23 13:19, Tomasz Nowicki wrote:
Hi Denis,
Sorry for late response, we had to check few things. Please see comments
inline.
On 10/6/20 3:16 PM, Denis Odintsov wrote:
Hi,
Am 15.07.2020 um 09:06 schrieb Tomasz Nowicki :
The series is meant to support SMMU for AP806 and a workaroun
On 2020-10-21 00:10, Tuan Phan wrote:
DMC-620 PMU supports total 10 counters which each is
independently programmable to different events and can
be started and stopped individually.
Currently, it only supports ACPI. Other platforms feel free to test and add
support for device tree.
Usage examp
On 2020-10-22 02:07, Vanshi Konda wrote:
On Thu, Oct 22, 2020 at 12:44:15AM +0100, Robin Murphy wrote:
On 2020-10-21 12:02, Jonathan Cameron wrote:
On Wed, 21 Oct 2020 09:43:21 +0530
Anshuman Khandual wrote:
On 10/20/2020 11:39 PM, Valentin Schneider wrote:
Hi,
Nit on the subject: this
On 2020-10-21 12:02, Jonathan Cameron wrote:
On Wed, 21 Oct 2020 09:43:21 +0530
Anshuman Khandual wrote:
On 10/20/2020 11:39 PM, Valentin Schneider wrote:
Hi,
Nit on the subject: this only increases the default, the max is still 2¹⁰.
Agreed.
On 20/10/20 18:34, Vanshidhar Konda wrote:
On 2020-10-19 12:30, Chao Hao wrote:
MTK_IOMMU driver writes one page entry and does tlb flush at a time
currently. More optimal would be to aggregate the writes and flush
BUS buffer in the end.
That's exactly what iommu_iotlb_gather_add_page() is meant to achieve.
Rather than jumping straight
having it all spelled out, so regardless,
Acked-by: Robin Murphy
Cheers,
Robin.
+
+ set_bit(qsmmu->bypass_cbndx, smmu->context_map);
+
+ reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE,
CBAR_TYPE_S1_TRANS_S2_BYPASS);
+ arm_smmu_gr1_write(smmu,
ARM_SMMU_GR1_CBAR(
mappings during initialization and make the
arm-smmu driver maintain the streams in bypass mode.
Acked-by: Robin Murphy
Signed-off-by: Bjorn Andersson
---
Changes since v4:
- Don't increment s2cr[i]->count, as this is not actually needed to survive
probe deferral
drivers/iommu/arm/
On 2020-10-17 05:39, Bjorn Andersson wrote:
The firmware found in some Qualcomm platforms intercepts writes to S2CR
in order to replace bypass type streams with fault; and ignore S2CR
updates of type fault.
Detect this behavior and implement a custom write_s2cr function in order
to trick the fir
On 2020-10-17 05:39, Bjorn Andersson wrote:
The Qualcomm boot loader configures stream mapping for the peripherals
that it accesses and in particular it sets up the stream mapping for the
display controller to be allowed to scan out a splash screen or EFI
framebuffer.
Read back the stream mappin
reasonable level of abstraction to
me - we'll still have plenty of flexibility to adjust things in future
if necessary.
With that change,
Reviewed-by: Robin Murphy
+ } else {
+ reg = FIELD_PREP(ARM_SMMU_S2CR_TYPE, s2cr->type) |
+ FIELD_P
On 2020-10-17 02:56, Nicolin Chen wrote:
On Fri, Oct 16, 2020 at 03:10:26PM +0100, Robin Murphy wrote:
On 2020-10-16 04:53, Nicolin Chen wrote:
On Thu, Oct 15, 2020 at 10:55:52AM +0100, Robin Murphy wrote:
On 2020-10-15 05:13, Nicolin Chen wrote:
On Wed, Oct 14, 2020 at 06:42:36PM +0100
On 2020-10-16 04:53, Nicolin Chen wrote:
On Thu, Oct 15, 2020 at 10:55:52AM +0100, Robin Murphy wrote:
On 2020-10-15 05:13, Nicolin Chen wrote:
On Wed, Oct 14, 2020 at 06:42:36PM +0100, Robin Murphy wrote:
On 2020-10-09 17:19, Nicolin Chen wrote:
This patch simply adds support for PCI
On 2020-10-14 19:39, Rob Herring wrote:
On Wed, Oct 14, 2020 at 9:54 AM Richard Fitzgerald
wrote:
Add an equivalent of of_count_phandle_with_args() for fixed argument
sets, to pair with of_parse_phandle_with_fixed_args().
Signed-off-by: Richard Fitzgerald
---
drivers/of/base.c | 42 ++
On 2020-10-15 10:52, Jisheng Zhang wrote:
On Thu, 15 Oct 2020 01:48:13 -0700
Saravana Kannan wrote:
On Thu, Oct 15, 2020 at 1:15 AM Jisheng Zhang
wrote:
On Wed, 14 Oct 2020 22:04:24 -0700 Saravana Kannan wrote:
On Wed, Oct 14, 2020 at 9:02 PM Jisheng Zhang
wrote:
On Wed, 14 Oct 202
On 2020-10-15 05:13, Nicolin Chen wrote:
On Wed, Oct 14, 2020 at 06:42:36PM +0100, Robin Murphy wrote:
On 2020-10-09 17:19, Nicolin Chen wrote:
This patch simply adds support for PCI devices.
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
Signed-off-by: Nicolin Chen
---
Changelog
On 2020-10-08 11:15, John Garry wrote:
Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip09
platform.
This contains a mix of architected and IMP def events
Signed-off-by: John Garry
---
.../hisilicon/hip09/sys/smmu-v3-pmcg.json | 42 +++
1 file changed,
On 2020-10-09 17:19, Nicolin Chen wrote:
This patch simply adds support for PCI devices.
Reviewed-by: Dmitry Osipenko
Tested-by: Dmitry Osipenko
Signed-off-by: Nicolin Chen
---
Changelog
v6->v7
* Renamed goto labels, suggested by Thierry.
v5->v6
* Added Dmitry's Reviewed-by and Tested-by
On 2020-10-14 17:52, Ard Biesheuvel wrote:
On Mon, 12 Oct 2020 at 13:38, Robin Murphy wrote:
On 2020-10-09 08:55, Jisheng Zhang wrote:
Currently, dw_pcie_msi_init() allocates and maps page for msi, then
program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex
may lose power during
On 2020-10-14 17:27, Helen Koike wrote:
Hi Tomasz,
On 9/26/20 10:00 AM, Tomasz Figa wrote:
Hi Helen,
On Wed, Jul 22, 2020 at 12:55:32PM -0300, Helen Koike wrote:
From: Shunqian Zheng
RK3399 has two ISPs, but only isp0 was tested.
Add isp0 node in rk3399 dtsi
Verified with:
make ARCH=arm64
On 2020-09-26 14:00, khol...@gmail.com wrote:
From: AngeloGioacchino Del Regno
Move the stream mapping reset logic from arm_smmu_device_reset into
a separate arm_smmu_stream_mapping_reset function, in preparation
for implementing an implementation detail.
This commit brings no functional chang
On 2020-09-26 14:00, khol...@gmail.com wrote:
From: AngeloGioacchino Del Regno
At least some Qualcomm SoCs do need to override the function
arm_smmu_test_smr_masks entirely: add a test_smr_masks function
to the implementation details structure and call it properly.
Signed-off-by: AngeloGioacch
On 2020-09-26 13:59, khol...@gmail.com wrote:
From: AngeloGioacchino Del Regno
Some IOMMUs are getting set-up for Shared Virtual Address, but:
1. They are secured by the Hypervisor, so any configuration
change will generate a hyp-fault and crash the system
2. This 39-bits Virtual Address si
On 2020-10-14 15:15, Rob Herring wrote:
On Mon, Oct 12, 2020 at 6:37 AM Robin Murphy wrote:
On 2020-10-09 08:55, Jisheng Zhang wrote:
Currently, dw_pcie_msi_init() allocates and maps page for msi, then
program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex
may lose power during
On 2020-10-13 23:41, Johan Jonker wrote:
Hi Uwe,
On 10/13/20 10:22 PM, Uwe Kleine-König wrote:
Hello Johan,
On 10/13/20 7:34 PM, Johan Jonker wrote:
Part 1 of 2 missing here.
Please complain to gmail then, given that patch 1 can be found on
https://lore.kernel.org/linux-arm-kernel/2020101
On 2020-10-12 08:31, Bjorn Andersson wrote:
On Mon 21 Sep 23:08 CEST 2020, Will Deacon wrote:
On Sat, Sep 12, 2020 at 10:25:59PM -0500, Bjorn Andersson wrote:
On Fri 11 Sep 12:13 CDT 2020, Robin Murphy wrote:
On 2020-09-04 16:55, Bjorn Andersson wrote:
Add a new operation to allow platform
On 2020-10-13 14:39, Neil Armstrong wrote:
In order to reduce the kernel Image size on multi-platform distributions,
make it possible to build the reset controller driver as a module.
This partially reverts 8290924e ("reset: meson: make it explicitly non-modular")
Signed-off-by: Neil Armstrong
On 2020-10-07 07:25, Christoph Hellwig wrote:
On Tue, Oct 06, 2020 at 09:19:32AM -0400, Jonathan Marek wrote:
One example why drm/msm can't use DMA API is multiple page table support
(that is landing in 5.10), which is something that definitely couldn't work
with DMA API.
Another one is being a
On 2020-10-06 16:16, Denis Odintsov wrote:
Hi,
Am 15.07.2020 um 09:06 schrieb Tomasz Nowicki :
The series is meant to support SMMU for AP806 and a workaround
for accessing ARM SMMU 64bit registers is the gist of it.
For the record, AP-806 can't access SMMU registers with 64bit width.
This pat
On 2020-10-09 08:55, Jisheng Zhang wrote:
Currently, dw_pcie_msi_init() allocates and maps page for msi, then
program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex
may lose power during suspend-to-RAM, so when we resume, we want to
redo the latter but not the former. If designware b
ose they would start faulting once we enable DMA/IOMMU integration
for Tegra SMMU if they have a bootloader that does initialize display to
actively scan out during boot.
I think Robin Murphy already suggested that we should simply create
a dummy "identity" IOMMU domain by default for the
On 2020-09-25 10:51, John Garry wrote:
Leizhen reported some time ago that IOVA performance may degrade over time
[0], but unfortunately his solution to fix this problem was not given
attention.
To summarize, the issue is that as time goes by, the CPU rcache and depot
rcache continue to grow. As
On 2020-09-15 16:51, Christoph Hellwig wrote:
[...]
+These APIs allow to allocate pages in the kernel direct mapping that are
+guaranteed to be DMA addressable. This means that unlike dma_alloc_coherent,
+virt_to_page can be called on the resulting address, and the resulting
Nit: if we explici
On 2020-09-23 11:14, Suravee Suthikulpanit wrote:
Add initial hook up code to implement generic IO page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/Kconfig | 1 +
drivers/iommu/amd/Makefile | 2 +-
drivers/iommu/amd/amd_iommu_types.h | 32
On 2020-09-24 10:25, Joerg Roedel wrote:
Hi Robin,
On Thu, Sep 24, 2020 at 10:08:46AM +0100, Robin Murphy wrote:
This should be fixed by
https://lore.kernel.org/linux-iommu/daedc9364a19dc07487e4d07b8768b1e5934abd4.1600700881.git.robin.mur...@arm.com/T/#u
(already in linux-next).
Thanks! The
Hi Joerg,
On 2020-09-24 10:03, Joerg Roedel wrote:
Adding Will and Robin.
This should be fixed by
https://lore.kernel.org/linux-iommu/daedc9364a19dc07487e4d07b8768b1e5934abd4.1600700881.git.robin.mur...@arm.com/T/#u
(already in linux-next).
Thanks,
Robin.
On Mon, Sep 21, 2020 at 06:50:40
On 2020-09-23 15:53, Charan Teja Reddy wrote:
In of_iommu_xlate(), check if iommu device is enabled before traversing
the iommu_device_list through iommu_ops_from_fwnode(). It is of no use
in traversing the iommu_device_list only to return NO_IOMMU because of
iommu device node is disabled.
Well
On 2020-09-22 07:18, Sai Prakash Ranjan wrote:
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12
1
On 2020-09-23 07:59, Jian-Hong Pan wrote:
The cdn-dp sub driver probes the device failed on PINEBOOK Pro.
kernel: cdn-dp fec0.dp: [drm:cdn_dp_probe [rockchipdrm]] *ERROR* missing
extcon or phy
kernel: cdn-dp: probe of fec0.dp failed with error -22
Wouldn't it make more sense to simply
On 2020-09-15 09:31, Tvrtko Ursulin wrote:
On 15/09/2020 02:47, Lu Baolu wrote:
Hi Tvrtko,
On 9/14/20 4:04 PM, Tvrtko Ursulin wrote:
Hi,
On 12/09/2020 04:21, Lu Baolu wrote:
Tom Murphy has almost done all the work. His latest patch series was
posted here.
https://lore.kernel.org/linux-iom
On 2020-09-18 21:47, Logan Gunthorpe wrote:
Hi Lu,
On 2020-09-11 9:21 p.m., Lu Baolu wrote:
Tom Murphy has almost done all the work. His latest patch series was
posted here.
https://lore.kernel.org/linux-iommu/20200903201839.7327-1-murph...@tcd.ie/
Thanks a lot!
This series is a follow-up wi
On 2020-09-21 19:03, Will Deacon wrote:
On Fri, Sep 11, 2020 at 07:57:18PM +0530, Sai Prakash Ranjan wrote:
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
I wonder if the panfrost folks can reuse this for the issu
On 2020-09-21 14:20, Naresh Kamboju wrote:
[...]
[2.256403] e1000e :01:00.0: Adding to iommu group 0
[2.261733] arm-smmu 500.iommu: Cannot accommodate DMA offset
for IOMMU page tables
Ah, I know what's going on there - the dma_range_map stuff has
overlooked a subtlety, but it's
On 2020-08-21 19:10, Tuan Phan wrote:
DMC-620 PMU supports total 10 counters which each is
independently programmable to different events and can
be started and stopped individually.
Currently, it only supports ACPI. Other platforms feel free to test and add
support for device tree.
[ Note to
On 2020-08-20 13:49, vji...@codeaurora.org wrote:
From: Vijayanand Jitta
When ever an iova alloc request fails we free the iova
ranges present in the percpu iova rcaches and then retry
but the global iova rcache is not freed as a result we could
still see iova alloc failure even after retry as
that, I think this looks OK (IIRC it's basically what I
originally suggested), so with the naming tweaked,
Reviewed-by: Robin Murphy
+
+retry:
do {
- limit_pfn = min(limit_pfn, curr_iova->pfn_lo);
- new_pfn = (limit_pfn - size) & align_mask;
+
v)
Looks good to me, but Robin should also have a look.
Yup, seems reasonable, thanks Tom!
Reviewed-by: Robin Murphy
On 2020-09-17 04:35, Gavin Shan wrote:
Hi Will,
On 9/16/20 6:28 PM, Will Deacon wrote:
On Wed, Sep 16, 2020 at 01:25:23PM +1000, Gavin Shan wrote:
This enables color zero pages by allocating contigous page frames
for it. The number of pages for this is determined by L1 dCache
(or iCache) size,
On 2020-09-16 09:28, Will Deacon wrote:
On Wed, Sep 16, 2020 at 01:25:23PM +1000, Gavin Shan wrote:
This enables color zero pages by allocating contigous page frames
for it. The number of pages for this is determined by L1 dCache
(or iCache) size, which is probbed from the hardware.
* Add c
On 2020-09-04 16:55, Bjorn Andersson wrote:
With many Qualcomm platforms not having functional S2CR BYPASS a
temporary IOMMU domain, without translation, needs to be allocated in
order to allow these memory transactions.
Unfortunately the boot loader uses the first few context banks, so
rather t
On 2020-09-04 16:55, Bjorn Andersson wrote:
Add a new operation to allow platform implementations to inherit any
stream mappings from the boot loader.
Is there a reason we need an explicit step for this? The aim of the
cfg_probe hook is that the SMMU software state should all be set up by
the
On 2020-09-11 17:21, Sai Prakash Ranjan wrote:
On 2020-09-11 21:37, Will Deacon wrote:
On Fri, Sep 11, 2020 at 05:03:06PM +0100, Robin Murphy wrote:
BTW am I supposed to have received 3 copies of everything? Because I
did...
Yeah, this seems to be happening for all of Sai's e
XXX(hch): this has no business in a driver and needs to move
+* to the device tree.
+*/
Apparently this one *does* want updating to use the MBUS interconnect
bindings - as does the cedrus instance below - so no complaint there :)
Other than those few trivial nitpicks, I think I
On 2020-09-11 15:28, Sai Prakash Ranjan wrote:
There are few places in arm-smmu-impl where there are
extra blank lines, remove them
FWIW those were deliberate - sometimes I like a bit of subtle space to
visually delineate distinct groups of definitions. I suppose it won't be
to everyone's tas
On 2020-09-11 12:15, Russell King - ARM Linux admin wrote:
On Thu, Sep 10, 2020 at 07:40:37AM +0200, Christoph Hellwig wrote:
The DMA offset notifier can only be used if PHYS_OFFSET is at least
KEYSTONE_HIGH_PHYS_START, which can't be represented by a 32-bit
phys_addr_t. Currently the code comp
t something to worry about in this series.
Reviewed-by: Robin Murphy
Signed-off-by: Christoph Hellwig
---
arch/arm/mach-keystone/keystone.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-keystone/keystone.c
b/arch/arm/mach-keystone/keystone.c
index 638808c4e12247..d
On 2020-09-08 17:47, Christoph Hellwig wrote:
Move the detailed gfp_t setup from __dma_direct_alloc_pages into the
caller to clean things up a little.
Other than a mild nitpick that it might be nicer to spend one extra line
to keep both gfp adjustments next to each other,
Reviewed-by: Robin
On 2020-09-08 17:47, Christoph Hellwig wrote:
Just merge these helpers into the main dma_direct_{alloc,free} routines,
as the additional checks are always false for the two callers.
Reviewed-by: Robin Murphy
Signed-off-by: Christoph Hellwig
---
arch/x86/kernel/amd_gart_64.c | 6
o great objection to this one-liner as-is, so
(modulo the couple of commit message typos),
Reviewed-by: Robin Murphy
(of course the hunk below is unquestionably OK)
Robin.
help
This option is selected by any driver which registers a
diff --git a/kernel/dma/Kconfig b/kern
o_dma.
Reviewed-by: Robin Murphy
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/dma-direct.h | 2 +-
arch/mips/bmips/dma.c | 2 +-
arch/mips/cavium-octeon/dma-octeon.c | 2 +-
arch/mips/include/asm/dma-direct.h | 2 +-
arch/mips/loongson2ef/fuloo
On 2020-09-08 17:47, Christoph Hellwig wrote:
Add a new file that contains helpera for misc DMA ops, which is only
The Latin plural of the singular "helperum", I guess? :P
built when CONFIG_DMA_OPS is set.
Reviewed-by: Robin Murphy
Signed-off-by: Christoph Hellwig
---
hacks), so meh.
Reviewed-by: Robin Murphy
Signed-off-by: Christoph Hellwig
---
Documentation/core-api/dma-api.rst | 24
kernel/dma/coherent.c | 17 +
2 files changed, 17 insertions(+), 24 deletions(-)
diff --git a/Documentation/core-ap
On 2020-09-09 21:06, Joe Perches wrote:
fallthrough to a separate case/default label break; isn't very readable.
Convert pseudo-keyword fallthrough; statements to a simple break; when
the next label is case or default and the only statement in the next
label block is break;
Found using:
$ grep
,
Reviewed-by: Robin Murphy
However I do wonder how much of this could be cleaned up further...
Signed-off-by: Christoph Hellwig
---
arch/arm/common/dmabounce.c| 2 +-
arch/arm/include/asm/dma-direct.h | 70 ++
arch/arm/include/asm/dma-mapping.h | 70
ng that it all does
just come back to __sme_clr(), which is indeed a no-op for everyone
other than AMD, any simplification of this mess is indeed welcome :)
Unless I've massively misunderstood how SME is supposed to work,
Reviewed-by: Robin Murphy
Signed-off-by: Christoph Hellwig
---
a
On 2020-09-08 17:47, Christoph Hellwig wrote:
Replace the currently open code copy.
Reviewed-by: Robin Murphy
Signed-off-by: Christoph Hellwig
---
kernel/dma/direct.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index
On 2020-09-09 06:32, Srinath Mannam wrote:
Fix IOVA reserve failure for memory regions listed in dma-ranges in the
following cases.
- start address of memory region is 0x0.
That's fair enough, and in fact generalises to the case of zero-sized
gaps between regions, which is indeed an oversight
On 2020-09-04 11:23, Mauro Carvalho Chehab wrote:
This RFC adds what seems to be needed for USB to work with Hikey 970.
While this driver works fine on Kernel 4.9 and 4.19, there's a hack there,
in the form of some special binding logic under dwg3 driver, that seems to
be just adding some dela
Hi Joerg,
On 2020-09-04 10:37, Joerg Roedel wrote:
Adding Robin.
Did you miss that I've reviewed this already? :)
https://lore.kernel.org/linux-iommu/3afcc7b2-0bfb-b79c-513f-1beb66c5f...@arm.com/
Robin.
On Thu, Aug 27, 2020 at 04:43:54PM +0800, Shaokun Zhang wrote:
From: Yuqi Jin
The pe
Since commit 9495b7e92f71 ("driver core: platform: Initialize dma_parms
for platform devices"), struct platform_device already provides a
dma_parms structure, so we can save allocating another one.
Signed-off-by: Robin Murphy
---
drivers/mmc/host/renesas_sdhi_internal_dmac.c | 4 --
On 2020-09-02 07:50, Elaine Zhang wrote:
support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-rk3399.c | 40 ++
On 2020-09-02 07:48, Elaine Zhang wrote:
clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-half-divider.c | 12 +
drivers/clk/rockchip/clk.c | 35
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