On 2020-10-22 16:44, Suzuki Poulose wrote:
On 10/22/20 12:07 PM, Sai Prakash Ranjan wrote:
On 2020-10-22 14:57, Suzuki Poulose wrote:
On 10/22/20 9:02 AM, Sai Prakash Ranjan wrote:
On 2020-10-21 15:38, Suzuki Poulose wrote:
On 10/21/20 8:29 AM, Sai Prakash Ranjan wrote:
On 2020-10-20 21:40
On 2020-10-22 16:27, Sai Prakash Ranjan wrote:
There was a report of NULL pointer dereference in ETF enable
path for perf CS mode with PID monitoring. It is almost 100%
reproducible when the process to monitor is something very
active such as chrome and with ETF as the sink and not ETR
On 2020-10-22 14:57, Suzuki Poulose wrote:
On 10/22/20 9:02 AM, Sai Prakash Ranjan wrote:
On 2020-10-21 15:38, Suzuki Poulose wrote:
On 10/21/20 8:29 AM, Sai Prakash Ranjan wrote:
On 2020-10-20 21:40, Sai Prakash Ranjan wrote:
On 2020-10-14 21:29, Sai Prakash Ranjan wrote:
On 2020-10-14 18
ssible NULL pointer dereference crashes and also check for
kernel events.
Fixes: 3147da92a8a8 ("coresight: tmc-etr: Allocate and free ETR memory buffers
for CPU-wide scenarios")
Suggested-by: Suzuki K Poulose
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresig
Export is_kernel_event() to be used by coresight drivers
in later changes to check for kernel events and bail out.
Suggested-by: Suzuki K Poulose
Signed-off-by: Sai Prakash Ranjan
---
include/linux/perf_event.h | 2 ++
kernel/events/core.c | 3 ++-
2 files changed, 4 insertions(+), 1
xes: 75d7dbd38824 ("coresight: etb10: Add support for CPU-wide trace
scenarios")
Suggested-by: Suzuki K Poulose
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etb10.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtrac
xec
ret_from_fork+0x4/0x18
Fixes: 880af782c6e8 ("coresight: tmc-etf: Add support for CPU-wide trace
scenarios")
Suggested-by: Suzuki K Poulose
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-priv.h| 2 ++
drivers/hwtracing/coresight/coresight-tmc-etf.c |
_in+0x60/0x6c
perf_event_context_sched_in+0x98/0xe0
__perf_event_task_sched_in+0x5c/0xd8
finish_task_switch+0x184/0x1cc
schedule_tail+0x20/0xec
ret_from_fork+0x4/0x18
Sai Prakash Ranjan (4):
perf/core: Export is_kernel_event()
coresight: tmc-etf: Fix NULL ptr derefere
On 2020-10-21 15:38, Suzuki Poulose wrote:
On 10/21/20 8:29 AM, Sai Prakash Ranjan wrote:
On 2020-10-20 21:40, Sai Prakash Ranjan wrote:
On 2020-10-14 21:29, Sai Prakash Ranjan wrote:
On 2020-10-14 18:46, Suzuki K Poulose wrote:
On 10/14/2020 10:36 AM, Sai Prakash Ranjan wrote:
On 2020-10
On 2020-10-20 21:40, Sai Prakash Ranjan wrote:
On 2020-10-14 21:29, Sai Prakash Ranjan wrote:
On 2020-10-14 18:46, Suzuki K Poulose wrote:
On 10/14/2020 10:36 AM, Sai Prakash Ranjan wrote:
On 2020-10-13 22:05, Suzuki K Poulose wrote:
On 10/07/2020 02:00 PM, Sai Prakash Ranjan wrote
On 2020-10-14 21:29, Sai Prakash Ranjan wrote:
On 2020-10-14 18:46, Suzuki K Poulose wrote:
On 10/14/2020 10:36 AM, Sai Prakash Ranjan wrote:
On 2020-10-13 22:05, Suzuki K Poulose wrote:
On 10/07/2020 02:00 PM, Sai Prakash Ranjan wrote:
There was a report of NULL pointer dereference in ETF
Hi Suzuki,
On 2020-10-16 18:45, Suzuki Poulose wrote:
On 10/16/20 12:47 PM, Sai Prakash Ranjan wrote:
Hi Suzuki,
On 2020-10-16 16:51, Suzuki Poulose wrote:
Hi Sai,
On 10/16/20 11:10 AM, Sai Prakash Ranjan wrote:
There is a bug on the systems supporting to skip power up
(qcom,skip-power-up
Hi Suzuki,
On 2020-10-16 16:51, Suzuki Poulose wrote:
Hi Sai,
On 10/16/20 11:10 AM, Sai Prakash Ranjan wrote:
There is a bug on the systems supporting to skip power up
(qcom,skip-power-up) where setting LPOVERRIDE bit(low-power
state override behaviour) will result in CPU hangs/lockups
even
Hi Leo,
On 2020-10-16 14:54, Leo Yan wrote:
Hi Sai,
On Fri, Oct 16, 2020 at 02:10:47PM +0530, Sai Prakash Ranjan wrote:
Hi Leo,
On 2020-10-16 12:54, Leo Yan wrote:
> On Thu, Oct 15, 2020 at 11:40:05PM -0700, Denis Nikitin wrote:
> > Hi Mathieu,
> >
> > I think one o
: 02510a5aa78d ("coresight: etm4x: Add support to skip trace unit power
up")
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
b/drivers
Hi Leo,
On 2020-10-16 12:54, Leo Yan wrote:
On Thu, Oct 15, 2020 at 11:40:05PM -0700, Denis Nikitin wrote:
Hi Mathieu,
I think one of the use cases could be VMs.
Is there isolation between EL1 guest kernels which we can control from
perf
in a system wide mode?
Sorry for suddenly jumping
Hi Suzuki,
On 2020-10-15 19:57, Suzuki K Poulose wrote:
Hi Sai,
On 10/15/2020 01:45 PM, Sai Prakash Ranjan wrote:
On production systems with ETMs enabled, it is preferred to
exclude kernel mode(NS EL1) tracing for security concerns and
support only userspace(NS EL0) tracing. So provide
not affect the
current configuration which has both kernel and userspace
tracing enabled by default.
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/Kconfig| 9 +
drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +-
2 files changed, 14 insertions(+), 1
On 2020-10-14 18:46, Suzuki K Poulose wrote:
On 10/14/2020 10:36 AM, Sai Prakash Ranjan wrote:
On 2020-10-13 22:05, Suzuki K Poulose wrote:
On 10/07/2020 02:00 PM, Sai Prakash Ranjan wrote:
There was a report of NULL pointer dereference in ETF enable
path for perf CS mode with PID monitoring
On 2020-10-13 22:05, Suzuki K Poulose wrote:
On 10/07/2020 02:00 PM, Sai Prakash Ranjan wrote:
There was a report of NULL pointer dereference in ETF enable
path for perf CS mode with PID monitoring. It is almost 100%
reproducible when the process to monitor is something very
active
Hi Suzuki,
On 2020-10-13 22:05, Suzuki K Poulose wrote:
On 10/07/2020 02:00 PM, Sai Prakash Ranjan wrote:
There was a report of NULL pointer dereference in ETF enable
path for perf CS mode with PID monitoring. It is almost 100%
reproducible when the process to monitor is something very
active
perf_event_sched_in+0x60/0x6c
perf_event_context_sched_in+0x98/0xe0
__perf_event_task_sched_in+0x5c/0xd8
finish_task_switch+0x184/0x1cc
schedule_tail+0x20/0xec
ret_from_fork+0x4/0x18
Fixes: 880af782c6e8 ("coresight: tmc-etf: Add support for CPU-wide trace
scenarios")
Signed-off-by: Sai Prak
ctx_flexible_sched_in+0x50/0x74
ctx_sched_in+0xa4/0xa8
perf_event_sched_in+0x60/0x6c
perf_event_context_sched_in+0x98/0xe0
__perf_event_task_sched_in+0x5c/0xd8
finish_task_switch+0x184/0x1cc
schedule_tail+0x20/0xec
ret_from_fork+0x4/0x18
Sai Prakash Ranjan (2):
coresight: tmc-etf: Fix NULL ptr dereference
in alloc_buffer() callback which is called as the part of
etm_setup_aux().
Fixes: 75d7dbd38824 ("coresight: etb10: Add support for CPU-wide trace
scenarios")
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etb10.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletio
On 2020-09-28 17:07, Sai Prakash Ranjan wrote:
There was a report of NULL pointer dereference in ETF enable
path for perf CS mode with PID. It is almost 100% reproducible
when the process to monitor is something very active such as
chrome and only with ETF as the sink. Currently in a bid to
find
On 2020-09-28 21:41, Jordan Crouse wrote:
On Mon, Sep 28, 2020 at 05:56:55PM +0530, Sai Prakash Ranjan wrote:
Hi Jordan,
On 2020-09-23 20:33, Jordan Crouse wrote:
>On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote:
>>From: Sharat Masetty
>>
>>The last l
On 2020-09-23 20:54, Robin Murphy wrote:
On 2020-09-22 07:18, Sai Prakash Ranjan wrote:
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm
Hi Jordan,
On 2020-09-23 20:33, Jordan Crouse wrote:
On Tue, Sep 22, 2020 at 11:48:17AM +0530, Sai Prakash Ranjan wrote:
From: Sharat Masetty
The last level system cache can be partitioned to 32 different
slices of which GPU has two slices preallocated. One slice is
used for caching GPU
ck to both TRCVMIDCCTLR0 and TRCVMIDCCTLR1
in etm4x_cpu_restore(). There is already a trcvmidcctlr1 state
variable available for TRCVMIDCCTLR1, so use it.
Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power
states")
Reviewed-by: Suzuki K Poulose
Signed-off-by
Prakash Ranjan (2):
coresight: tmc-etf: Fix NULL pointer dereference in
tmc_enable_etf_sink_perf()
coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register
drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++--
drivers/hwtracing/coresight/coresight-tmc-etf.c| 3 +++
2 files
finish_task_switch+0x184/0x1cc
schedule_tail+0x20/0xec
ret_from_fork+0x4/0x18
Signed-off-by: Sai Prakash Ranjan
---
I am not sure of this incomplete solution hence the RFC. This issue was also
reported when this code was first added [1] but somehow it didn't get much
notice at the time. So
Hi Suzuki,
On 2020-09-28 16:35, Suzuki K Poulose wrote:
Hi Sai,
On 09/27/2020 05:20 PM, Sai Prakash Ranjan wrote:
In commit f188b5e76aae ("coresight: etm4x: Save/restore state
across CPU low power states"), mistakenly TRCVMIDCCTLR1 register
value was saved in trcvmidcctlr0 stat
Hi Prasad,
On 2020-09-28 06:04, Prasad Sodagudi wrote:
Qualcomm team have tried to upstreaming the register trace buffer(RTB)
use case earlier - [1]
with pstore approach. In that discussion, there was suggestion to use
the ftrace events for
tracking the register reads and writes. In this patch,
tate across CPU low power
states")
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
b/drivers/hwtracing/coresight/coresight-e
This 2 patch series provides fixes to ETF null pointer dereference crash
and TRCVMIDCCTLR1 register save and restore fix.
Patch 1 is an RFC since I am not sure of the fix provided since it looks
more like a band-aid than the actual fix.
Sai Prakash Ranjan (2):
coresight: tmc-etf: Fix NULL
finish_task_switch+0x184/0x1cc
schedule_tail+0x20/0xec
ret_from_fork+0x4/0x18
Signed-off-by: Sai Prakash Ranjan
---
I am not sure of this incomplete solution hence the RFC. This issue was also
reported when this code was first added [1] but somehow it didn't get much
notice at the time. So
Hi Will,
On 2020-09-21 23:33, Will Deacon wrote:
On Fri, Sep 11, 2020 at 07:57:18PM +0530, Sai Prakash Ranjan wrote:
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
I wonder if the panfrost folks can reuse
.
Signed-off-by: Sharat Masetty
[saiprakash.ranjan: fix to set attr before device attach to iommu and rebase]
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++
drivers/gpu/drm/msm/adreno
Prakash Ranjan
---
drivers/gpu/drm/msm/msm_drv.c | 8
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 49685571dc0e..a1e22b974b77
Fix the checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
b/drivers/iommu/arm/arm
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12
1 file changed, 8 insertions(+), 4 deletions
Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +
drivers/iommu
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 7 ++-
include/linux/io-pgtable.h | 4
2 files changed, 10 insertions(+), 1
pagetables series
Sai Prakash Ranjan (4):
iommu/io-pgtable-arm: Add support to use system cache
iommu/arm-smmu: Add domain attribute for system cache
iommu: arm-smmu-impl: Use table to list QCOM implementations
iommu: arm-smmu-impl: Add a space before open parenthesis
Sharat Masetty (2):
drm/msm
On 2020-09-11 22:20, Sai Prakash Ranjan wrote:
On 2020-09-11 22:04, Robin Murphy wrote:
On 2020-09-11 17:21, Sai Prakash Ranjan wrote:
On 2020-09-11 21:37, Will Deacon wrote:
On Fri, Sep 11, 2020 at 05:03:06PM +0100, Robin Murphy wrote:
BTW am I supposed to have received 3 copies
Cleanup qcom_llcc_cfg_program() by moving llcc configuration
to a separate function of its own. Also correct misspelled
'instance' caught by checkpatch.
Suggested-by: Stephen Boyd
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/llcc-qcom.c | 89
1
:
* Fix build errors reported by kernel test robot.
Isaac J. Manjarres (1):
soc: qcom: llcc: Support chipsets that can write to llcc
Sai Prakash Ranjan (1):
soc: qcom: llcc: Move llcc configuration to its own function
drivers/soc/qcom/llcc-qcom.c | 115 +++
1
xact power numbers are not known at
the moment.
Signed-off-by: Isaac J. Manjarres
Reviewed-by: Douglas Anderson
[saiprakash.ran...@codeaurora.org: use existing config and reword commit msg]
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/llcc-qcom.c | 32
1 fi
On 2020-09-15 00:14, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2020-09-14 04:12:59)
Cleanup qcom_llcc_cfg_program() by moving llcc attribute
configuration to a separate function of its own. Also
correct misspelled 'instance' caught by checkpatch.
Suggested-by: Stephen Boyd
Signed-off
On 2020-09-15 00:16, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2020-09-14 04:13:00)
From: "Isaac J. Manjarres"
Older chipsets may not be allowed to configure certain LLCC registers
as that is handled by the secure side software. However, this is not
the case for newe
Cleanup qcom_llcc_cfg_program() by moving llcc attribute
configuration to a separate function of its own. Also
correct misspelled 'instance' caught by checkpatch.
Suggested-by: Stephen Boyd
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/llcc-qcom.c | 75
xact power numbers are not known at
the moment.
Signed-off-by: Isaac J. Manjarres
Reviewed-by: Douglas Anderson
(saiprakash.ran...@codeaurora.org: use existing config and reword commit msg)
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/llcc-qcom.c | 27 +--
1 file c
: Support chipsets that can write to llcc
Sai Prakash Ranjan (1):
soc: qcom: llcc: Move attribute config to its own function
drivers/soc/qcom/llcc-qcom.c | 100 +++
1 file changed, 65 insertions(+), 35 deletions(-)
base-commit
On 2020-09-11 22:04, Robin Murphy wrote:
On 2020-09-11 17:21, Sai Prakash Ranjan wrote:
On 2020-09-11 21:37, Will Deacon wrote:
On Fri, Sep 11, 2020 at 05:03:06PM +0100, Robin Murphy wrote:
BTW am I supposed to have received 3 copies of everything? Because I
did...
Yeah, this seems
There are few places in arm-smmu-impl where there are
extra blank lines, remove them and while at it fix the
checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 5 +
1 file changed, 1 insertion
On 2020-09-11 21:37, Will Deacon wrote:
On Fri, Sep 11, 2020 at 05:03:06PM +0100, Robin Murphy wrote:
BTW am I supposed to have received 3 copies of everything? Because I
did...
Yeah, this seems to be happening for all of Sai's emails :/
Sorry, I am not sure what went wrong as I only sent
Prakash Ranjan
---
drivers/gpu/drm/msm/msm_drv.c | 8
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index abf5799d9a22..03caafa7c7b2
On 2020-09-11 21:33, Robin Murphy wrote:
On 2020-09-11 15:28, Sai Prakash Ranjan wrote:
There are few places in arm-smmu-impl where there are
extra blank lines, remove them
FWIW those were deliberate - sometimes I like a bit of subtle space to
visually delineate distinct groups of definitions
.
Signed-off-by: Sharat Masetty
(saiprakash.ranjan: fix to set attr before device attach to iommu and rebase)
Signed-off-by: Sai Prakash Ranjan
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++
drivers/gpu/drm/msm/adreno
Use table and of_match_node() to match qcom implementation
instead of multiple of_device_compatible() calls for each
QCOM SMMU implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12
1 file changed, 8 insertions(+), 4 deletions
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 7 ++-
include/linux/io-pgtable.h | 4
2 files changed, 10 insertions(+), 1
Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 17 +
drivers/iommu
latest split pagetables and per-instance
pagetables support
Changes in v2:
* Addressed review comments and rebased on top of Jordan's split
pagetables series
Sai Prakash Ranjan (4):
iommu/io-pgtable-arm: Add support to use system cache
iommu/arm-smmu: Add domain attribute for system cache
-by: Bjorn Andersson
---
Reviewed-by: Sai Prakash Ranjan
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
Prakash Ranjan
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
On 2020-09-04 21:25, Bjorn Andersson wrote:
Add a new operation to allow platform implementations to inherit any
stream mappings from the boot loader.
Signed-off-by: Bjorn Andersson
---
Reviewed-by: Sai Prakash Ranjan
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm
to result in indeterministic results, as these
mappings might linger and reference context banks that Linux is
reconfiguring.
Use the fact that BYPASS writes result in FAULT type to force all
stream
mappings to FAULT.
Signed-off-by: Bjorn Andersson
---
Reviewed-by: Sai Prakash Ranjan
Tested-by: S
_s2cr);
+ if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS)
+ qsmmu->bypass_broken = true;
+
Clever :)
Reviewed-by: Sai Prakash Ranjan
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
On 2020-09-04 21:25, Bjorn Andersson wrote:
For implementations of the ARM SMMU where stream mappings of bypass
type
are prohibited identity domains can be implemented by using context
banks with translation disabled.
Postpone the decision to skip allocating a context bank until the
the
implementation specific context bank allocator has been consulted and
if
it decides to use a context bank for the identity map, don't enable
translation (i.e. omit ARM_SMMU_SCTLR_M).
Signed-off-by: Bjorn Andersson
---
Minor nit in the subject: identify -> identity
Reviewed-by: Sai Prakash Ran
executed, in a later patch.
Signed-off-by: Bjorn Andersson
---
Reviewed-by: Sai Prakash Ranjan
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
parameter, as this can be read from the
newly passed object.
This allows us to not assign smmu_domain->smmu before attempting to
allocate the context bank and as such we don't need to roll back this
assignment on failure.
Signed-off-by: Bjorn Andersson
---
Reviewed-by: Sai Prakash Ranjan
Tes
Hi Bjorn,
On 2020-09-04 21:25, Bjorn Andersson wrote:
Based on previous attempts and discussions this is the latest attempt
at
inheriting stream mappings set up by the bootloader, for e.g. boot
splash or
efifb.
Per Will's request this builds on the work by Jordan and Rob for the
Adreno
SMMU
On 2020-09-09 12:38, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2020-09-09 00:04:00)
Hi,
On 2020-09-09 00:02, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2020-09-07 22:36:48)
>> From: "Isaac J. Manjarres"
>>
>> Older chipsets may not be allowed to c
Hi,
On 2020-09-08 20:30, Doug Anderson wrote:
Hi,
On Mon, Sep 7, 2020 at 10:36 PM Sai Prakash Ranjan
wrote:
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -73,6 +73,7 @@ struct llcc_edac_reg_data {
* @bitmap: Bit map to track the active slice ids
Hi,
On 2020-09-09 00:02, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2020-09-07 22:36:48)
From: "Isaac J. Manjarres"
Older chipsets may not be allowed to configure certain LLCC registers
as that is handled by the secure side software. However, this is not
the case for newe
xact power numbers are not known at
the moment.
Signed-off-by: Isaac J. Manjarres
(sai: use existing config instead of dt property and commit msg change)
Signed-off-by: Sai Prakash Ranjan
---
Changes in v3:
* Drop separate table and use existing qcom_llcc_config (Doug)
* More descriptive commit
On 2020-09-03 23:08, Doug Anderson wrote:
Hi,
On Thu, Sep 3, 2020 at 9:04 AM Sai Prakash Ranjan
wrote:
Hi,
On 2020-09-03 21:24, Doug Anderson wrote:
> Hi,
>
> On Thu, Sep 3, 2020 at 8:47 AM Sai Prakash Ranjan
> wrote:
>>
>> On 2020-09-03 19:16, Doug
Hi,
On 2020-09-03 21:24, Doug Anderson wrote:
Hi,
On Thu, Sep 3, 2020 at 8:47 AM Sai Prakash Ranjan
wrote:
On 2020-09-03 19:16, Doug Anderson wrote:
> Hi,
>
> On Thu, Sep 3, 2020 at 2:58 AM Sai Prakash Ranjan
> wrote:
>>
>> Hi,
>>
>> On 2020-08-18 21:0
On 2020-09-03 19:16, Doug Anderson wrote:
Hi,
On Thu, Sep 3, 2020 at 2:58 AM Sai Prakash Ranjan
wrote:
Hi,
On 2020-08-18 21:07, Sai Prakash Ranjan wrote:
> Hi Doug,
>
>>
>> I guess to start, it wasn't obvious (to me) that there were two
>> choices and we were
Hi,
On 2020-08-18 21:07, Sai Prakash Ranjan wrote:
Hi Doug,
I guess to start, it wasn't obvious (to me) that there were two
choices and we were picking one. Mentioning that the other
alternative was way-based allocation would help a lot. Even if you
can't fully explain the differences
wrote the code with
some guidance :) . I talked to Steve as well in the past about the
basic of idea of this. Steve is on vacation this week though.
This is similar to what +Sai Prakash Ranjan was trying to do sometime
ago: https://lkml.org/lkml/2018/9/8/221 . But that approach involved
higher overhead
+0x
Cc: Abhinav Kumar
Cc: Jeykumar Sankaran
Cc: Jordan Crouse
Cc: Sean Paul
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Stephen Boyd
---
Tested-by: Sai Prakash Ranjan
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of Code
On 2020-08-26 19:21, Robin Murphy wrote:
On 2020-08-26 13:17, Sai Prakash Ranjan wrote:
On 2020-08-26 17:07, Robin Murphy wrote:
On 2020-08-25 16:42, Sai Prakash Ranjan wrote:
Currently the non-strict or lazy mode of TLB invalidation can only
be set
for all or no domains. This works well
On 2020-08-26 17:07, Robin Murphy wrote:
On 2020-08-25 16:42, Sai Prakash Ranjan wrote:
Currently the non-strict or lazy mode of TLB invalidation can only be
set
for all or no domains. This works well for development platforms where
setting to non-strict/lazy mode is fine for performance
Hi,
On 2020-08-26 03:45, Doug Anderson wrote:
Hi,
On Tue, Aug 25, 2020 at 12:01 PM Sai Prakash Ranjan
wrote:
Hi,
On 2020-08-25 21:40, Doug Anderson wrote:
> Hi,
>
> On Tue, Aug 25, 2020 at 8:43 AM Sai Prakash Ranjan
> wrote:
>>
>> Currently the non-strict or lazy
Hi,
On 2020-08-25 21:40, Doug Anderson wrote:
Hi,
On Tue, Aug 25, 2020 at 8:43 AM Sai Prakash Ranjan
wrote:
Currently the non-strict or lazy mode of TLB invalidation can only be
set
for all or no domains. This works well for development platforms where
setting to non-strict/lazy mode
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/iommu.c | 37 +
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index 609bd25bf154..fd10a073f557 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/io
Cc: Russell King
Signed-off-by: Kim Phillips
Signed-off-by: Tingwei Zhang
Tested-by: Mike Leach
Suggested-by: Suzuki K Poulose
---
Tested-by: Sai Prakash Ranjan
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of Code Aurora Forum, hosted by The Linux Foundation
-by: kernel test robot
Tested-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
Tested-by: Sai Prakash Ranjan
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
-by: Kim Phillips
Signed-off-by: Tingwei Zhang
Tested-by: Mike Leach
---
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
Reviewed-by: Suzuki K Poulose
Reviewed-by: Mathieu Poirier
---
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
Phillips
Signed-off-by: Tingwei Zhang
Tested-by: Mike Leach
Reviewed-by: Suzuki K Poulose
Reviewed-by: Mathieu Poirier
---
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
module as these are not exported
symbols.
This reverts commit efde2659b0fe835732047357b2902cca14f054d9.
Cc: Sai Prakash Ranjan
Cc: John Stultz
Cc: Stephen Rothwell
Signed-off-by: Maulik Shah
---
Reviewed-by: Sai Prakash Ranjan
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation
Hi Doug,
On 2020-08-18 20:42, Doug Anderson wrote:
Hi,
...
I guess to start, it wasn't obvious (to me) that there were two
choices and we were picking one. Mentioning that the other
alternative was way-based allocation would help a lot. Even if you
can't fully explain the differences
On 2020-08-18 20:42, Rob Clark wrote:
On Tue, Aug 18, 2020 at 3:03 AM Sai Prakash Ranjan
wrote:
Hi,
On 2020-06-01 16:33, Krishna Manikandan wrote:
> Define shutdown callback for display drm driver,
> so as to disable all the CRTCS when shutdown
> notification is received by t
s: qcom: sc7180: Add Last level cache controller
node")
Signed-off-by: Sai Prakash Ranjan
---
Changes in v2:
* Edit commit msg to remove confusing references (Doug).
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/
translations are getting disabled
during reboot sequence.
Signed-off-by: Krishna Manikandan
Changes in v2:
- Remove NULL check from msm_pdev_shutdown (Stephen Boyd)
- Change commit text to reflect when this issue
was uncovered (Sai Prakash Ranjan)
---
drivers/gpu/drm/msm
Hi,
On 2020-08-18 02:35, Doug Anderson wrote:
Hi,
On Mon, Aug 17, 2020 at 7:47 AM Sai Prakash Ranjan
wrote:
From: "Isaac J. Manjarres"
Older chipsets may not be allowed to configure certain LLCC registers
as that is handled by the secure side software. However, this is no
Hi,
On 2020-08-18 02:42, Doug Anderson wrote:
Hi,
On Sun, Aug 16, 2020 at 9:04 PM Sai Prakash Ranjan
wrote:
There is only one LLCC logical bank on SC7180 SoC of size
0x5(320KB) not 2MB, so correct the size and fix copy
paste mistake from SDM845 which had 4 logical banks.
I guess
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