commit msg change)
Signed-off-by: Sai Prakash Ranjan
---
Changes in v2:
* Fix build errors reported by kernel test robot.
---
drivers/soc/qcom/llcc-qcom.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qc
to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Sai-Prakash-Ranjan/soc-qcom-llcc-Support-chipsets-that-can-write-to-llcc-registers/20200817-161342
commit msg change)
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/llcc-qcom.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 429b5a60a1ba..20619d15ecba 100644
--- a/drivers/soc/qcom/llcc-qc
Add Last level cache controller
node")
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index d46b3833e52f..e875f6c3b6
On 2020-08-14 13:47, Marc Zyngier wrote:
On 2020-08-14 05:34, Sai Prakash Ranjan wrote:
On 2020-08-13 23:29, Marc Zyngier wrote:
[...]
We'd need to disable the late onlining of CPUs that would change
the mitigation state, and this is... ugly.
Ugh, yes indeed and here I was thinking
machine(struct device *dev, unsigned int
id)
From the chipinfo document that I have at hand, this is correct soc id
for SC7180, so
Reviewed-by: Sai Prakash Ranjan
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
On 2020-08-13 23:29, Marc Zyngier wrote:
On 2020-08-13 13:33, Sai Prakash Ranjan wrote:
On 2020-08-13 16:09, Marc Zyngier wrote:
On 2020-08-13 10:40, Will Deacon wrote:
On Thu, Aug 13, 2020 at 02:49:37PM +0530, Sai Prakash Ranjan wrote:
On 2020-08-13 14:33, Will Deacon wrote:
> On Thu,
On 2020-08-13 16:09, Marc Zyngier wrote:
On 2020-08-13 10:40, Will Deacon wrote:
On Thu, Aug 13, 2020 at 02:49:37PM +0530, Sai Prakash Ranjan wrote:
On 2020-08-13 14:33, Will Deacon wrote:
> On Thu, Aug 13, 2020 at 01:48:34PM +0530, Sai Prakash Ranjan wrote:
> > KRYO4XX gold/big
On 2020-08-13 14:33, Will Deacon wrote:
On Thu, Aug 13, 2020 at 01:48:34PM +0530, Sai Prakash Ranjan wrote:
KRYO4XX gold/big CPU cores are based on Cortex-A76 which has CSV2
bits set and are spectre-v2 safe. But on big.LITTLE systems where
they are coupled with other CPU cores
that CSV2 bits are not set for KRYO4XX gold cores.
Reported-by: Stephen Boyd
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/kernel/cpu_errata.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 6bd1d3ad037a..6cbdd2d98a2a 100644
as they
are currently no-op anyways and the scaling support that may
be added in future will use interconnect apis.
Signed-off-by: Sai Prakash Ranjan
---
drivers/scsi/ufs/ufs-qcom.c | 225 +---
drivers/scsi/ufs/ufs-qcom.h | 11 --
2 files changed, 1 insertion(+), 235
MSM bus scaling has moved on to use interconnect framework
and downstream bus scaling apis are not present anymore.
Remove them as they are nop anyways in the current code,
no functional change.
Signed-off-by: Sai Prakash Ranjan
---
.../gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c | 24
MSM bus scaling has moved on to use interconnect framework
and downstream bus scaling apis are not present anymore.
Remove them as they are nop anyways in the current code,
no functional change.
Signed-off-by: Sai Prakash Ranjan
---
.../gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c | 51
MSM bus scaling has moved on to use interconnect framework
and downstream bus scaling apis are not present anymore.
Remove them as they are nop anyways in the current code,
no functional change.
Sai Prakash Ranjan (2):
drm/msm/mdp4: Remove unused downstream bus scaling apis
drm/msm/mdp5
Hi Qi Liu,
On 2020-08-03 19:05, Qi Liu wrote:
Add ETMv4 periperhal ID for HiSilicon Hip08 and Hip09 platform. Hip08
contains ETMv4.2 device and Hip09 contains ETMv4.5 device.
Signed-off-by: Qi Liu
---
drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++
1 file changed, 2 insertions(+)
diff
tate
machine")
Suggested-by: Suzuki K Poulose
Signed-off-by: Sai Prakash Ranjan
---
Changes in v3:
* Minor cleanups from v2 and change to device_initcall (Stephen Boyd)
* Move to non cpuslocked cpuhp callbacks and rename to etm_pm_setup() (Mike
Leach)
Changes in v2:
* Rearrange cpuhp callback
Hi Mike,
On 2020-07-29 01:46, Mike Leach wrote:
Hi Sai,
On Tue, 28 Jul 2020 at 08:51, Sai Prakash Ranjan
wrote:
etm4_count keeps track of number of ETMv4 registered and on some
systems,
a race is observed on etm4_count variable which can lead to multiple
calls
On 2020-07-28 13:59, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2020-07-28 00:51:02)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b/drivers/hwtracing/coresight/coresight-etm4x.c
index 6d7d2169bfb2..adb71987a1e3 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b
ely remove etm4_count usage.
Fixes: 9b6a3f3633a5 ("coresight: etmv4: Fix CPU power management setup in
probe() function")
Fixes: 58eb457be028 ("hwtracing/coresight-etm4x: Convert to hotplug state
machine")
Suggested-by: Suzuki K Poulose
Signed-off-by: Sai Prakash Ranjan
--
On 2020-07-28 11:58, Bjorn Andersson wrote:
On Mon 27 Jul 21:40 PDT 2020, Sai Prakash Ranjan wrote:
On 2020-07-28 02:28, Bjorn Andersson wrote:
> On Tue 23 Jun 23:56 PDT 2020, Sai Prakash Ranjan wrote:
>
> > Hi Bjorn,
> >
> > On 2020-06-21 13:39, Sai Prakash Ranj
On 2020-07-28 02:28, Bjorn Andersson wrote:
On Tue 23 Jun 23:56 PDT 2020, Sai Prakash Ranjan wrote:
Hi Bjorn,
On 2020-06-21 13:39, Sai Prakash Ranjan wrote:
> Hi Bjorn,
>
> On 2020-06-21 12:52, Bjorn Andersson wrote:
> > On Tue 09 Jun 06:30 PDT 2020, Sai Prakash Ranjan wrote:
&
On 2020-07-27 15:09, Suzuki K Poulose wrote:
On 07/27/2020 07:07 AM, Sai Prakash Ranjan wrote:
etm4_count keeps track of number of ETMv4 registered and on some
systems, a race is observed on etm4_count variable which can
lead to multiple calls to cpuhp_setup_state_nocalls_cpuslocked
On 2020-07-27 11:37, Sai Prakash Ranjan wrote:
etm4_count keeps track of number of ETMv4 registered and on some
systems, a race is observed on etm4_count variable which can
lead to multiple calls to cpuhp_setup_state_nocalls_cpuslocked().
This function internally calls cpuhp_store_callbacks
tate
machine")
Suggested-by: Mike Leach
(Mike: Rootcause and context for commit message)
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresigh
Add "arm,coresight-loses-context-with-cpu" property to coresight
ETM nodes to avoid failure of trace session because of losing
context on entering deep idle states.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8
1 file changed, 8 insertion
_abort_xfer(gi2c);
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
that dev_pm_opp_put_clkname()
is called only when an opp_table exists.
Fixes: f99131fa7a23 ("drm/msm: dsi: Use OPP API to set clk/perf state")
Reported-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
has_opp_table)
dev_pm_opp_of_remove_table(dev);
- dev_pm_opp_put_clkname(dpu_kms->opp_table);
+ if (dpu_kms->opp_table)
+ dev_pm_opp_put_clkname(dpu_kms->opp_table);
}
static const struct component_ops dpu_ops = {
Tested-by: Sai Prakash Ranj
for return values to fix the issue.
We were hitting this issue when one of QUP is disabled.
Fixes: 048eb908a1f2 ("soc: qcom-geni-se: Add interconnect support to
fix earlycon crash")
Reported-by: Sai Prakash Ranjan
Reviewed-by: Matthias Kaehlcke
Signed-off-by: Akash Asthana
Nit: my
On 2020-07-14 00:43, Jordan Crouse wrote:
On Mon, Jul 13, 2020 at 08:03:32PM +0100, Will Deacon wrote:
On Mon, Jul 13, 2020 at 11:00:32AM -0600, Jordan Crouse wrote:
> On Mon, Jul 13, 2020 at 04:11:23PM +0100, Will Deacon wrote:
> > On Thu, Jun 11, 2020 at 04:36:56PM -0600, Jordan Crouse wrote:
Gold (rcpe to rfpf) => (r0p0 to r3p1) */
MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
+ {},
};
#endif
My bad missing this, thanks for the fix.
Reviewed-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code
On 2020-07-03 21:34, Rob Clark wrote:
On Fri, Jul 3, 2020 at 7:53 AM Sai Prakash Ranjan
wrote:
Hi Will,
On 2020-07-03 19:07, Will Deacon wrote:
> On Mon, Jun 29, 2020 at 09:22:50PM +0530, Sai Prakash Ranjan wrote:
>> diff --git a/drivers/gpu/drm/msm/msm_iommu.c
>> b/driv
On 2020-07-03 21:55, Will Deacon wrote:
The IOMMU_SYS_CACHE_ONLY flag was never exposed via the DMA API and
has no in-tree users. Remove it.
Cc: Robin Murphy
Cc: "Isaac J. Manjarres"
Cc: Joerg Roedel
Cc: Christoph Hellwig
Cc: Sai Prakash Ranjan
Cc: Rob Clark
Signed-off-by: W
Hi Will,
On 2020-07-03 19:07, Will Deacon wrote:
On Mon, Jun 29, 2020 at 09:22:50PM +0530, Sai Prakash Ranjan wrote:
diff --git a/drivers/gpu/drm/msm/msm_iommu.c
b/drivers/gpu/drm/msm/msm_iommu.c
index f455c597f76d..bd1d58229cc2 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu
Hi Will,
On 2020-07-03 19:25, Will Deacon wrote:
On Tue, Jun 30, 2020 at 11:30:55PM +0530, Sai Prakash Ranjan wrote:
KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
erratum 1530923 and 1024718, so add them to the respective list.
The variant and revision bits
Hi Will, Robin,
On 2020-06-27 01:30, Jordan Crouse wrote:
Another iteration of the split-pagetable support for arm-smmu and the
Adreno GPU
SMMU. After email discussions [1] we opted to make a arm-smmu
implementation for
specifically for the Adreno GPU and use that to enable split pagetable
1463225 and 1418040.
Patch 3 adds Kryo4xx silver CPU cores to erratum list 1530923 and 1024718.
Sai Prakash Ranjan (3):
arm64: Add MIDR value for KRYO4XX gold CPU cores
arm64: Add KRYO4XX gold CPU cores to erratum list 1463225 and 1418040
arm64: Add KRYO4XX silver CPU cores to erratum list
) is equivalent to (rcpe to rfpf).
Signed-off-by: Sai Prakash Ranjan
---
Documentation/arm64/silicon-errata.rst | 4
arch/arm64/kernel/cpu_errata.c | 19 +--
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.rst
b
to rdpe.
Signed-off-by: Sai Prakash Ranjan
---
Documentation/arm64/silicon-errata.rst | 4
arch/arm64/kernel/cpu_errata.c | 2 ++
arch/arm64/kernel/cpufeature.c | 2 ++
3 files changed, 8 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.rst
b/Documentation
Add MIDR value for KRYO4XX gold/big CPU cores which are
used in Qualcomm Technologies, Inc. SoCs. This will be
used to identify and apply erratum which are applicable
for these CPU cores.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions
erty")
Cc: sta...@vger.kernel.org
Reported-by: Sai Prakash Ranjan
Signed-off-by: Sibi Sankar
---
arch/arm64/boot/dts/qcom/sc7180-idp.dts| 2 +-
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.d
There are few places in arm-smmu-impl where there are
extra blank lines, remove them and while at it fix the
checkpatch warning for space required before the open
parenthesis.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu-impl.c | 6 +-
1 file changed, 1 insertion(+), 5
series
[1] https://lore.kernel.org/patchwork/cover/1264446/
[2] https://lore.kernel.org/patchwork/cover/1264460/
Jordan Crouse (1):
iommu/arm-smmu: Add a init_context_bank implementation hook
Sai Prakash Ranjan (4):
iommu/io-pgtable-arm: Add support to use system cache
iommu/arm-smmu: Add
Use of_match_node() to match qcom implementation instead
of multiple of_device_compatible() calls for each qcom
implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu-impl.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu
it.
Similarly DOMAIN_ATTR_SYS_CACHE is another domain level attribute
used by the IOMMU driver to set the right attributes to cache the
hardware pagetables into the system cache.
Signed-off-by: Sharat Masetty
(sai: fix to set attr before device attach to IOMMU and rebase)
Signed-off-by: Sai Prakash
transactions. Doing so could hang the GPU if one of the terminated
transactions is a CP read.
This depends on the arm-smmu adreno SMMU implementation [1].
[1] https://lore.kernel.org/patchwork/patch/1264452/
Signed-off-by: Jordan Crouse
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu
Add iommu domain attribute for using system cache aka last level
cache by client drivers like GPU to set right attributes for caching
the hardware pagetables into the system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu.c | 17 +
drivers/iommu/arm-smmu.h
Prakash Ranjan
---
drivers/gpu/drm/msm/msm_drv.c | 8
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 0c219b954943..5aa070929220
Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
attributes set in TCR for the page table walker when
using system cache.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/io-pgtable-arm.c | 7 ++-
include/linux/io-pgtable.h | 4
2 files changed, 10 insertions(+), 1
On 2020-06-26 02:48, Guenter Roeck wrote:
On Fri, Jun 26, 2020 at 12:52:31AM +0530, Sai Prakash Ranjan wrote:
> >
> I don't think the watchdog mailing list has been copied on this series,
> meaning I don't have a copy that I could apply if I wanted to.
I kept you in CC for all t
Convert QCOM watchdog timer bindings to DT schema format using
json-schema.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Stephen Boyd
Reviewed-by: Rob Herring
---
.../devicetree/bindings/watchdog/qcom-wdt.txt | 28
.../bindings/watchdog/qcom-wdt.yaml | 44
Add missing compatible for watchdog timer on QCS404,
SC7180, SDM845 and SM8150 SoCs.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Stephen Boyd
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 4
1 file changed, 4 insertions(+)
diff --git
use of const:qcom,kpss-wdt and made use of enum.
Sai Prakash Ranjan (2):
dt-bindings: watchdog: Convert QCOM watchdog timer bindings to YAML
dt-bindings: watchdog: Add compatible for QCS404, SC7180, SDM845,
SM8150
.../devicetree/bindings/watchdog/qcom-wdt.txt | 28 ---
.../bindings
On 2020-06-25 21:30, Guenter Roeck wrote:
On Mon, Jun 22, 2020 at 11:50:52AM +0530, Sai Prakash Ranjan wrote:
On 2020-06-21 13:03, Bjorn Andersson wrote:
> On Tue 16 Jun 23:56 PDT 2020, Sai Prakash Ranjan wrote:
>
> > Hi Bjorn,
> >
>
> Hi Sai,
>
> > On 2020-02-1
QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on
Cortex-A55 and are SSB safe, hence add them to SSB
safelist -> arm64_ssb_cpus[].
Reported-by: Stephen Boyd
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/kernel/cpu_errata.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/ar
QCOM KRYO{3,4}XX silver/LITTLE CPU cores are based on Cortex-A55
and are meltdown safe, hence add them to kpti_safe_list[].
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/kernel/cpufeature.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64
Hi Bjorn,
On 2020-06-21 13:39, Sai Prakash Ranjan wrote:
Hi Bjorn,
On 2020-06-21 12:52, Bjorn Andersson wrote:
On Tue 09 Jun 06:30 PDT 2020, Sai Prakash Ranjan wrote:
Define iommus property for Coresight ETR component in
SC7180 SoC with the SID and mask to enable SMMU
translation
On 2020-06-23 22:55, Mathieu Poirier wrote:
On Tue, Jun 16, 2020 at 10:26:23AM +0530, Sai Prakash Ranjan wrote:
Implement a shutdown callback to ensure ETR hardware is
properly shutdown in reboot/shutdown path. This is required
for ETR which has SMMU address translation enabled like on
SC7180
Hi Mansur,
On 2020-06-13 16:03, Mansur Alisha Shaik wrote:
After the SMMU translation is disabled in the
arm-smmu shutdown callback during reboot, if
any subsystem are still alive then IOVAs they
are using will become PAs on bus, which may
lead to crash.
Below are the consumers of smmu from
On 2020-06-21 13:03, Bjorn Andersson wrote:
On Tue 16 Jun 23:56 PDT 2020, Sai Prakash Ranjan wrote:
Hi Bjorn,
Hi Sai,
On 2020-02-12 03:54, Sai Prakash Ranjan wrote:
> This series converts QCOM watchdog timer bindings to YAML. Also
> it adds the missing SoC-specific compatible for
Hi Bjorn,
On 2020-06-21 12:52, Bjorn Andersson wrote:
On Tue 09 Jun 06:30 PDT 2020, Sai Prakash Ranjan wrote:
Define iommus property for Coresight ETR component in
SC7180 SoC with the SID and mask to enable SMMU
translation for this master.
We don't have _smmu in linux-next, as we've yet
Hi Bjorn,
On 2020-02-12 03:54, Sai Prakash Ranjan wrote:
This series converts QCOM watchdog timer bindings to YAML. Also
it adds the missing SoC-specific compatible for QCS404, SC7180,
SDM845 and SM8150 SoCs.
v1:
https://lore.kernel.org/lkml/cover.1576211720.git.saiprakash.ran
translation
is disabled and device_link in SMMU driver will take care of
ordering of shutdown callbacks such that SMMU shutdown callback
is not called before any of its consumer shutdown callbacks.
Signed-off-by: Sai Prakash Ranjan
---
Changes since v2:
* Remove ETF/ETB disable as suggested by Mathieu
x2 :
x1 : 0004 x0 : 0001
Kernel panic - not syncing: Asynchronous SError Interrupt
Fixes: 4525412a5046 ("coresight: tmc: making prepare/unprepare functions
generic")
Reported-by: Mike Leach
Signed-off-by: Sai Prakash Ranjan
---
drivers
Hi Mathieu,
On 2020-06-09 20:57, Mathieu Poirier wrote:
On Mon, 8 Jun 2020 at 08:07, Sai Prakash Ranjan
wrote:
Hi Mathieu, Mike
On 2020-06-04 12:57, Sai Prakash Ranjan wrote:
>
[...]
>>
>> Robin has a point - user space is long gone at this time. As such the
>> fir
Hi Bjorn,
On 2020-05-15 16:21, Sai Prakash Ranjan wrote:
Add "qcom,skip-power-up" property to skip powering up ETM
on SC7180 SoC to workaround a hardware errata where CPU
watchdog counter is stopped when ETM power up bit is set
(i.e., when TRCPDCR.PU = 1).
Signed-off-by: Sai Prak
Add "qcom,skip-power-up" property to skip powering up ETM
on SC7180 SoC to workaround a hardware errata where CPU
watchdog counter is stopped when ETM power up bit is set
(i.e., when TRCPDCR.PU = 1).
Signed-off-by: Sai Prakash Ranjan
---
Depends on ETM driver change here:
Add "qcom,replicator-loses-context" property to the replicator
in Always-on domain in SC7180 SoC to enable coresight replicator
driver to handle this variation of replicator designs.
Signed-off-by: Sai Prakash Ranjan
---
Depends on coresight replicator change here:
-
https://git.
Add coresight components found on Qualcomm SM8150 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Depends on following coresight driver and SM8150 SMMU support:
-
https://git.linaro.org/kernel/coresight.git/commit/?h=next-v5.8-rc1=159e248e75b1b548276b6571d7740a35cab1f5be
-
https://git.linaro.org
Define iommus property for Coresight ETR component in
SC7180 SoC with the SID and mask to enable SMMU
translation for this master.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
=159e248e75b1b548276b6571d7740a35cab1f5be
-
https://git.linaro.org/kernel/coresight.git/commit/?h=next-v5.8-rc1=1b6cddfb7ebb5ed293124698f147e914b15315a1
- https://lore.kernel.org/lkml/20200524023815.21789-2-jonat...@marek.ca/
Tested this series on SM8150 and SC7180.
Sai Prakash Ranjan (4):
arm64: dts: qcom
Hi Mathieu, Mike
On 2020-06-04 12:57, Sai Prakash Ranjan wrote:
[...]
Robin has a point - user space is long gone at this time. As such the
first
question to ask is what kind of CS session was running at the time the
system
was shutting down. Was it a perf session of a sysfs session
Hi Will,
On 2020-06-08 17:08, Will Deacon wrote:
On Mon, Jun 08, 2020 at 02:43:03PM +0530, Sai Prakash Ranjan wrote:
On 2020-06-08 13:48, Will Deacon wrote:
> On Sun, Jun 07, 2020 at 04:39:18PM +0530, Sai Prakash Ranjan wrote:
> > Remove SMMU shutdown callback since it seems to c
Hi Robin,
On 2020-06-08 16:56, Robin Murphy wrote:
On 2020-06-08 10:13, Sai Prakash Ranjan wrote:
Hi Will,
On 2020-06-08 13:48, Will Deacon wrote:
On Sun, Jun 07, 2020 at 04:39:18PM +0530, Sai Prakash Ranjan wrote:
Remove SMMU shutdown callback since it seems to cause more
problems than
Hi Will,
On 2020-06-08 13:48, Will Deacon wrote:
On Sun, Jun 07, 2020 at 04:39:18PM +0530, Sai Prakash Ranjan wrote:
Remove SMMU shutdown callback since it seems to cause more
problems than benefits. With this callback, we need to make
sure that all clients/consumers of SMMU do not perform any
, we need to identify the client of SMMU causing
the memory corruption and add appropriate shutdown callback
to the client rather than to the SMMU.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu-v3.c | 6 --
drivers/iommu/arm-smmu.c| 6 --
2 files changed, 12 deletions
On 2020-06-05 20:21, Nicolas Dechesne wrote:
On Fri, Jun 5, 2020 at 4:39 PM Sai Prakash Ranjan
wrote:
Hi Nico,
On 2020-06-05 20:01, Nicolas Dechesne wrote:
> On Fri, Jun 5, 2020 at 4:14 PM Sai Prakash Ranjan
> wrote:
>>
>> On 2020-06-05 19:40, Jonathan Marek wrote:
>&
Hi Nico,
On 2020-06-05 20:01, Nicolas Dechesne wrote:
On Fri, Jun 5, 2020 at 4:14 PM Sai Prakash Ranjan
wrote:
On 2020-06-05 19:40, Jonathan Marek wrote:
> On 6/5/20 10:03 AM, Sai Prakash Ranjan wrote:
>> On 2020-05-29 08:45, Bjorn Andersson wrote:
>>> On Thu 28 May 20:02
On 2020-05-25 15:07, Sai Prakash Ranjan wrote:
Hi Jonathan,
On 2020-05-24 08:08, Jonathan Marek wrote:
Add the apps_smmu node for sm8150. Note that adding the iommus field
for
UFS is required because initializing the iommu removes the bypass
mapping
that created by the bootloader.
Signed
On 2020-06-05 19:40, Jonathan Marek wrote:
On 6/5/20 10:03 AM, Sai Prakash Ranjan wrote:
On 2020-05-29 08:45, Bjorn Andersson wrote:
On Thu 28 May 20:02 PDT 2020, Jonathan Marek wrote:
On 5/28/20 10:52 PM, Bjorn Andersson wrote:
> On Sat 23 May 19:38 PDT 2020, Jonathan Marek wr
On 2020-05-29 08:45, Bjorn Andersson wrote:
On Thu 28 May 20:02 PDT 2020, Jonathan Marek wrote:
On 5/28/20 10:52 PM, Bjorn Andersson wrote:
> On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
>
> > Add the apps_smmu node for sm8150. Note that adding the iommus field for
> > UFS is required
Hi Mathieu,
+Will
On 2020-06-03 23:14, Mathieu Poirier wrote:
On Wed, Jun 03, 2020 at 02:34:10PM +0100, Robin Murphy wrote:
On 2020-06-03 14:22, Mike Leach wrote:
> Hi Sai,
>
> On Wed, 3 Jun 2020 at 13:14, Sai Prakash Ranjan
> wrote:
> >
> > Hi Mike,
> >
>
Hi Bjorn,
On 2020-06-03 23:39, Bjorn Andersson wrote:
On Thu 28 May 23:56 PDT 2020, Sai Prakash Ranjan wrote:
Hi Bjorn,
On 2020-05-29 06:41, Bjorn Andersson wrote:
> On Mon 25 May 02:47 PDT 2020, Sai Prakash Ranjan wrote:
>
> > Hi Jonathan,
> >
> > On 2020-05-25 02:
Hi Mike,
On 2020-06-03 19:21, Mike Leach wrote:
Hi,
On Wed, 3 Jun 2020 at 14:34, Robin Murphy wrote:
On 2020-06-03 14:22, Mike Leach wrote:
> Hi Sai,
>
> On Wed, 3 Jun 2020 at 13:14, Sai Prakash Ranjan
> wrote:
>>
>> Hi Mike,
>>
>> On 2020-0
Hi Robin,
On 2020-06-03 19:10, Robin Murphy wrote:
On 2020-06-03 13:26, Sai Prakash Ranjan wrote:
Hi Robin,
On 2020-06-03 17:51, Robin Murphy wrote:
On 2020-06-03 13:00, Sai Prakash Ranjan wrote:
Hi Robin, Mathieu
On 2020-06-03 17:07, Robin Murphy wrote:
On 2020-06-01 22:28, Mathieu
Hi Mike,
On 2020-06-03 19:04, Robin Murphy wrote:
On 2020-06-03 14:22, Mike Leach wrote:
Hi Sai,
On Wed, 3 Jun 2020 at 13:14, Sai Prakash Ranjan
wrote:
Hi Mike,
On 2020-06-03 16:57, Mike Leach wrote:
Hi,
On Wed, 3 Jun 2020 at 11:24, Sai Prakash Ranjan
wrote:
Hi Mike,
Thanks again
Hi Robin,
On 2020-06-03 17:51, Robin Murphy wrote:
On 2020-06-03 13:00, Sai Prakash Ranjan wrote:
Hi Robin, Mathieu
On 2020-06-03 17:07, Robin Murphy wrote:
On 2020-06-01 22:28, Mathieu Poirier wrote:
That being said I'm sure that dependencies on an IOMMU isn't a
problem confined
Hi Mike,
On 2020-06-03 16:57, Mike Leach wrote:
Hi,
On Wed, 3 Jun 2020 at 11:24, Sai Prakash Ranjan
wrote:
Hi Mike,
Thanks again for looking at this.
On 2020-06-03 03:42, Mike Leach wrote:
[...]
>>
>> SMMU/IOMMU won't be able to do much here as it is the client's
>
Hi Robin, Mathieu
On 2020-06-03 17:07, Robin Murphy wrote:
On 2020-06-01 22:28, Mathieu Poirier wrote:
That being said I'm sure that dependencies on an IOMMU isn't a problem
confined
to coresight. I am adding Robin Murphy, who added this commit [1], to
the thread
in the hope that he can
Hi Mike,
Thanks again for looking at this.
On 2020-06-03 03:42, Mike Leach wrote:
[...]
SMMU/IOMMU won't be able to do much here as it is the client's
responsiblity to
properly shutdown and SMMU device link just makes sure that
SMMU(supplier) shutdown is
called only after its consumers
Hi Emil,
On 2020-06-02 21:09, Emil Velikov wrote:
On Tue, 2 Jun 2020 at 15:49, Sai Prakash Ranjan
wrote:
Hi Emil,
On 2020-06-02 19:43, Emil Velikov wrote:
> Hi Krishna,
>
> On Tue, 2 Jun 2020 at 08:17, Krishna Manikandan
> wrote:
>>
>> Define shutdown callback for d
Hi Emil,
On 2020-06-02 19:43, Emil Velikov wrote:
Hi Krishna,
On Tue, 2 Jun 2020 at 08:17, Krishna Manikandan
wrote:
Define shutdown callback for display drm driver,
so as to disable all the CRTCS when shutdown
notification is received by the driver.
This change will turn off the timing
Hi Mathieu,
Thanks for taking your time for review.
On 2020-06-02 02:58, Mathieu Poirier wrote:
Hi Sai,
On top of the comments already privided by Mike, I have the following:
On Mon, Jun 01, 2020 at 01:32:26PM +0530, Sai Prakash Ranjan wrote:
Implement a shutdown callback to ensure ETR/ETF
SMMU translation is
disabled and device_link in SMMU driver will take care of ordering
of shutdown callbacks such that SMMU shutdown callback is not
called before any of its consumer shutdown callbacks.
Signed-off-by: Sai Prakash Ranjan
---
Changes since v1:
* Use mode flag and drop enable flag
Hi Mike,
Thanks for the review.
On 2020-06-01 19:05, Mike Leach wrote:
Hi,
On Mon, 1 Jun 2020 at 09:02, Sai Prakash Ranjan
wrote:
Implement a shutdown callback to ensure ETR/ETF hardware is
properly shutdown in reboot/shutdown path. This is required
for ETR/ETF which has SMMU address
Hi Mike,
Thanks for the review.
On 2020-06-01 18:57, Mike Leach wrote:
Hi,
On Mon, 1 Jun 2020 at 09:02, Sai Prakash Ranjan
wrote:
Add a flag to check whether TMC ETR/ETF is enabled or not.
This is later used in shutdown callback to determine if
we require to disable ETR/ETF.
Signed-off
SMMU translation is
disabled and device_link in SMMU driver will take care of ordering
of shutdown callbacks such that SMMU shutdown callback is not
called before any of its consumer shutdown callbacks.
Signed-off-by: Sai Prakash Ranjan
---
.../hwtracing/coresight/coresight-tmc-etf.c | 4
is shutdown before
SMMU translation is disabled and device_link in SMMU driver will take
care of ordering of shutdown callbacks such that SMMU shutdown callback
is not called before any of its consumer shutdown callbacks.
Sai Prakash Ranjan (2):
coresight: tmc: Add enable flag to indicate the status
Add a flag to check whether TMC ETR/ETF is enabled or not.
This is later used in shutdown callback to determine if
we require to disable ETR/ETF.
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-tmc.c | 2 ++
drivers/hwtracing/coresight/coresight-tmc.h | 2 ++
2 files
Hi Bjorn,
On 2020-05-29 06:41, Bjorn Andersson wrote:
On Mon 25 May 02:47 PDT 2020, Sai Prakash Ranjan wrote:
Hi Jonathan,
On 2020-05-25 02:36, Jonathan Marek wrote:
> Add support for the graphics clock controller found on SM8250
> based devices. This would allow graphics drivers to
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