Hi Suzuki,
On 7/18/2019 1:58 PM, Suzuki K Poulose wrote:
Hi Sai,
etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x06048000 0x1000>;
+
+ clocks = < RPM_SMD_QDSS_CLK>, <
RPM_SMD_QDSS_A_CLK>;
+ clock-names =
Hi Mathieu,
On 7/17/2019 10:30 PM, Mathieu Poirier wrote:
On Fri, Jul 12, 2019 at 07:46:25PM +0530, Sai Prakash Ranjan wrote:
From: Vivek Gautam
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on MSM8998.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Acked-by: Suzuki K Poulose
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 ++
1 file changed
From: Vivek Gautam
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
Signed-off-by: Vivek Gautam
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Acked-By: Suzuki K Poulose
initialized
[5.501802] OF: graph: no port node found in /soc/debug@3b1
[5.512901] coresight-etm4x: probe of 3b1.debug failed with error -22
[5.513192] coresight-cpu-debug 3b1.debug: Coresight debug-CPU3
initialized
Signed-off-by: Sai Prakash Ranjan
---
.../hwtracing/coresight
Prakash Ranjan
Reviewed-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c
b/drivers/hwtracing/coresight/coresight-etm4x.c
index 7bcac8896fc1
* Addressed Mathieu's feedback about masking the minor version in
etm4_arch_supported() and added a comment for reason to bypass
the AMBA bus discovery method.
Sai Prakash Ranjan (4):
arm64: dts: qcom: sdm845: Add Coresight support
arm64: dts: qcom: msm8998: Add Coresight support
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Acked-by: Suzuki K Poulose
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++
1 file changed, 451 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom
and cpu-debug to abort earlier
in case of unavailability of respective cpus.
Sai Prakash Ranjan (2):
dt-bindings: coresight: Change CPU phandle to required property
coresight: Do not default to CPU0 for missing CPU phandle
.../bindings/arm/coresight-cpu-debug.txt | 4 ++--
.../devicetree
Coresight platform support assumes that a missing "cpu" phandle
defaults to CPU0. This could be problematic and unnecessarily binds
components to CPU0, where they may not be. In coresight etm and
cpu-debug drivers, abort the probe for such cases.
Signed-off-by: Sai Prakash Ranjan
Do not assume the affinity to CPU0 if cpu phandle is omitted.
Update the DT binding rules to reflect the same by changing it
to a required property.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Suzuki K Poulose
Tested-by: Mathieu Poirier
Reviewed-by: Mathieu Poirier
---
.../devicetree
On 7/4/2019 1:32 AM, Mathieu Poirier wrote:
Hi Greg,
On Thu, 27 Jun 2019 at 12:15, Sai Prakash Ranjan
wrote:
Do not assume the affinity to CPU0 if cpu phandle is omitted.
Update the DT binding rules to reflect the same by changing it
to a required property.
Signed-off-by: Sai Prakash Ranjan
On 6/27/2019 10:54 PM, Mathieu Poirier wrote:
I want to apply your code to my tree but it isn't easy for me to do
so. Did you notice the checkpatch.pl warning about the DT bindings
being in a separate patch? In this case it is not a new binding but
following the process gives the DT
Coresight platform support assumes that a missing "cpu" phandle
defaults to CPU0. This could be problematic and unnecessarily binds
components to CPU0, where they may not be. In coresight etm and
cpu-debug drivers, abort the probe for such cases.
Signed-off-by: Sai Prakash Ranjan
in case of unavailability of respective cpus.
Sai Prakash Ranjan (2):
dt-bindings: coresight: Change CPU phandle to required property
coresight: Do not default to CPU0 for missing CPU phandle
.../bindings/arm/coresight-cpu-debug.txt | 4 ++--
.../devicetree/bindings/arm/coresight.txt
Do not assume the affinity to CPU0 if cpu phandle is omitted.
Update the DT binding rules to reflect the same by changing it
to a required property.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Suzuki K Poulose
---
.../devicetree/bindings/arm/coresight-cpu-debug.txt | 4
of unavailability of respective cpus.
Sai Prakash Ranjan (1):
coresight: Do not default to CPU0 for missing CPU phandle
.../bindings/arm/coresight-cpu-debug.txt | 4 ++--
.../devicetree/bindings/arm/coresight.txt | 8 +---
.../hwtracing/coresight/coresight-cpu-debug.c | 3
y information.
Also in coresight etm and cpu-debug drivers, abort the probe
for such cases.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Suzuki K Poulose
---
.../bindings/arm/coresight-cpu-debug.txt | 4 ++--
.../devicetree/bindings/arm/coresight.txt | 8 +---
.../hwtracing/cor
Hi Mathieu,
On 6/26/2019 11:11 PM, Mathieu Poirier wrote:
Hi Sai,
On Sun, 23 Jun 2019 at 21:36, Sai Prakash Ranjan
wrote:
diff --git a/drivers/hwtracing/coresight/coresight-platform.c
b/drivers/hwtracing/coresight/coresight-platform.c
index 3c5ceda8db24..4990da2c13e9 100644
--- a/drivers
.
Sai Prakash Ranjan (1):
coresight: Do not default to CPU0 for missing CPU phandle
.../bindings/arm/coresight-cpu-debug.txt | 4 ++--
.../devicetree/bindings/arm/coresight.txt | 8 +---
.../hwtracing/coresight/coresight-cpu-debug.c | 3 +++
drivers/hwtracing/coresight/coresight
y information.
Also in coresight etm and cpu-debug drivers, abort the probe
for such cases.
Signed-off-by: Sai Prakash Ranjan
---
.../bindings/arm/coresight-cpu-debug.txt | 4 ++--
.../devicetree/bindings/arm/coresight.txt | 8 +---
.../hwtracing/coresight/coresight-cpu-debug
On 6/24/2019 1:56 PM, Suzuki K Poulose wrote:
Sai,
Thanks for getting this done.
On 24/06/2019 04:36, Sai Prakash Ranjan wrote:
Coresight platform support assumes that a missing "cpu" phandle
defaults to CPU0. This could be problematic and unnecessarily binds
components to C
y information.
Also in coresight etm and cpu-debug drivers, abort the probe
for such cases.
Signed-off-by: Sai Prakash Ranjan
---
.../bindings/arm/coresight-cpu-debug.txt | 4 ++--
.../devicetree/bindings/arm/coresight.txt| 8 +---
.../hwtracing/coresight/coresight-cpu-debug.c
acpi_coresight_get_cpu.
* Removed patch 2 which had invalid check for online
cpus.
v2:
* Addressed review comments from Suzuki and Mathieu.
* Allows the probe of etm and cpu-debug to abort earlier
in case of unavailability of respective cpus.
Sai Prakash Ranjan (1):
coresight: Do
Hello Suzuki,
On 6/21/2019 3:18 PM, Suzuki K Poulose wrote:
Hi Sai,
On 06/20/2019 07:31 PM, Sai Prakash Ranjan wrote:
Coresight platform support assumes that a missing "cpu" phandle
defaults to CPU0. This could be problematic and unnecessarily binds
components to CPU0, wher
Hi Suzuki,
On 6/21/2019 3:10 PM, Suzuki K Poulose wrote:
On 06/20/2019 07:31 PM, Sai Prakash Ranjan wrote:
Currently coresight etm and cpu-debug will go ahead with
the probe even when corresponding cpus are not available
and error out later in the probe path. In such cases, it
is better
to abort
earlier in case cpus are not available.
v2:
* Addressed review comments from Suzuki and Mathieu.
* Allows the probe of etm and cpu-debug to abort earlier
in case of unavailability of respective cpus.
Sai Prakash Ranjan (2):
coresight: Do not default to CPU0 for missing CPU phandle
.etm failed with error -22
[5.964853] coresight-etm4x 85f000.etm: ETM arch init failed
[5.971096] coresight-etm4x: probe of 85f000.etm failed with error -22
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-platform.c | 3 +++
1 file changed, 3 insertions
y information.
Also in coresight etm and cpu-debug drivers, abort the probe
for such cases.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Suzuki K Poulose
---
Documentation/devicetree/bindings/arm/coresight.txt | 2 +-
drivers/hwtracing/coresight/coresight-cpu-debug.c | 3 +++
drivers
Hi Mathieu,
Thanks for the review comments.
On 6/20/2019 11:09 PM, Mathieu Poirier wrote:
Hi Sai,
On Thu, Jun 20, 2019 at 07:15:46PM +0530, Sai Prakash Ranjan wrote:
Affinity defaults to CPU0 in case of missing CPU phandle
and this leads to crashes in some cases because of such
wrong
Hi Mathieu,
Thanks for the review comments.
On 6/20/2019 11:13 PM, Mathieu Poirier wrote:
On Thu, Jun 20, 2019 at 07:15:47PM +0530, Sai Prakash Ranjan wrote:
diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c
b/drivers/hwtracing/coresight/coresight-cpu-debug.c
index 07a1367c733f
On 6/20/2019 8:53 PM, Suzuki K Poulose wrote:
Please wait for Mathieu's thoughts on it. And in general I would wait
for feedback from the people in a version, before posting another one,
to reduce the number of respins.
Mathieu already said he was OK in the other thread, but I will wait
On 6/20/2019 7:28 PM, Suzuki K Poulose wrote:
On 20/06/2019 14:45, Sai Prakash Ranjan wrote:
Currently the coresight etm and cpu-debug drivers
assume the affinity to CPU0 returned by coresight
platform and continue the probe in case of missing
CPU phandle. This is not true and leads to crash
Hi Suzuki,
Thanks for the review.
On 6/20/2019 7:25 PM, Suzuki K Poulose wrote:
Sai,
Thanks for the patch. Please could you change the subject to :
"coresight: Do not default to CPU0 for missing CPU phandle"
Sure.
On 20/06/2019 14:45, Sai Prakash Ranjan wrote:
Affinit
Affinity defaults to CPU0 in case of missing CPU phandle
and this leads to crashes in some cases because of such
wrong assumption. Fix this by returning -ENODEV in
coresight platform for such cases and then handle it
in the coresight drivers.
Signed-off-by: Sai Prakash Ranjan
---
drivers
Currently the coresight etm and cpu-debug drivers
assume the affinity to CPU0 returned by coresight
platform and continue the probe in case of missing
CPU phandle. This is not true and leads to crash
in some cases, so abort the probe in case of missing
CPU phandle.
Signed-off-by: Sai Prakash
In case of missing CPU phandle, the affinity is set default to
CPU0 which is not a correct assumption and leads to crashes
in few cases. Fix this by returning -ENODEV in coresight
platform and abort the probe in coresight etm and cpu-debug
drivers.
Sai Prakash Ranjan (2):
coresight: Set
with this
change and it works just fine.
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On 4/16/2019 8:30 PM, Alexander Shishkin wrote:
Sai Prakash Ranjan writes:
From: Mulu He
Bitmap allocation works on array of unsigned longs and
for stm master allocation when the number of software
channels is 32, 4 bytes are allocated and there is a out of
bound access at the first 8 bytes
On 4/5/2019 6:44 PM, David Laight wrote:
From: Sai Prakash Ranjan
diff --git a/drivers/hwtracing/stm/core.c b/drivers/hwtracing/stm/core.c
index 93ce3aa740a9..21a5838f6e67 100644
--- a/drivers/hwtracing/stm/core.c
+++ b/drivers/hwtracing/stm/core.c
@@ -168,7 +168,7 @@ static int
oduce an abstraction for System Trace
Module devices")
Signed-off-by: Mulu He
Signed-off-by: Sai Prakash Ranjan
Cc: sta...@vger.kernel.org
---
drivers/hwtracing/stm/core.c | 2 +-
drivers/hwtracing/stm/stm.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/st
xes: 7bd1d4093c2f ("stm class: Introduce an abstraction for System Trace
Module devices")
Signed-off-by: Tingwei Zhang
Signed-off-by: Sai Prakash Ranjan
Cc: sta...@vger.kernel.org
---
drivers/hwtracing/stm/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/hwtraci
Hi,
On 2/13/2019 8:10 PM, Pintu Agarwal wrote:
OK thanks for your suggestions. sdm845-perf_defconfig did not work for
me. The target did not boot.
Perf defconfig works fine. You need to enable serial console with below
config added to perf defconfig.
CONFIG_SERIAL_MSM_GENI_CONSOLE=y
Hi Pintu,
On 2/13/2019 2:04 PM, Pintu Agarwal wrote:
This is the complete logs at the time of crash:
[ 21.681020] VFS: Mounted root (ext4 filesystem) readonly on device 8:6.
[ 21.690441] devtmpfs: mounted
[ 21.702517] Freeing unused kernel memory: 6528K
[ 21.75] BUG: sleeping
On 2/8/2019 7:50 PM, Suzuki K Poulose wrote:
On 01/02/2019 00:53, Sai Prakash Ranjan wrote:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree
On 2/8/2019 1:58 AM, Mathieu Poirier wrote:
On Thu, 31 Jan 2019 at 17:55, Sai Prakash Ranjan
wrote:
Add support for coresight CPU debug module on Qualcomm
Kryo CPUs. This patch adds the UCI entries for Kryo CPUs
found on MSM8996 which shares the same PIDs as ETMs.
[..]
I have reviewed
On 2/8/2019 1:56 AM, Mathieu Poirier wrote:
On Thu, 31 Jan 2019 at 17:54, Sai Prakash Ranjan
wrote:
I am good with this patch but there isn't much I can do with it until
Mike's patchset has been merged. Please submit again when that has
been done.
Sure, thanks.
--
QUALCOMM INDIA
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on MSM8998.
Signed-off-by: Sai Prakash Ranjan
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
This depends on MSM8998
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
- Depends on AOSS QMP side channel patches by Bjorn Andersson [1] - [4].
- AMBA
764.etm: CPU6: ETM v4.2 initialized
[6.705646] coresight-etm4x 774.etm: CPU7: ETM v4.2 initialized
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Prakash Ranjan
Reviewed-by: Suzuki K Poulose
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
This patch depends on UCI support by Mike Leach in below link:
* https://lore.kernel.org/lkml/20190130234051.2294-1-mike.le
initialized
[5.501802] OF: graph: no port node found in /soc/debug@3b1
[5.512901] coresight-etm4x: probe of 3b1.debug failed with error -22
[5.513192] coresight-cpu-debug 3b1.debug: Coresight debug-CPU3
initialized
Signed-off-by: Sai Prakash Ranjan
---
For testing, all dependent
From: Vivek Gautam
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
Signed-off-by: Vivek Gautam
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 434
() and added a comment for reason to bypass
the AMBA bus discovery method.
Sai Prakash Ranjan (5):
arm64: dts: qcom: sdm845: Add Coresight support
arm64: dts: qcom: msm8998: Add Coresight support
coresight: etm4x: Add support to enable ETMv4.2
coresight: etm4x: Add ETM PIDs for SDM845
On 2/1/2019 6:17 AM, Sai Prakash Ranjan wrote:
On 1/31/2019 11:31 PM, Suzuki K Poulose wrote:
On 31/01/2019 14:22, Sai Prakash Ranjan wrote:
Add UCI table for coresight CPU debug module. This patch adds
the UCI entries for Kryo CPUs found on MSM8996 which shares
the same PIDs as ETMs
On 1/31/2019 11:31 PM, Suzuki K Poulose wrote:
On 31/01/2019 14:22, Sai Prakash Ranjan wrote:
Add UCI table for coresight CPU debug module. This patch adds
the UCI entries for Kryo CPUs found on MSM8996 which shares
the same PIDs as ETMs.
Without this, below error is observed on MSM8996
On 1/31/2019 10:01 PM, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2019-01-31 06:22:24)
diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c
b/drivers/hwtracing/coresight/coresight-cpu-debug.c
index e8819d750938..915d86a39cee 100644
--- a/drivers/hwtracing/coresight/coresight-cpu
Prakash Ranjan
Reviewed-by: Suzuki K Poulose
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
This patch depends on UCI support by Mike Leach in below link:
* https://lore.kernel.org/lkml/20190130234051.2294-1-mike.le
] OF: graph: no port node found in /soc/debug@3b1
[5.512901] coresight-etm4x: probe of 3b1.debug failed with error -22
[5.513192] coresight-cpu-debug 3b1.debug: Coresight debug-CPU3
initialized
Signed-off-by: Sai Prakash Ranjan
---
For testing, all dependent patches are in below
764.etm: CPU6: ETM v4.2 initialized
[6.705646] coresight-etm4x 774.etm: CPU7: ETM v4.2 initialized
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Vivek Gautam
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
Signed-off-by: Vivek Gautam
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 434
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on MSM8998.
Signed-off-by: Sai Prakash Ranjan
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
This depends on MSM8998
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
For testing, all dependent patches are in below tree:
* https://github.com/saiprakash-ranjan/linux/tree/coresight-next
- Depends on AOSS QMP side channel patches by Bjorn Andersson [1] - [4].
- AMBA
and added coresight cpu debug nodes for msm8996.
* Merged coresight dtsi file into sdm845.dtsi as suggested by Bjorn
* Addressed Mathieu's feedback about masking the minor version in
etm4_arch_supported() and added a comment for reason to bypass
the AMBA bus discovery method.
Sai Prakash
On 1/31/2019 12:07 AM, Mathieu Poirier wrote:
On Tue, Jan 29, 2019 at 12:43:58AM +0530, Sai Prakash Ranjan wrote:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Depends on AOSS QMP side channel patches and AMBA bus pclk change
by Bjorn Andersson
pointer in
the amba_id structure.
Existing drivers that currently use the amba_id->data pointer for private
data are updated to use the amba_cs_uci_id->data pointer. Macros and
inline functions are added to simplify this code.
Thanks Mike, this fixes STM probe with UCI change.
Tested-by: Sai P
}
ret = clk_prepare_enable(pcdev->pclk);
if (ret)
Thanks.
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
cc: clock-controller {
+ compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
};
};
Tested-by: Sai Prakash Ranjan
--
QUALCOMM INDIA
Hi Leo,
On 1/29/2019 7:06 PM, Leo Yan wrote:
I just now found if apply this patch onto coresight next branch [1],
it will conflict with patch 'coresight: cpu-debug: Support for CA73
CPUs' [2]. Sorry if introduce regression by this.
This patch depends on UCI support which is being discussed
On 1/29/2019 6:55 PM, Leo Yan wrote:
Looks good to me and tested on my Hikey board (though I cannot test
for a device with UCI ID):
Reviewed-and-tested-by: Leo Yan
Thanks Leo.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The
On 1/29/2019 2:56 PM, Suzuki K Poulose wrote:
Reviewed-by: Suzuki K Poulose
Thanks Suzuki.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On 1/28/2019 10:45 PM, Mathieu Poirier wrote:
For SDM845(A75 based):
*0xB_B8_03* does indicate that the JEP106 identification
code is 0x3B and continuation code is 0x4 which is of ARM and not
QCOM(JEP106 ID is 0x70) which is expected.
And the other values of PIDR0[0:7] and PIDR1[3:0] are
to ETM4X driver.
Signed-off-by: Sai Prakash Ranjan
---
This patch depends on UCI support by Mike Leach in below link:
https://lore.kernel.org/lkml/20190121233151.13363-2-mike.le...@linaro.org/
---
.../hwtracing/coresight/coresight-cpu-debug.c | 41 +--
1 file changed, 28 insertions
From: Vivek Gautam
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
Signed-off-by: Vivek Gautam
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 434
Prakash Ranjan
---
This patch depends on UCI support by Mike Leach in below link:
https://lore.kernel.org/lkml/20190121233151.13363-2-mike.le...@linaro.org/
---
drivers/hwtracing/coresight/coresight-etm4x.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/hwtracing/coresight
Remove the duplicate inclusion of qcom,gcc-sdm845.h
mistakenly introduced by commit 6e17f8140521 ("arm64:
dts: sdm845: add prng-ee node").
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 -
1 file changed, 1 deletion(-)
764.etm: CPU6: ETM v4.2 initialized
[6.705646] coresight-etm4x 774.etm: CPU7: ETM v4.2 initialized
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on MSM8998.
Signed-off-by: Sai Prakash Ranjan
---
This depends on MSM8998 rpm clocks and rpmcc node by Jeffrey Hugo
and Marc Gonzalez [1][2].
[1]
https://lore.kernel.org/lkml/1545099336-5615-1
into sdm845.dtsi as suggested by Bjorn
* Addressed Mathieu's feedback about masking the minor version in
etm4_arch_supported() and added a comment for reason to bypass
the AMBA bus discovery method.
Sai Prakash Ranjan (6):
arm64: dts: qcom: sdm845: Add Coresight support
arm64: dts: qcom
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Depends on AOSS QMP side channel patches and AMBA bus pclk change
by Bjorn Andersson [1][2].
Also depends on patch ("arm64: dts: qcom: sdm845: Increase address
and size cells for soc") [3].
M fails to probe on both SDM845 and MSM8996.
With this,
Tested-by: Sai Prakash Ranjan
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
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Good day Mathieu,
On 1/24/2019 9:37 PM, Mathieu Poirier wrote:
Good day Sai,
On Wed, 23 Jan 2019 at 13:18, Sai Prakash Ranjan
wrote:
Hi Mathieu,
On 1/24/2019 12:44 AM, Mathieu Poirier wrote:
On Wed, 23 Jan 2019 at 05:12, Sai Prakash Ranjan
wrote:
That depends on whether the ETMs have
On 1/24/2019 9:37 PM, Marc Gonzalez wrote:
On 23/01/2019 21:17, Sai Prakash Ranjan wrote:
On 1/24/2019 12:44 AM, Mathieu Poirier wrote:
What version of the Kryo CPU?
There is no Kryo version for MSM8996 (its only given as Kryo), MSM8998
onwards we have Kryo versions like Kryo 280 and so
Hi Suzuki,
On 1/24/2019 4:49 PM, Suzuki K Poulose wrote:
Hi Sai,
That looks fine with me. But as Mathieu said, this needs to be a separate
patch. But before all that please could you provide me the PIDR4 value for
the Kryo A75 and A55 please ?
Sure.
PIDR4 value is 0x4.
I get it now. So
Hi Mathieu,
On 1/24/2019 12:44 AM, Mathieu Poirier wrote:
On Wed, 23 Jan 2019 at 05:12, Sai Prakash Ranjan
wrote:
That depends on whether the ETMs have been modified at all, something
Suzuki has asked to be clarified. If ETMs have been modified then we
need to understand how they differ from
Hi Suzuki,
On 1/23/2019 1:42 AM, Suzuki K Poulose wrote:
Hi Sai,
On 01/22/2019 04:48 PM, Sai Prakash Ranjan wrote:
Hi Suzuki,
[..]
SDM845 has 4 Kryo 385 Gold (ARM A75) + 4 Kryo 385 Silver (ARM A55),
so the PID values should be same for 4 ETMs atleast. But here one
pid value(001bb803
Hi Suzuki,
On 1/22/2019 9:38 PM, Suzuki K Poulose wrote:
By inconsistent, I meant the registers provides values which are not
the same on two different CPUs of the *same type*. And it is expected
that two different CPU/ETM implementations will have different PIDs.
SDM845 has 4 Kryo 385 Gold
Hi Suzuki,
Thanks for looking into this. Please find my response inline.
On 1/22/2019 7:30 PM, Suzuki K Poulose wrote:
Hi Sai,
On 01/22/2019 01:37 PM, Sai Prakash Ranjan wrote:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
Sorry, but I hadn't
On 1/22/2019 3:07 AM, Mathieu Poirier wrote:
On Mon, 21 Jan 2019 at 11:48, Mathieu Poirier
wrote:
On Mon, Jan 21, 2019 at 04:18:36PM +0530, Vivek Gautam wrote:
On 1/18/2019 5:52 PM, Sai Prakash Ranjan wrote:
SDM845 has ETMv4.2 and can use the existing etm4x driver.
But the current etm
Hi Mathieu,
On 1/22/2019 12:07 AM, Mathieu Poirier wrote:
Hi Sai,
On Fri, Jan 18, 2019 at 05:52:53PM +0530, Sai Prakash Ranjan wrote:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
This depends on AMBA bus pclk change by Bjorn Andersson [1
Remove the duplicate inclusion of qcom,gcc-sdm845.h
mistakenly introduced by commit 6e17f8140521 ("arm64:
dts: sdm845: add prng-ee node").
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 -
1 file changed, 1 deletion(-)
-etm4x 764.etm: CPU6: ETM v4.2 initialized
[6.705646] coresight-etm4x 774.etm: CPU7: ETM v4.2 initialized
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing
From: Vivek Gautam
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
Signed-off-by: Vivek Gautam
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 448
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Depends on AOSS QMP side channel patches and AMBA bus pclk change
by Bjorn Andersson [1][2].
Also depends on patch ("arm64: dts: qcom: sdm845: Increase address
and size cells for soc") [3].
the AMBA bus discovery method.
Sai Prakash Ranjan (3):
arm64: dts: qcom: sdm845: Add Coresight support
coresight: etm4x: Add support to enable ETMv4.2
arm64: dts: qcom: sdm845: Remove the duplicate header inclusion
Vivek Gautam (1):
arm64: dts: qcom: msm8996: Add Coresight support
arch
Remove the duplicate inclusion of qcom,gcc-sdm845.h
mistakenly introduced by commit 6e17f8140521 ("arm64:
dts: sdm845: add prng-ee node").
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Douglas Anderson
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 -
1 file changed, 1 deletion(-)
coresight dtsi file into sdm845.dtsi as suggested by Bjorn
* Addressed Mathieu's feedback about masking the minor version in
etm4_arch_supported() and added a comment for reason to bypass
the AMBA bus discovery method.
Sai Prakash Ranjan (3):
arm64: dts: qcom: sdm845: Add Coresight support
-etm4x 764.etm: CPU6: ETM v4.2 initialized
[6.705646] coresight-etm4x 774.etm: CPU7: ETM v4.2 initialized
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
2 files changed, 2 insertions
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
This depends on AMBA bus pclk change by Bjorn Andersson [1].
Also depends on patch ("arm64: dts: qcom: sdm845: Increase address
and size cells for soc") [2].
[1]
https://lore.kerne
From: Vivek Gautam
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
Signed-off-by: Vivek Gautam
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 448
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