On 3/22/2021 10:36 PM, Randy Dunlap wrote:
> [CAUTION: External Email]
>
> On 3/21/21 9:59 PM, Sanjay R Mehta wrote:
>> From: Sanjay R Mehta
>>
>> Add support for AMD PTDMA controller. It performs high-bandwidth
>> memory to memory and IO copy operation. Dev
On 3/22/2021 10:29 AM, Sanjay R Mehta wrote:
> From: Sanjay R Mehta
>
> This patch series add support for AMD PTDMA controller which
> performs high bandwidth memory-to-memory and IO copy operation,
> performs DMA transfer through queue based descriptor management.
>
&
On 3/22/2021 11:34 AM, Vinod Koul wrote:
> [CAUTION: External Email]
>
> On 18-03-21, 16:16, Sanjay R Mehta wrote:
>>>> +#include
>>>> +#include
>>>> +#include
>>>> +#include
>>>> +#include
>>>> +#include
From: Sanjay R Mehta
Add support for AMD PTDMA controller. It performs high-bandwidth
memory to memory and IO copy operation. Device commands are managed
via a circular queue of 'descriptors', each of which specifies source
and destination addresses for copying a single buffer of dat
From: Sanjay R Mehta
This patch series add support for AMD PTDMA controller which
performs high bandwidth memory-to-memory and IO copy operation,
performs DMA transfer through queue based descriptor management.
AMD Processor has multiple ptdma device instances with each controller
having single
From: Sanjay R Mehta
Expose data about the configuration and operation of the
PTDMA through debugfs entries: device name, capabilities,
configuration, statistics.
Signed-off-by: Sanjay R Mehta
---
drivers/dma/ptdma/Makefile| 2 +-
drivers/dma/ptdma/ptdma-debugfs.c | 115
From: Sanjay R Mehta
Register ptdma queue to Linux dmaengine framework as general-purpose
DMA channels.
Signed-off-by: Sanjay R Mehta
---
drivers/dma/ptdma/Kconfig | 2 +
drivers/dma/ptdma/Makefile | 2 +-
drivers/dma/ptdma/ptdma-dev.c | 32 +++
drivers/dma/ptdma
>> + dma_dev->dst_addr_widths = PT_DMA_WIDTH(dma_get_mask(pt->dev));
>> + dma_dev->directions = DMA_MEM_TO_MEM;
>> + dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
>> + dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
>> + dma_cap_set(DMA_INTERRUPT, dma_dev->cap_m
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>
> why do you need sched.h here?
>
>> +
>> +#include "ptdma.h"
>> +
>> +/* Ever-increasing value to produce unique unit numbers */
>> +static atomic_t pt_ordinal;
>
> Wh
On 11/24/2020 7:53 PM, Vitaly Mayatskih wrote:
> [CAUTION: External Email]
>
> On Wed, Nov 18, 2020 at 7:20 AM Vinod Koul wrote:
>
>> this should be single line
>
> Vinod, do you see any obvious functional defects still present in the
> driver, or can it be finally merged for us to start tes
On 11/24/2020 10:48 PM, Vinod Koul wrote:
> [CAUTION: External Email]
>
> Hello Vitaly,
>
> On 24-11-20, 09:23, Vitaly Mayatskih wrote:
>> On Wed, Nov 18, 2020 at 7:20 AM Vinod Koul wrote:
>>
>>> this should be single line
>>
>> Vinod, do you see any obvious functional defects still present i
On 10/16/2020 1:09 PM, Sanjay R Mehta wrote:
> From: Sanjay R Mehta
>
> This patch series adds support for AMD PTDMA controller which
> performs high bandwidth memory-to-memory and IO copy operation,
> performs DMA transfer through queue based descriptor management.
>
&
> Sanjay R Mehta (3):
> dmaengine: ptdma: Initial driver for the AMD PTDMA
> dmaengine: ptdma: register PTDMA controller as a DMA resource
> dmaengine: ptdma: Add debugfs entries for PTDMA information
>
> MAINTAINERS | 6 +
>
From: Sanjay R Mehta
if DL_ACTIVE bit is set it means that there is no need to check
PCI_EXP_LNKSTA_LT bit, as DL_ACTIVE would have set only if the link
is already trained. Hence adding a check which takes care of this
scenario.
Signed-off-by: Sanjay R Mehta
---
drivers/pci/hotplug
From: Sanjay R Mehta
This patch series adds support for AMD PTDMA controller which
performs high bandwidth memory-to-memory and IO copy operation,
performs DMA transfer through queue based descriptor management.
AMD Processor has multiple ptdma device instances with each controller
having
From: Sanjay R Mehta
Register ptdma queue to Linux dmaengine framework as general-purpose
DMA channels.
Signed-off-by: Sanjay R Mehta
---
drivers/dma/ptdma/Kconfig | 2 +
drivers/dma/ptdma/Makefile | 2 +-
drivers/dma/ptdma/ptdma-dev.c | 32 +++
drivers/dma/ptdma
From: Sanjay R Mehta
Adding support for AMD PTDMA controller. It performs high-bandwidth
memory to memory and IO copy operation. Device commands are managed
via a circular queue of 'descriptors', each of which specifies source
and destination addresses for copying a single buff
From: Sanjay R Mehta
Expose data about the configuration and operation of the
PTDMA through debugfs entries: device name, capabilities,
configuration, statistics.
Signed-off-by: Sanjay R Mehta
---
drivers/dma/ptdma/Makefile| 2 +-
drivers/dma/ptdma/ptdma-debugfs.c | 115
From: Sanjay R Mehta
This patch series adds support for AMD PTDMA controller which
performs high bandwidth memory-to-memory and IO copy operation,
performs DMA transfer through queue based descriptor management.
AMD Processor has multiple ptdma device instances with each controller
having
From: Sanjay R Mehta
Expose data about the configuration and operation of the
PTDMA through debugfs entries: device name, capabilities,
configuration, statistics.
Signed-off-by: Sanjay R Mehta
---
drivers/dma/ptdma/Makefile| 2 +-
drivers/dma/ptdma/ptdma-debugfs.c | 115
From: Sanjay R Mehta
Register ptdma queue to Linux dmaengine framework as general-purpose
DMA channels.
Signed-off-by: Sanjay R Mehta
---
drivers/dma/ptdma/Kconfig | 2 +
drivers/dma/ptdma/Makefile | 2 +-
drivers/dma/ptdma/ptdma-dev.c | 32 ++
drivers/dma/ptdma
From: Sanjay R Mehta
Adding support for AMD PTDMA controller. It performs high-bandwidth
memory to memory and IO copy operation. Device commands are managed
via a circular queue of 'descriptors', each of which specifies source
and destination addresses for copying a single buff
On 10/7/2020 1:08 AM, Lukas Wunner wrote:
> [CAUTION: External Email]
>
> On Tue, Oct 06, 2020 at 01:24:28PM -0500, Sanjay R Mehta wrote:
>> if DL_ACTIVE bit is set it means that there is no need to check
>> PCI_EXP_LNKSTA_LT bit, as DL_ACTIVE would have set only if t
From: Sanjay R Mehta
if DL_ACTIVE bit is set it means that there is no need to check
PCI_EXP_LNKSTA_LT bit, as DL_ACTIVE would have set only if the link
is already trained. Hence adding a check which takes care of this
scenario.
Signed-off-by: Sanjay R Mehta
---
drivers/pci/hotplug
This driver supports hardware watchdog for AMD SoCs.
Signed-off-by: Sanjay R Mehta
---
MAINTAINERS| 5 +
drivers/watchdog/Kconfig | 14 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/amd_wdt.c | 361 +
4 files changed, 381
> On 24-08-20, 13:11, Sanjay R Mehta wrote:
>> Apologies for my delayed response.
>>
>> On 7/3/2020 12:48 PM, Vinod Koul wrote:
>>> [CAUTION: External Email]
>>>
>>> On 16-06-20, 20:11, Sanjay R Mehta wrote:
>>>
>
On 7/3/2020 1:07 PM, Vinod Koul wrote:
>
> On 16-06-20, 20:11, Sanjay R Mehta wrote:
>
>> --- a/drivers/dma/ptdma/Makefile
>> +++ b/drivers/dma/ptdma/Makefile
>> @@ -5,6 +5,7 @@
>>
>> obj-$(CONFIG_AMD_PTDMA) += ptdma.o
>>
>> -ptdm
>
> On 16-06-20, 20:11, Sanjay R Mehta wrote:
>> From: Sanjay R Mehta
>>
>> Expose data about the configuration and operation of the
>> PTDMA through debugfs entries: device name, capabilities,
>> configuration, statistics.
>>
>> Signed-off-
Apologies for my delayed response.
On 7/3/2020 12:48 PM, Vinod Koul wrote:
> [CAUTION: External Email]
>
> On 16-06-20, 20:11, Sanjay R Mehta wrote:
>
>> +static int pt_core_execute_cmd(struct ptdma_desc *desc,
>> +struct pt_cmd_queue *cmd_
From: Sanjay R Mehta
Expose data about the configuration and operation of the
PTDMA through debugfs entries: device name, capabilities,
configuration, statistics.
Signed-off-by: Sanjay R Mehta
---
drivers/dma/ptdma/Makefile| 3 +-
drivers/dma/ptdma/ptdma-debugfs.c | 130
From: Sanjay R Mehta
This patch series adds support for AMD PTDMA controller which
performs high bandwidth memory-to-memory and IO copy operation and
performs DMA transfer through queue based descriptor management.
AMD Processor has multiple ptdma device instances and each controller
has single
From: Sanjay R Mehta
This registers the ptdma queue to Linux dmaengine framework
as general-purpose DMA channels.
Signed-off-by: Sanjay R Mehta
---
drivers/dma/ptdma/Kconfig | 2 +
drivers/dma/ptdma/Makefile | 3 +-
drivers/dma/ptdma/ptdma-dev.c | 33 ++
drivers
From: Sanjay R Mehta
This driver add support for AMD PTDMA controller. This device
performs high-bandwidth memory to memory and IO copy operation.
Device commands are managed via a circular queue of 'descriptors',
each of which specifies source and destination addresses for copyin
On 5/4/2020 11:44 AM, Vinod Koul wrote:
> [CAUTION: External Email]
>
> On 28-04-20, 16:13, Sanjay R Mehta wrote:
>
>> +static void pt_do_cmd_complete(unsigned long data)
>> +{
>> + struct pt_tasklet_data *tdata = (struct pt_tasklet_data *)data;
>> +
On 5/26/2020 11:59 AM, Greg KH wrote:
> [CAUTION: External Email]
>
> On Tue, May 26, 2020 at 11:35:02AM +0530, Sanjay R Mehta wrote:
>> Apologies for my delayed response.
>>
>>>> +#include
>>>> +#include
>>>> +#include
>&
>> +static const struct file_operations pt_debugfs_info_ops = {
>> + .owner = THIS_MODULE,
>> + .open = simple_open,
>> + .read = ptdma_debugfs_info_read,
>> + .write = NULL,
>> +};
>> +
>> +static const struct file_operations pt_debugfs_queue_ops = {
>> + .owner = THIS_MODULE,
Apologies for my delayed response.
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "ptdma.h"
>> +
>> +static int cmd_queue_length = 32;
>> +module_param(cmd_queue_length, uint, 0644);
>> +MODULE_PARM_DESC(cmd_queue_length,
>> + " length of the c
After trying to send commands for a maximum of MSG_TRIES
re-tries, link-up fails due to short sleep time(1ms) between
re-tries. Hence increasing the sleep time to one second providing
sufficient time for perf link-up.
Signed-off-by: Sanjay R Mehta
Signed-off-by: Arindam Nath
---
drivers/ntb
eve this is by changing the
first parameter of dma_alloc_coherent() as ntb->pdev->dev
instead.
Fixes: 5648e56 ("NTB: ntb_perf: Add full multi-port NTB API support")
Signed-off-by: Logan Gunthorpe
Signed-off-by: Sanjay R Mehta
Signed-off-by: Arindam Nath
---
drivers/ntb/test/ntb_per
eve this is by changing the
first parameter of dma_alloc_coherent() as ntb->pdev->dev
instead.
Fixes: 5648e56 ("NTB: ntb_perf: Add full multi-port NTB API support")
Signed-off-by: Sanjay R Mehta
Signed-off-by: Arindam Nath
---
drivers/ntb/test/ntb_tool.c | 6 +++---
1 file changed,
The DMA map and unmap of destination address is already being
done in perf_init_test() and perf_clear_test() functions.
Hence avoiding it by making necessary changes in perf_copy_chunk()
function.
Signed-off-by: Sanjay R Mehta
Signed-off-by: Arindam Nath
---
drivers/ntb/test/ntb_perf.c | 11
: hw: remove the code that sets the DMA mask
Sanjay R Mehta (4):
ntb_perf: pass correct struct device to dma_alloc_coherent
ntb_tool: pass correct struct device to dma_alloc_coherent
ntb_perf: increase sleep time from one milli sec to one sec
ntb_perf: avoid false dma unmap of destination
From: Logan Gunthorpe
This patch removes the code that sets the DMA mask as it no longer
makes sense to do this.
Fixes: 7f46c8b3a552 ("NTB: ntb_tool: Add full multi-port NTB API support")
Signed-off-by: Logan Gunthorpe
Tested-by: Alexander Fomichev
Signed-off-by: Sanjay R Mehta
--
From: Sanjay R Mehta
This registers the ptdma queue to Linux dmaengine framework
as general-purpose DMA channels.
Signed-off-by: Sanjay R Mehta
---
drivers/dma/ptdma/Kconfig | 2 +
drivers/dma/ptdma/Makefile | 3 +-
drivers/dma/ptdma/ptdma-dev.c | 35 +++
drivers
From: Sanjay R Mehta
Expose data about the configuration and operation of the
PTDMA through debugfs entries: device name, capabilities,
configuration, statistics.
Signed-off-by: Sanjay R Mehta
---
drivers/dma/ptdma/Makefile| 3 +-
drivers/dma/ptdma/ptdma-debugfs.c | 237
From: Sanjay R Mehta
This driver add support for AMD PTDMA controller. This device
performs high-bandwidth memory to memory and IO copy operation.
Device commands are managed via a circular queue of 'descriptors',
each of which specifies source and destination addresses for copyin
From: Sanjay R Mehta
This patch series adds support for AMD PTDMA controller which
performs high bandwidth memory-to-memory and IO copy operation and
performs DMA transfer through queue based descriptor management.
AMD Processor has multiple ptdma device instances and each controller
has single
On 9/25/2019 12:42 AM, Vinod Koul wrote:
> [CAUTION: External Email]
>
> On 24-09-19, 07:31, Mehta, Sanju wrote:
>> From: Sanjay R Mehta
>>
>> This is the driver for the AMD passthrough DMA Engine
> Please fix threading for your series, they are all over my inbox
On 9/24/2019 10:07 PM, Vinod Koul wrote:
> [CAUTION: External Email]
>
> On 24-09-19, 07:31, Mehta, Sanju wrote:
>> From: Sanjay R Mehta
>>
>> *** This patch series adds support for AMD PTDMA engine ***
> What lots of stars!
>
> Can you describe the controll
On 9/24/2019 8:05 PM, Randy Dunlap wrote:
> [CAUTION: External Email]
>
> On 9/24/19 12:31 AM, Mehta, Sanju wrote:
>> From: Sanjay R Mehta
>>
>> This is the driver for the AMD passthrough DMA Engine
>>
>> Signed-off-by: Sanjay R Mehta
>> Reviewed
On 9/24/2019 1:35 PM, gre...@linuxfoundation.org wrote:
> [CAUTION: External Email]
>
> On Tue, Sep 24, 2019 at 07:33:02AM +, Mehta, Sanju wrote:
>> +static const struct file_operations pt_debugfs_info_ops = {
>> + .owner = THIS_MODULE,
>> + .open = simple_open,
>> + .read = ptdma_
On 9/24/2019 1:35 PM, gre...@linuxfoundation.org wrote:
> [CAUTION: External Email]
>
> On Tue, Sep 24, 2019 at 07:33:02AM +, Mehta, Sanju wrote:
>> +static const struct file_operations pt_debugfs_info_ops = {
>> + .owner = THIS_MODULE,
>> + .open = simple_open,
>> + .read = ptdma_
On 3/20/2019 11:20 PM, Jon Mason wrote:
> On Fri, Feb 15, 2019 at 09:20:07AM +, Mehta, Sanju wrote:
>> From: Sanjay R Mehta
>>
>> while waiting for the peer ntb_perf to initialize scratchpad
>> registers, local side ntb_perf might have already exhausted the
&
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