On Wed, Mar 10, 2021, Paolo Bonzini wrote:
> On 10/03/21 01:30, Sean Christopherson wrote:
> > diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp_mmu.c
> > index 50ef757c5586..f0c99fa04ef2 100644
> > --- a/arch/x86/kvm/mmu/tdp_mmu.c
> > +++ b/arch/x86/kvm/
On Wed, Mar 10, 2021, Peter Zijlstra wrote:
> On Tue, Mar 09, 2021 at 09:10:19AM -0800, Sean Christopherson wrote:
>
> > @@ -2024,9 +2021,6 @@ static int __init init_hw_perf_events(void)
> > if (!x86_pmu.read)
> > x86_pmu.read = _x86_pm
On Wed, Mar 10, 2021, Martin Radev wrote:
> On Wed, Mar 10, 2021 at 08:08:37AM -0800, Sean Christopherson wrote:
> > On Wed, Mar 10, 2021, Joerg Roedel wrote:
> > > + /*
> > > + * Sanity check CPUID results from the Hypervisor. See comment in
> > > + * do_
On Wed, Mar 10, 2021, Joerg Roedel wrote:
> From: Joerg Roedel
>
> The 32-bit #VC handler has no GHCB and can only handle CPUID exit codes.
> It is needed by the early boot code to handle #VC exceptions raised in
> verify_cpu() and to get the position of the C bit.
>
> But the CPUID information
On Wed, Mar 10, 2021, Jarkko Sakkinen wrote:
> On Wed, Mar 03, 2021 at 08:56:52AM -0800, Dave Hansen wrote:
> > On 3/3/21 7:03 AM, Jarkko Sakkinen wrote:
> > > If sgx_page_cache_init() fails in the middle, a trivial return
> > > statement causes unused memory and virtual address space reserved for
GPRs (it's a subtly big function), as well as
several conditional branches before bailing out.
Cc: Ben Gardon
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/tdp_mmu.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/kvm/mmu/tdp_mmu.c b/arch/x86/kvm/mmu/tdp
On Wed, Mar 03, 2021, Haiwei Li wrote:
> On 21/3/3 10:09, lihaiwei.ker...@gmail.com wrote:
> > From: Haiwei Li
> >
> > In my test environment, advance_expire_delta is frequently greater than
> > the fixed LAPIC_TIMER_ADVANCE_ADJUST_MAX. And this will hinder the
> > adjustment.
>
> Supplementary
er.kernel.org
Cc: Brijesh Singh
Cc: Tom Lendacky
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 22 +-
arch/x86/kvm/svm/svm.c | 5 ++---
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 6
, etc...
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 24 +---
arch/x86/kvm/mmu/mmu_audit.c| 2 +-
arch/x86/kvm/mmu/mmu_internal.h | 10 ++
3 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/ar
From: Sean Christopherson
Fix a merge conflict gone bad.
Fixes: a16241ae56fa ("KVM: x86: Get active PCID only when writing a CR3 value")
Signed-off-by: Sean Christopherson
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/svm.c | 8 +++-
1 file changed, 7 insertions(+),
fireworks, crashes KVM, and likely hangs the host kernel.
Fixes: b14e28f37e9b ("KVM: x86/mmu: Use a dedicated bit to track
shadow/MMU-present SPTEs")
Reported-by: Tom Lendacky
Reported-by: Paolo Bonzini
Reviewed-by: Maxim Levitsky
Tested-by: Tom Lendacky
Signed-off-by: Sean Chri
snafu, though
I expect they'll get squashed away.
- Added the PAE patches from the SME shadow paging fixes to avoid
spreading out the dependencies.
Sean Christopherson (4):
KVM: x86: Fixup "Get active PCID only when writing a CR3 value"
KVM: x86/mmu: Exclude the MMU_PRES
On Tue, Mar 09, 2021, Jim Mattson wrote:
> On Tue, Mar 9, 2021 at 9:10 AM Sean Christopherson
> wrote:
> > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> > index 50810d471462..32cf8287d4a7 100644
> > --- a/arch/x86/kvm/vmx/vmx.c
> > +++ b/arch/x8
On Mon, Mar 08, 2021, Steve Rutherford wrote:
> On Mon, Mar 8, 2021 at 1:11 PM Brijesh Singh wrote:
> > On 3/8/21 1:51 PM, Sean Christopherson wrote:
> > > If the guest does the hypercall after writing the page, then the guest is
> > > hosed
> > > if it
On Fri, Mar 05, 2021, Ashish Kalra wrote:
> On Thu, Feb 25, 2021 at 10:49:00AM -0800, Steve Rutherford wrote:
> > On Thu, Feb 25, 2021 at 6:57 AM Tom Lendacky
> > wrote:
> > > >> +int svm_vm_copy_asid_to(struct kvm *kvm, unsigned int mirror_kvm_fd)
> > > >> +{
> > > >> + struct file *mirror
On Mon, Mar 08, 2021, Sean Christopherson wrote:
> From: Sean Christopherson
>
> Fix SME and PCID, which got horribly mangled on application.
Gah, the SME changes are supposed to be in "KVM: x86/mmu: Mark the PAE roots as
decrypted for shadow paging", which has not yet bee
u
Cc: Paolo Bonzini
Cc: Jim Mattson
Reported-by: Dmitry Vyukov
Reported-by: syzbot+cce9ef2dd25246f81...@syzkaller.appspotmail.com
Suggested-by: Peter Zijlstra
Signed-off-by: Sean Christopherson
---
v2:
- Use __static_call_return0 to return NULL instead of manually checking
the hook at
On Tue, Mar 09, 2021, Peter Zijlstra wrote:
> On Tue, Mar 09, 2021 at 08:46:49AM +0100, Peter Zijlstra wrote:
> > On Mon, Mar 08, 2021 at 12:40:44PM -0800, Sean Christopherson wrote:
> > > On Mon, Mar 08, 2021, Peter Zijlstra wrote:
> >
> > > > Given the one us
fireworks, crashes KVM, and likely hangs the host kernel.
Fixes: b14e28f37e9b ("KVM: x86/mmu: Use a dedicated bit to track
shadow/MMU-present SPTEs")
Reported-by: Tom Lendacky
Reported-by: Paolo Bonzini
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/spte.h | 12 +++-
1 fi
bits.
For the PCID thing, note that there are two patches with the same changelog.
Not sure what's intended there...
Also, I forgot about adding the PAE root helpers until I tried testing and
PAE didn't work with SME. I'll get those to you tomorrow.
Sean Christopherson (2):
KV
From: Sean Christopherson
Fix SME and PCID, which got horribly mangled on application.
Fixes: a16241ae56fa ("KVM: x86: Get active PCID only when writing a CR3 value")
Signed-off-by: Sean Christopherson
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/svm.c | 9 +++
On Mon, Mar 08, 2021, Paolo Bonzini wrote:
> On 05/03/21 19:31, Sean Christopherson wrote:
> > Sean Christopherson (11):
> >KVM: x86: Get active PCID only when writing a CR3 value
...
> Huh, I was sure I had queued this already for 5.12. Well, done so now.
Maybe this seri
On Mon, Mar 08, 2021, syzbot wrote:
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:a38fd874 Linux 5.12-rc2
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=14158fdad0
> kernel config: https://syzkaller.appspot.com/x/.config?x=db9c6
On Mon, Mar 08, 2021, Sean Christopherson wrote:
> On Mon, Mar 08, 2021, Tom Lendacky wrote:
> > On the hypervisor, I see the following:
> >
> > [ 55.886136] get_mmio_spte: detect reserved bits on spte, addr
> > 0xffc12792, dump hierarchy:
> > [ 55.895284
On Mon, Mar 08, 2021, Paolo Bonzini wrote:
> On 08/03/21 17:44, Sean Christopherson wrote:
> > VMCALL is also probably ok
> > in most scenarios, but patching L2's code from L0 KVM is sketchy.
>
> I agree that patching is sketchy and I'll send a patch. However...
&g
On Mon, Mar 08, 2021, Peter Zijlstra wrote:
> On Mon, Mar 08, 2021 at 10:25:59AM +0800, Xu, Like wrote:
> > On 2021/3/6 6:33, Sean Christopherson wrote:
> > > Handle a NULL x86_pmu.guest_get_msrs at invocation instead of patching
> > > in perf_guest_get_msrs_nop() during
On Mon, Mar 08, 2021, Tom Lendacky wrote:
> On 2/25/21 2:47 PM, Sean Christopherson wrote:
> > Introduce MMU_PRESENT to explicitly track which SPTEs are "present" from
> > the MMU's perspective. Checking for shadow-present SPTEs is a very
> > common operat
On Mon, Mar 08, 2021, Ashish Kalra wrote:
> On Fri, Feb 26, 2021 at 09:44:41AM -0800, Sean Christopherson wrote:
> > +Will and Quentin (arm64)
> >
> > Moving the non-KVM x86 folks to bcc, I don't they care about KVM details at
> > this
> > point.
> >
On Mon, Mar 08, 2021, Maxim Levitsky wrote:
> On Thu, 2021-03-04 at 18:16 -0800, Sean Christopherson wrote:
> > Directly connect the 'npt' param to the 'npt_enabled' variable so that
> > runtime adjustments to npt_enabled are reflected in sysfs. Move the
> &g
On Sat, Mar 06, 2021, Paolo Bonzini wrote:
> On 06/03/21 02:39, Sean Christopherson wrote:
> > Unless KVM (L0) knowingly wants to override L1, e.g. KVM_GUESTDBG_* cases,
> > KVM
> > shouldn't do a damn thing except forward the exception to L1 if
VM_AMD_SEV)
check in svm_sev_enabled(), which will be dropped in a future patch.
Reviewed by: Tom Lendacky
Reviewed-by: Brijesh Singh
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/sev.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/svm/sev.c b/ar
VM if
SEV_INIT fails, but that's a problem for another day.
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/sev.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index 3bf04a697723..f8ebda7c3
e intended.
Acked-by: Tom Lendacky
Reviewed-by: Brijesh Singh
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/sev.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index 871e040aad16..d6f069271e75 10
E_BY_DEFAULT has the
unfortunate side effect of enabling all the SEV-ES _guest_ code due to
it being dependent on CONFIG_AMD_MEM_ENCRYPT=y.
Cc: Borislav Petkov
Cc: Tom Lendacky
Cc: Brijesh Singh
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/sev.c | 4 ++--
1 file changed, 2 insertions(+),
Remove the forward declaration of sev_flush_asids(), which is only a few
lines above the function itself.
No functional change intended.
Reviewed by: Tom Lendacky
Reviewed-by: Brijesh Singh
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/sev.c | 1 -
1 file changed, 1 deletion
Move the allocation of the SEV VMCB array to sev.c to help pave the way
toward encapsulating SEV enabling wholly within sev.c.
No functional change intended.
Reviewed by: Tom Lendacky
Reviewed-by: Brijesh Singh
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/sev.c | 12
: Brijesh Singh
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/sev.c | 6 +++---
arch/x86/kvm/svm/svm.h | 5 -
2 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index 4685be80f551..9837fd753d88 100644
--- a/arch/x86/kvm/svm
material. [Tom]
- Collect one Ack. [Tom]
v1:
- https://lkml.kernel.org/r/20210109004714.1341275-1-sea...@google.com
Sean Christopherson (14):
KVM: SVM: Zero out the VMCB array used to track SEV ASID association
KVM: SVM: Free sev_asid_bitmap during init if SEV setup fails
KVM: SVM: Move SEV mo
t
side of things has already laid claim to 'sev_enabled'.
Reviewed-by: Tom Lendacky
Reviewed-by: Brijesh Singh
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/sev.c | 11 +++
arch/x86/kvm/svm/svm.c | 15 +--
arch/x86/kvm/svm/svm.h | 2 --
3 files changed,
t; for its own
purposes.
No functional change intended.
Reviewed-by: Tom Lendacky
Reviewed-by: Brijesh Singh
Signed-off-by: Sean Christopherson
---
arch/x86/include/asm/mem_encrypt.h | 1 -
arch/x86/mm/mem_encrypt.c | 12 +---
arch/x86/mm/mem_encrypt_identity.c | 1 -
3 file
Query max_sev_asid directly after setting it instead of bouncing through
its wrapper, svm_sev_enabled(). Using the wrapper is unnecessary
obfuscation.
No functional change intended.
Reviewed by: Tom Lendacky
Reviewed-by: Brijesh Singh
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm
Singh
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/svm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 6dd8bcf3e8fa..0fa6c409b484 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -883,8
#x27; flag directly. While sev_hardware_enabled() checks max_sev_asid,
which is true even if KVM setup fails, 'sev' will be true if and only
if KVM setup fully succeeds.
Fixes: 33af3a7ef9e6 ("KVM: SVM: Reduce WBINVD/DF_FLUSH invocations")
Cc: Tom Lendacky
Signed-off-by: Sean Christo
islav Petkov
Reviewed-by: Tom Lendacky
Reviewed-by: Brijesh Singh
Fixes: 70cd94e60c73 ("KVM: SVM: VMRUN should use associated ASID when SEV is
enabled")
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/svm.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/a
know it can skip CLFLUSH operations.
Cc: Tom Lendacky
Cc: Brijesh Singh
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/cpuid.c | 6 ++
arch/x86/kvm/cpuid.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 6bd2f8b830e4..45745c6c2161
Hopefully I got the In-Reply-To header right...
On Thu, May 28, 2020, Paolo Bonzini wrote:
> This allows exceptions injected by the emulator to be properly delivered
> as vmexits. The code also becomes simpler, because we can just let all
> L0-intercepted exceptions go through the usual path. In
putting random garbage from the stack into the MSR
load list.
Fixes: abd562df94d1 ("x86/perf: Use static_call for x86_pmu.guest_get_msrs")
Cc: Like Xu
Cc: Paolo Bonzini
Cc: Jim Mattson
Cc: k...@vger.kernel.org
Reported-by: Dmitry Vyukov
Signed-off-by: Sean Christopherson
---
arch/
I'm an idiot and Cc'd my old @intel.com address on everything. Apologies in
advance for the inevitable bounces. :-/
On Fri, Mar 05, 2021, Sean Christopherson wrote:
> Clean up KVM's PV TLB flushing when running with EPT on Hyper-V, i.e. as
> a nested VMM. No real goal i
From: Sean Christopherson
Track the address of the top-level EPT struct, a.k.a. the root HPA,
instead of the EPTP itself for Hyper-V's paravirt TLB flush. The
paravirt API takes only the address, not the full EPTP, and in theory
tracking the EPTP could lead to false negatives, e.g. if th
From: Sean Christopherson
Don't invalidate the common EPTP, and thus trigger rechecking of EPTPs
across all vCPUs, if the new EPTP matches the old/common EPTP. In all
likelihood this is a meaningless optimization, but there are (uncommon)
scenarios where KVM can reload the same EPTP.
Rev
From: Sean Christopherson
Drop the dedicated 'ept_pointers_match' field in favor of stuffing
'hv_tlb_eptp' with INVALID_PAGE to mark it as invalid, i.e. to denote
that there is at least one EPTP mismatch. Use a local variable to
track whether or not a mismatch is detected
From: Sean Christopherson
Ifdef away the Hyper-V specific fields in structs kvm_vmx and vcpu_vmx
as each field has only a single reference outside of the struct itself
that isn't already wrapped in ifdeffery (and both are initialization).
vcpu_vmx.ept_pointer in particular should be wrapp
From: Sean Christopherson
Explicitly check that kvm_x86_ops.tlb_remote_flush() points at Hyper-V's
implementation for PV flushing instead of assuming that a non-NULL
implementation means running on Hyper-V. Wrap the related logic in
ifdeffery as hv_remote_flush_tlb() is define
From: Sean Christopherson
Skip additional EPTP flushes if one fails when processing EPTPs for
Hyper-V's paravirt TLB flushing. If _any_ flush fails, KVM falls back
to a full global flush, i.e. additional flushes are unnecessary (and
will likely fail anyways).
Continue processing the
From: Sean Christopherson
Combine the for-loops for Hyper-V TLB EPTP checking and flushing, and in
doing so skip flushes for vCPUs whose EPTP matches the target EPTP.
Reviewed-by: Vitaly Kuznetsov
Signed-off-by: Sean Christopherson
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/vmx
From: Sean Christopherson
Fold check_ept_pointer_match() into hv_remote_flush_tlb_with_range() in
preparation for combining the kvm_for_each_vcpu loops of the ==CHECK and
!=MATCH statements.
No functional change intended.
Reviewed-by: Vitaly Kuznetsov
Signed-off-by: Sean Christopherson
From: Sean Christopherson
Capture kvm_vmx in a local variable instead of polluting
hv_remote_flush_tlb_with_range() with to_kvm_vmx(kvm).
No functional change intended.
Reviewed-by: Vitaly Kuznetsov
Signed-off-by: Sean Christopherson
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/vmx
From: Sean Christopherson
Explicitly track the EPTP that is common to all vCPUs instead of
grabbing vCPU0's EPTP when invoking Hyper-V's paravirt TLB flush.
Tracking the EPTP will allow optimizing the checks when loading a new
EPTP and will also allow dropping ept_pointer_match, e.g.
https://lkml.kernel.org/r/20201020215613.8972-1-sean.j.christopher...@intel.com
v1: ???
Sean Christopherson (11):
KVM: x86: Get active PCID only when writing a CR3 value
KVM: VMX: Track common EPTP for Hyper-V's paravirt TLB flush
KVM: VMX: Stash kvm_vmx in a local variable for Hyper-V para
From: Sean Christopherson
Retrieve the active PCID only when writing a guest CR3 value, i.e. don't
get the PCID when using EPT or NPT. The PCID is especially problematic
for EPT as the bits have different meaning, and so the PCID and must be
manually stripped, which is annoying and unnece
On Fri, Mar 05, 2021, Paolo Bonzini wrote:
> On 05/03/21 02:10, Sean Christopherson wrote:
> > Use '0' to denote an invalid pae_root instead of '0' or INVALID_PAGE.
> > Unlike root_hpa, the pae_roots hold permission bits and thus are
> > guaranteed to be n
On Fri, Mar 05, 2021, Paolo Bonzini wrote:
> On 05/03/21 02:10, Sean Christopherson wrote:
> > @@ -5301,6 +5307,22 @@ static int __kvm_mmu_create(struct kvm_vcpu *vcpu,
> > struct kvm_mmu *mmu)
> > for (i = 0; i < 4; ++i)
> > mmu->pae_root[i]
would also be wrong as that wouldn't actually delay delivery
of the IRQ if it is indeed sent via posted interrupt.
Fixes: 010fd37fddf6 ("KVM: LAPIC: Reduce world switch latency caused by
timer_advance_ns")
Cc: sta...@vger.kernel.org
Signed-off-by: Sean Christopherson
---
arch/x86/k
g why
NPT requires a 64-bit kernel or a kernel with PAE enabled.
Opportunistically switch the param to octal permissions.
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/svm/svm.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/arch/x86/kvm/
allocation of pae_root and lm_root means bugs crash the host.
Obviously, KVM could unconditionally allocate the roots, but that's
arguably a worse failure mode as it would potentially corrupt the guest
instead of crashing it.
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c
For clarity, explicitly skip syncing roots if the MMU load failed
instead of relying on the !VALID_PAGE check in kvm_mmu_sync_roots().
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b
Unexport the MMU load and unload helpers now that they are no longer
used (incorrectly) in vendor code.
Opportunistically move the kvm_mmu_sync_roots() declaration into mmu.h,
it should not be exposed to vendor code.
No functional change intended.
Signed-off-by: Sean Christopherson
---
arch
ng
an emulated instruction, nor does queuing a single-step #DB. No other
post-switch side effects exist.
Fixes: 41ab93727467 ("KVM: nVMX: Emulate EPTP switching for the L1 hypervisor")
Cc: sta...@vger.kernel.org
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/vmx/nested.c | 9 ++---
ip an instruction, which would lead to fireworks
if the emulator were invoked without a valid MMU.
Fixes: eb4b248e152d ("kvm: vmx: Support INVPCID in shadow paging mode")
Cc: sta...@vger.kernel.org
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/x86.c | 2 +-
1 file changed, 1 insertion
Don't strip the C-bit from the faulting address on an intercepted #PF,
the address is a virtual address, not a physical address.
Fixes: 0ede79e13224 ("KVM: SVM: Clear C-bit from the page fault address")
Cc: sta...@vger.kernel.org
Cc: Brijesh Singh
Cc: Tom Lendacky
Sign
er.kernel.org
Cc: Brijesh Singh
Cc: Tom Lendacky
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 24 +++-
arch/x86/kvm/svm/svm.c | 7 +--
2 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu
, etc...
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index b82c1b0d6d6e..dbf7f0395e4b 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/ar
guest, in which case KVM uses a direct
mapped MMU even though TDP is disabled.
Fixes: d0ec49d4de90 ("kvm/x86/svm: Support Secure Memory Encryption within KVM")
Cc: sta...@vger.kernel.org
Cc: Brijesh Singh
Cc: Tom Lendacky
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu
PAE roots being leaked, not to mention the above false
positive.
Opportunistically delete a warning on root_hpa being valid, there's
nothing special about 4/5-level shadow pages that warrants a WARN.
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 7 +++
1 file change
Check the validity of the PDPTRs before allocating any of the PAE roots,
otherwise a bad PDPTR will cause KVM to leak any previously allocated
roots.
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff
the guest PDPTR checks fail.
This will be addressed in a future commit.
Cc: Ben Gardon
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 50 +++---
arch/x86/kvm/mmu/tdp_mmu.c | 23 --
2 files changed, 25 insertions(+), 48 deletions(-
, and thus avoid having to deal with failure in the middle of
root allocation.
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 84 +++---
1 file changed, 54 insertions(+), 30 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu
ssues will be fixed in future commits.
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 64 --
1 file changed, 31 insertions(+), 33 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index c4f8e59f596c..7cb5fb5d2d4d 10
Grab 'mmu' and do s/vcpu->arch.mmu/mmu to shorten line lengths and yield
smaller diffs when moving code around in future cleanup without forcing
the new code to use the same ugly pattern.
No functional change intended.
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/m
32-bit NPT")
Cc: sta...@vger.kernel.org
Reviewed-by: Ben Gardon
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 44 --
1 file changed, 29 insertions(+), 15 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 0987cc1d
")
Cc: sta...@vger.kernel.org
Signed-off-by: Sean Christopherson
---
arch/x86/kvm/mmu/mmu.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index c462062d36aa..0987cc1d53eb 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++
in make_mmu_pages_available() since the
final check wouldn't actually guarnatee 4 pages were "available".
Instead, add a comment about the limit being soft.
v1:
- https://lkml.kernel.org/r/20210302184540.2829328-1-sea...@google.com
Sean Christopherson (17):
KVM: nSVM: Se
On Thu, Mar 04, 2021, Xu, Like wrote:
> On 2021/3/4 1:26, Sean Christopherson wrote:
> > On Wed, Mar 03, 2021, Like Xu wrote:
> > > New VMX controls bits for Arch LBR are added. When bit 21 in vmentry_ctrl
> > > is set, VM entry will write the value from the "Guest
On Thu, Mar 04, 2021, Yang Weijiang wrote:
> @@ -3375,6 +3391,12 @@ enum nvmx_vmentry_status
> nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
> if (kvm_mpx_supported() &&
> !(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
> vmx->nested.vmcs01_guest_bnd
On Thu, Mar 04, 2021, Like Xu wrote:
> On 2021/3/4 2:03, Sean Christopherson wrote:
> > if (vmx_umip_emulated())
> > kvm_cpu_cap_set(X86_FEATURE_UMIP);
> >
> > /* CPUID 0xD.1 */
> > - supported_xss = 0;
>
On Thu, Mar 04, 2021, Xu, Like wrote:
> On 2021/3/4 1:19, Sean Christopherson wrote:
> > > @@ -4463,6 +4470,8 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu,
> > > bool init_event)
> > > vmcs_writel(GUEST_SYSENTER_ESP, 0);
>
On Thu, Mar 04, 2021, Xu, Like wrote:
> Hi Sean,
>
> Thanks for your detailed review on the patch set.
>
> On 2021/3/4 0:58, Sean Christopherson wrote:
> > On Wed, Mar 03, 2021, Like Xu wrote:
> > > @@ -348,10 +352,26 @@ static bool intel_pmu_handle_lbr_msrs_acces
On Wed, Mar 03, 2021, Like Xu wrote:
> This unit-test is intended to test the KVM's support for the
> Architectural LBRs which is a Architectural performance monitor
> unit (PMU) feature on Intel processors.
These really need negative testing, especially on the MSR values. IMO, negative
tests sho
On Wed, Mar 03, 2021, Like Xu wrote:
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 034708a3df20..ec4593e0ee6d 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -7268,6 +7268,8 @@ static __init void vmx_set_cpu_caps(void)
> supported_xss = 0;
>
On Wed, Mar 03, 2021, Sean Christopherson wrote:
> On Wed, Mar 03, 2021, Like Xu wrote:
> > If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, then KVM supports Arch
> > LBRs and CPUID leaf 01CH indicates details of the Arch LBRs capabilities.
> > Currently, KVM only supports
On Wed, Mar 03, 2021, Like Xu wrote:
> If CPUID.(EAX=07H, ECX=0):EDX[19] is set to 1, then KVM supports Arch
> LBRs and CPUID leaf 01CH indicates details of the Arch LBRs capabilities.
> Currently, KVM only supports the current host LBR depth for guests,
> which is also the maximum supported depth
On Wed, Mar 03, 2021, Like Xu wrote:
> New VMX controls bits for Arch LBR are added. When bit 21 in vmentry_ctrl
> is set, VM entry will write the value from the "Guest IA32_LBR_CTL" guest
> state field to IA32_LBR_CTL. When bit 26 in vmexit_ctrl is set, VM exit
> will clear IA32_LBR_CTL after the
On Wed, Mar 03, 2021, Like Xu wrote:
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index 25d620685ae7..d14a14eb712d 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -19,6 +19,7 @@
> #include "pmu.h"
>
> #define MSR_PMC_FULL_WID
On Wed, Mar 03, 2021, Like Xu wrote:
> @@ -348,10 +352,26 @@ static bool intel_pmu_handle_lbr_msrs_access(struct
> kvm_vcpu *vcpu,
> return true;
> }
>
> +/*
> + * Check if the requested depth values is supported
> + * based on the bits [0:7] of the guest cpuid.1c.eax.
> + */
> +static bo
On Wed, Mar 03, 2021, Like Xu wrote:
> Starting from v5.12, KVM reports guest LBR and extra_regs
> support when the host has relevant support.
>
> Cc: Peter Zijlstra
> Reviewed-by: Kan Liang
> Signed-off-by: Like Xu
> ---
> arch/x86/events/intel/core.c | 2 +-
> 1 file changed, 1 insertion(+),
On Tue, Mar 02, 2021, Ben Gardon wrote:
> > @@ -3241,16 +3237,10 @@ static int mmu_alloc_direct_roots(struct kvm_vcpu
> > *vcpu)
> >
> > if (is_tdp_mmu_enabled(vcpu->kvm)) {
> > root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
> > -
> > - if (!VALID_PAGE(root))
> >
On Wed, Mar 03, 2021, Wanpeng Li wrote:
> > Side topic, I think there's a theoretical bug where KVM could inject a
> > spurious
> > timer interrupt. If KVM is using hrtimer, the hrtimer expires early due to
> > an
> > overzealous timer_advance_ns, and the guest writes MSR_TSCDEADLINE after the
>
-off-by: Babu Moger
Cc: sta...@vger.kernel.org
The bug goes back too far to have a meaningful Fixes.
Reviewed-by: Sean Christopherson
On a related topic, I think we can clean up the RESET/INIT flows by hoisting the
common code into kvm_vcpu_reset(). That would also provide good motivation
On Wed, Jan 27, 2021, Paolo Bonzini wrote:
> On 27/10/20 22:23, Sean Christopherson wrote:
> > Clean up KVM's PV TLB flushing when running with EPT on Hyper-V, i.e. as
> > a nested VMM. No real goal in mind other than the sole patch in v1, which
> > is a minor change to
Don't strip the C-bit from the faulting address on an intercepted #PF,
the address is a virtual address, not a physical address.
Fixes: 0ede79e13224 ("KVM: SVM: Clear C-bit from the page fault address")
Cc: sta...@vger.kernel.org
Cc: Brijesh Singh
Cc: Tom Lendacky
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