[PATCH V4 3/4] spi: tegra114: add support for HW CS timing

This patch implements set_cs_timing SPI controller method to allow SPI client driver to configure device specific SPI CS timings. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 48 -- 1 file changed, 46 insertions(+), 2 deletions

[PATCH V4 1/4] spi: tegra114: add support for gpio based CS

This patch adds support for GPIO based CS control through SPI core function spi_set_cs. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index b1f31bb16659

[PATCH V4 4/4] spi: tegra114: add support for TX and RX trimmers

configuring TX and RX clock delay trimmers through the device tree properties. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 69 -- 1 file changed, 67 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers

RE: [PATCH V3 5/9] spi: export spi core function spi_set_cs

> On Mon, Apr 29, 2019 at 10:02:46PM +0000, Sowjanya Komatineni wrote: > > Please fix your mail client to word wrap within paragraphs at something > substantially less than 80 columns. Doing this makes your messages much > easier to read and reply to. > > > > On

RE: [PATCH V3 5/9] spi: export spi core function spi_set_cs

> On Mon, Apr 15, 2019 at 02:30:30PM -0700, Sowjanya Komatineni wrote: > > This patch exports spi_set_cs of the spi core to allow SPI masters to > > use when gpio based chip select is needed. > > This isn't really what I meant when I said it'd be good to use the co

RE: Applied "spi: tegra114: fix PIO transfer" to the spi tree

any relevant lists and maintainers to the CCs when replying to > this mail. > > Thanks, > Mark > > From 3f6e3f7843a6a1667ed890ca51a1388fc7bf3429 Mon Sep 17 00:00:00 2001 > From: Sowjanya Komatineni > Date: Mon, 15 Apr 2019 14:30:26 -0700 > Subject: [PATCH] spi: tegra114

RE: [PATCH V3 3/9] spi: add SPI_LSBYTE_FIRST mode

> On Mon, Apr 15, 2019 at 02:30:28PM -0700, Sowjanya Komatineni wrote: > > Some SPI slaves expect bytes to be in least significant first order > > and some expects most significant first oder. > > > > This patch adds support for requesting SPI master controllers for

[PATCH V3 1/9] spi: tegra114: fix PIO transfer

This patch fixes PIO mode transfer to use PIO bit in SPI_COMMAND1 register. Current driver uses DMA_EN instead of PIO bit. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b

[PATCH V3 4/9] spi: tegra114: add support for Tegra SPI LSBYTE_FIRST

Tegra SPI master controller supports configuring least significant first byte order or most significant first byte order for transfers. This patch adds SPI_LSBYTE_FIRST to supported mode list and also configures byte order based on the mode request for transfer. Signed-off-by: Sowjanya

[PATCH V3 7/9] spi: tegra114: add support for hw based cs

only for single transfers without cs_change request. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 39 +++ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index

[PATCH V3 9/9] spi: tegra114: add support for TX and RX trimmers

configuring TX and RX clock delay trimmers through the device tree properties. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 68 +- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers

[PATCH V3 8/9] spi: tegra114: add support for HW CS timing

This patch implements set_cs_timing SPI controller method to allow SPI client driver to configure device specific SPI CS timings. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 48 -- 1 file changed, 46 insertions(+), 2 deletions

[PATCH V3 6/9] spi: tegra114: add support for gpio based CS

This patch adds support for GPIO based CS control through SPI core function spi_set_cs. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index f4e39eb3857c

[PATCH V3 5/9] spi: export spi core function spi_set_cs

This patch exports spi_set_cs of the spi core to allow SPI masters to use when gpio based chip select is needed. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi.c | 3 ++- include/linux/spi/spi.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi.c

[PATCH V3 0/9] bug fixes and more features to Tegra SPI

setup, hold and inactive delay timing configuration. - Fixed HW based CS decision to be based on single transfer and cs_change. Remove selection of HW based CS through DT. Sowjanya Komatineni (9): spi: tegra114: fix PIO transfer spi: expand mode support spi: add

[PATCH V3 2/9] spi: expand mode support

This patch changes mode and mode_bits from u16 to u32 to allow more mode configurations. Signed-off-by: Sowjanya Komatineni --- include/linux/spi/spi.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 589f9dc9ac2b

[PATCH V3 3/9] spi: add SPI_LSBYTE_FIRST mode

Some SPI slaves expect bytes to be in least significant first order and some expects most significant first oder. This patch adds support for requesting SPI master controllers for least significant first order using SPI_LSBYTE_FIRST mode. Signed-off-by: Sowjanya Komatineni --- drivers/spi

RE: [PATCH V2 11/20] spi: expand mode support and add LSBYTE_FIRST mode

> On Thu, Apr 04, 2019 at 05:14:10PM -0700, Sowjanya Komatineni wrote: > > Some SPI Master controllers support configuring Least significant byte > > first or Most significant byte first order for transfers. Also some > > SPI slave devices expect bytes to be in Least si

RE: [PATCH V3 05/10] arm64: tegra: fix default tap and trim values

> On Mon, 1 Apr 2019 at 19:43, Sowjanya Komatineni > wrote: > > > > > > > > > > > > Default tap and trim values are incorrect for Tegra186 SDMMC4. > > > > > This patch fixes it. > > > > > > > > > > Tested-by:

[PATCH V1 1/2] arm64: tegra: fix default tap and trim values

Default tap and trim values are incorrect for Tegra186 SDMMC4. This patch fixes it. Tested-by: Jon Hunter Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186

[PATCH V1 2/2] arm64: tegra: enable command queue for tegra186 sdmmc4

This patch enables command queue support for Tegra186 SDMMC4. Tested-by: Jon Hunter Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia

[PATCH V4] mmc: tegra: add sdhci tegra suspend and resume

This patch adds suspend and resume PM ops for tegra SDHCI. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 58 +- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci

[PATCH V2 03/20] spi: tegra114: de-assert CS before SPI mode change

. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 22 -- 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 3042521c3785..c60e40cab0a0 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers

[PATCH V2 04/20] spi: tegra114: avoid reset call in atomic context

This patch moves SPI controller reset out of spin lock. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index c60e40cab0a0..d928a2c92a3d 100644

[PATCH V2 10/20] Documentation: devicetree: spi: add spi-lsbyte-first propery

spi-lsbyte-first optional property allows SPI slaves to choose byte order of little endian for transfers. Signed-off-by: Sowjanya Komatineni --- Documentation/devicetree/bindings/spi/spi-bus.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/spi

[PATCH V2 07/20] spi: tegra114: set bus number based on id

This patch sets SPI device id from the device tree as the bus number. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 191233eae149..58f5059b339f 100644 --- a

[PATCH V2 02/20] spi: tegra114: use unpacked mode for below 4 bytes

Packed mode expects minimum transfer length of 4 bytes. This patch fixes this by using unpacked mode for transfers less than 4 bytes. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114

[PATCH V2 12/20] spi: tegra114: add support for LSBYTE_FIRST

Some SPI devices expects SPI transfers to be in Least significant byte first order and some devices expect Most significant byte first order. This patch adds SPI_LSBYTE_FIRST to the supported SPI mode list and also configures Tegra SPI controller accordingly. Signed-off-by: Sowjanya Komatineni

[PATCH V2 11/20] spi: expand mode support and add LSBYTE_FIRST mode

: Sowjanya Komatineni --- drivers/spi/spi.c | 5 - include/linux/spi/spi.h | 7 --- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index bd2a424672df..97ce047a776b 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1638,6

[PATCH V2 13/20] spi: tegra114: add support for interrupt mask

interrupts while Tegra124 and prior uses interrupt enable bits in SPI_DMA_CTL register. This patch creates flag has_intr_mask_reg in tegra_spi_soc_data to identify this and implements accordingly. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 53

[PATCH V2 16/20] spi-summary: document set_cs_timing

This patch documents set_cs_timing SPI master method. Signed-off-by: Sowjanya Komatineni --- Documentation/spi/spi-summary | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/spi/spi-summary b/Documentation/spi/spi-summary index 1721c1b570c3..1a63194b74d7 100644 --- a

[PATCH V2 14/20] spi: tegra114: add support for gpio based cs

This patch adds supports for chip select control using GPIO if valid CS gpio exists. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 59 ++ 1 file changed, 59 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi

[PATCH V2 09/20] spi: tegra114: add 3 wire transfer mode support

This patch adds 3 wire transfer support to SPI mode list along with its implementation. 3 wire or Bi-directional mode uses only one serial data pin for the transfer. SPI in master mode uses MOSI data line only and MISO data line is not used. Signed-off-by: Sowjanya Komatineni --- drivers/spi

[PATCH V2 18/20] spi: tegra114: add support for HW CS timing

This patch implements set_cs_timing SPI controller method to allow SPI client driver to configure device specific SPI CS timings. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 48 -- 1 file changed, 46 insertions(+), 2 deletions

[PATCH V2 17/20] spi: add a method for configuring CS timing

inactive delay. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi.c | 15 +++ include/linux/spi/spi.h | 15 +++ 2 files changed, 30 insertions(+) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 97ce047a776b..0f92329e990f 100644 --- a/drivers/spi/spi.c

[PATCH V2 20/20] spi: tegra114: add support for tuning TX and RX trimmers

platform design for each of the slaves on the SPI bus. This patch adds support for configuring TX/RX clock delays specified through device tree properties. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 63 +- 1 file changed, 62

[PATCH V2 19/20] DT bindings: spi: document tx/rx clock delay properties

Tegra SPI controller has TX and RX trimmers to tuning the delay of SPI master clock with respect to the data. TX and RX tap values are based on the platform validation across the PVT and the trimmer values vary based on the trace lengths to the corresponding SPI devices. Signed-off-by: Sowjanya

[PATCH V2 01/20] spi: tegra114: fix PIO transfer

This patch fixes PIO mode transfer to use PIO bit in SPI_COMMAND1 register. Current driver uses DMA_EN instead of PIO bit. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b

[PATCH V2 06/20] spi: tegra114: set supported bits per word

Tegra SPI supports 4 through 32 bits per word. This patch sets bits_per_word_mask accordingly to support transfer with these bits per word. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers

[PATCH V2 15/20] spi: tegra114: add support for hw based cs

only for single transfers without cs_change request. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 38 ++ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index

[PATCH V2 08/20] spi: tegra114: add dual mode support

and MISO lines. Even bits are transmitted or received on the MOSI data line and odd bits are transmitted or received on the MISO data line. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi

[PATCH V2 05/20] spi: tegra114: dump SPI registers during timeout

This patch dumps SPI registers on transfer error or timeout for debug purpose. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index d928a2c92a3d

[PATCH V3] mmc: tegra: add sdhci tegra suspend and resume

This patch adds suspend and resume PM ops for tegra SDHCI. Acked-by: Thierry Reding Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 56 +- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci

RE: [PATCH V1 21/26] DT bindings: spi: add tx/rx clock delay SPI client properties

> On Tue, Mar 26, 2019 at 10:56:42PM -0700, Sowjanya Komatineni wrote: > > This patch adds Tegra SPI master tx and rx clock delay properties. > > > > TX/RX clock delays may vary depending on the platform design trace > > lengths for each client on the Tegra SPI

[PATCH V2] mmc: tegra: add sdhci tegra suspend and resume

This patch adds suspend and resume PM ops for tegra SDHCI. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 56 +- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci

RE: [PATCH V1] mmc: tegra: add sdhci tegra suspend and resume

> On Mon, Apr 01, 2019 at 10:27:33PM -0700, Sowjanya Komatineni wrote: > > This patch adds suspend and resume PM ops for tegra SDHCI. > > > > Signed-off-by: Sowjanya Komatineni > > --- > > drivers/mmc/host/sdhci-tegra.c | 45 > > +++

[PATCH V1] mmc: tegra: add sdhci tegra suspend and resume

This patch adds suspend and resume PM ops for tegra SDHCI. Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 45 +- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci

RE: [PATCH V1 18/26] spi: tegra114: add support for hw based cs

> On Tue, Mar 26, 2019 at 10:56:39PM -0700, Sowjanya Komatineni wrote: > > > Tegra SPI driver default uses SW CS control for transfers and HW CS > > control can be enabled through SPI client device node DT property > > nvidia,enable-hw-based-cs and is used only for s

RE: [PATCH V1 04/26] spi: tegra114: use packed mode for 32 bits per word

> On Tue, Mar 26, 2019 at 10:56:25PM -0700, Sowjanya Komatineni wrote: > > Fixes: Use packed mode for 32 bits per word transfers to increase > > performance as each packet is a full 32-bit word. > > This is an optimization rather than a bug fix, ideally it should be late

RE: [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default

> On Tue, Mar 26, 2019 at 10:56:45PM -0700, Sowjanya Komatineni wrote: > > With SW CS, during transfer completion CS is de-asserted by writing > > the default command1 register value to SPI_COMMAND1 register. With > > this both mode and CS state are set at the sam

RE: [PATCH V1 19/26] DT bindings: spi: add spi client device properties

> On Tue, Mar 26, 2019 at 10:56:40PM -0700, Sowjanya Komatineni wrote: > > This patch adds below cs timing properties to allow SPI master > > configuring setup, hold and time interval between two SPI transactions > > to meet specific SPI client device requirements. >

RE: [PATCH V3 05/10] arm64: tegra: fix default tap and trim values

> > > > > > Default tap and trim values are incorrect for Tegra186 SDMMC4. > > > This patch fixes it. > > > > > > Tested-by: Jon Hunter > > > Signed-off-by: Sowjanya Komatineni > > > > Is this a fix and/or for stable? > >

[PATCH V1 03/26] spi: tegra114: fix for unpacked mode transfers

computation of the actual bytes to fill in FIFO during transmit and the actual bytes to read from FIFO during receive ignoring 0 padded bytes. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 43 --- 1 file changed, 36 insertions(+), 7 deletions

[PATCH V1 11/26] spi: tegra114: reset controller on probe

Fixes: SPI driver can be built as module so perform SPI controller reset on probe to make sure it is in valid state before initiating transfer. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 32 ++-- 1 file changed, 18 insertions(+), 14 deletions

[PATCH V1 06/26] spi: tegra114: terminate dma and reset on transfer timeout

Fixes: terminate DMA and perform controller reset on transfer timeout to clear the FIFO's and errors. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c

[PATCH V1 10/26] spi: tegra114: avoid reset call in atomic context

Fixes: move SPI controller reset out of spin lock. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 268a790a663e..5523936b21f5 100644 --- a

[PATCH V1 05/26] spi: tegra114: use unpacked mode for below 4 byte transfers

Fixes: use unpacked mode when transfer length is less than 4 bytes. Packed mode expects minimum transfer length of 4 bytes. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b

[PATCH V1 09/26] spi: tegra114: dump SPI registers during timeout

This patch dumps SPI registers on DMA or transfer timeout for debug purpose. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index b7e71676a506

[PATCH V1 12/26] spi: tegra114: add SPI_LSB_FIRST support

Tegra SPI controller supports lsb first mode. Default is MSB bit first and on selection of SPI_LSB_FIRST through SPI mode transmission happens with LSB bit first. This patch adds SPI_LSB_FIRST flag to mode_bits and also configures it on request. Signed-off-by: Sowjanya Komatineni --- drivers

[PATCH V1 17/26] spi: tegra114: add support for interrupt mask

interrupts while Tegra124 and prior uses interrupt enable bits in SPI_DMA_CTL register. This patch creates flag has_intr_mask_reg in tegra_spi_soc_data to identify this and implements accordingly. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 53

[PATCH V1 14/26] spi: tegra114: add 3 wire transfer mode support

This patch adds 3 wire transfer support to SPI mode list and also implements it. 3 wire or Bi-directional mode uses only one serial data pin for the transfer. SPI in master mode uses MOSI data line only and MISO data line is not used by the SPI. Signed-off-by: Sowjanya Komatineni --- drivers

[PATCH V1 19/26] DT bindings: spi: add spi client device properties

8vlhV96anQSaGkioOUTp8ThlHSwBKLRFHRofVlrhT53K0xvTCvVst4aHvA1aq3QPw0 sVr25yohIPq7w== Signed-off-by: Sowjanya Komatineni --- Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt | 7 +++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree

[PATCH V1 20/26] spi: tegra114: add support for tuning HW CS timing

properties. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 61 +++--- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 86c34f02d13a..e01962344bde 100644 --- a/drivers

[PATCH V1 21/26] DT bindings: spi: add tx/rx clock delay SPI client properties

This patch adds Tegra SPI master tx and rx clock delay properties. TX/RX clock delays may vary depending on the platform design trace lengths for each client on the Tegra SPI bus. These properties helps to tune the clock delays. Signed-off-by: Sowjanya Komatineni --- .../devicetree/bindings

[PATCH V1 23/26] spi: tegra114: add support for gpio based cs

This patch adds supports for chip select control using GPIO if valid CS gpio exists rather than controlling from the SPI controller. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 57 ++ 1 file changed, 57 insertions(+) diff

[PATCH V1 26/26] spi: tegra114: add support for LSBYTE_FIRST

Some SPI devices expects SPI transfers to be in Least significant byte first order and some devices expect Most significant byte first order. This patch adds SPI_LSBYTE_FIRST to supported mode list and implements configuration accordingly. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi

[PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default

. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 9b216e9d6079..e1669ab3b0fe 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c

[PATCH V1 25/26] spi: expand mode and mode_bits support

devices expect bytes to be in Least significant first order and some devices expect Most significant first order. This patch creates SPI_LSBYTE_FIRST mode for this purpose. Signed-off-by: Sowjanya Komatineni --- include/linux/spi/spi.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions

[PATCH V1 13/26] spi: tegra114: add dual mode support

and MISO lines. Even bits are transmitted or received on the MOSI data line and odd bits are transmitted or received on the MISO data line. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi

[PATCH V1 18/26] spi: tegra114: add support for hw based cs

only for single transfers. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 71 +- 1 file changed, 64 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 68fee474580b..86c34f02d13a

[PATCH V1 15/26] spi: tegra114: set supported bits_per_word

Tegra SPI supports 4 through 32 bits per word. This patch sets bits_per_word_mask accordingly to support transfer with these bits per word. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers

[PATCH V1 22/26] spi: tegra114: add support for tuning clock delay

platform design for each of the slaves on the SPI bus. This patch adds support for configuring TX/RX clock delays specified through device tree properties. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 27 ++- 1 file changed, 26 insertions(+), 1 deletion

[PATCH V1 16/26] spi: tegra114: set bus number based on id

This patch sets the SPI device id from the device tree as the bus number. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 94acef0f5ea5..9b9d4b9e1f3e 100644

[PATCH V1 08/26] spi: tegra114: configure dma burst size to fifo trig level

Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels to avoid mismatch. SPI FIFO trigger levels are calculated based on the transfer length. So this patch moves DMA slave configuration to happen before start of DMAs. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi

[PATCH V1 07/26] spi: tegra114: flush fifos

Fixes: Flush TX and RX FIFOs before start of new transfer and on FIFO overflow or underrun errors. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 39 ++- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi

[PATCH V1 01/26] spi: tegra114: fix PIO transfer

Fixes: Use PIO bit in SPI_COMMAND1 register for PIO mode. Current driver uses DMA_EN instead of PIO bit. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi

[PATCH V1 02/26] spi: tegra114: clear packed bit for unpacked mode

Fixes: Clear packed bit when not using packed mode. Packed bit is not cleared when not using packed mode. This results in transfer timeouts for the unpacked mode transfers followed by the packed mode transfers. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 2 ++ 1 file

[PATCH V1 04/26] spi: tegra114: use packed mode for 32 bits per word

Fixes: Use packed mode for 32 bits per word transfers to increase performance as each packet is a full 32-bit word. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi

RE: [PATCH] spi: tegra20-slink: change chip select action order

et, removing the > > spike. > > > > Signed-off-by: Randolph Maaßen Very minor typo in the comment below: Fix looks good as chip select need to be selected prior to asserting during start of transfer. Reviewed-by: Sowjanya Komatineni > > --- > > drivers/spi/spi-te

RE: [PATCH V3 01/10] mmc: tegra: fix ddr signaling for non-ddr modes

ches from HS400 to HS > > DDR and then from HS DDR to HS mode and then to HS200. > > > > This patch fixes the ddr_signaling to set properly for non DDR modes. > > > > Tested-by: Jon Hunter > > Acked-by: Adrian Hunter > > Signed-off-by: Sowjanya Komatineni

[PATCH V4 05/10] arm64: tegra: fix default tap and trim values

Default tap and trim values are incorrect for Tegra186 SDMMC4. This patch fixes it. Tested-by: Jon Hunter Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186

[PATCH V4 10/10] arm64: tegra: enable command queue for tegra186 sdmmc4

This patch enables command queue support for Tegra186 SDMMC4. Tested-by: Jon Hunter Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia

[PATCH V4 09/10] mmc: tegra: fix CQE enable and resume sequence

sandisk emmc device when status command is sent during the transfer of last data block due to marginal timing. Tested-by: Jon Hunter Acked-by: Adrian Hunter Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 72 -- 1 file changed, 62

[PATCH V4 03/10] mmc: tegra: update hw tuning process

Hunter Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 216 - 1 file changed, 215 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 46086dd43bfb..f1aa0591112a 100644 --- a

[PATCH V4 06/10] mmc: cqhci: allow hosts to update dcmd cmd desc

This patch adds update_dcmd_desc interface to cqhci_host_ops to allow hosts to update any of the DCMD task descriptor attributes and parameters. Tested-by: Jon Hunter Reviewed-by: Ritesh Harjani Signed-off-by: Sowjanya Komatineni --- [V4]: Minor fix of missing declaration of mmc_request

[PATCH V4 08/10] mmc: cqhci: add CQHCI_SSC1 register CBC field mask

This patch adds define for CBC field mask of the register CQHCI_SSC1. Tested-by: Jon Hunter Acked-by: Adrian Hunter Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/cqhci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index

[PATCH V4 07/10] mmc: tegra: add Tegra186 WAR for CQE

and also implements update_dcmd_desc of cqhci_host_ops interface to set CMD_TIMING bit depending on the NVQUIRK. Tested-by: Jon Hunter Reviewed-by: Ritesh Harjani Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 17 - 1 file changed, 16 insertions(+), 1

[PATCH V4 02/10] mmc: sdhci: allow host to specify maximum tuning loops

Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci.c | 5 +++-- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index a8141ff9be03..bbc0e0bb7128 100644 --- a/drivers/mmc/host/sdhci.c +++ b

[PATCH V4 01/10] mmc: tegra: fix ddr signaling for non-ddr modes

mode and then to HS200. This patch fixes the ddr_signaling to set properly for non DDR modes. Tested-by: Jon Hunter Acked-by: Adrian Hunter Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b

[PATCH V4 04/10] dt-bindings: mmc: tegra: document Tegra194 compatible string

SDHCI controller of Tegra194 is similar to SDHCI controller in Tegra186. This patch documents Tegra194 sdhci compatible string. Signed-off-by: Sowjanya Komatineni --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation

RE: [PATCH V3 01/10] mmc: tegra: fix ddr signaling for non-ddr modes

tches from HS400 to HS DDR and then > > from HS DDR to HS mode and then to HS200. > > > > This patch fixes the ddr_signaling to set properly for non DDR modes. > > > > Tested-by: Jon Hunter > > Acked-by: Adrian Hunter > > Signed-off-by: Sowjanya Komatineni

RE: [PATCH V3 05/10] arm64: tegra: fix default tap and trim values

> > > > Default tap and trim values are incorrect for Tegra186 SDMMC4. > > This patch fixes it. > > > > Tested-by: Jon Hunter > > Signed-off-by: Sowjanya Komatineni > > Is this a fix and/or for stable? > > In either case, I am leaving this for arm-

[PATCH V3 07/10] mmc: tegra: add Tegra186 WAR for CQE

and also implements update_dcmd_desc of cqhci_host_ops interface to set CMD_TIMING bit depending on the NVQUIRK. Tested-by: Jon Hunter Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 17 - 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a

[PATCH V3 06/10] mmc: cqhci: allow hosts to update dcmd cmd desc

This patch adds update_dcmd_desc interface to cqhci_host_ops to allow hosts to update any of the DCMD task descriptor attributes and parameters. Tested-by: Jon Hunter Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/cqhci.c | 2 ++ drivers/mmc/host/cqhci.h | 2 ++ 2 files changed, 4

[PATCH V3 02/10] mmc: sdhci: allow host to specify maximum tuning loops

Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci.c | 5 +++-- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index a8141ff9be03..bbc0e0bb7128 100644 --- a/drivers/mmc/host/sdhci.c +++ b

[PATCH V3 04/10] dt-bindings: mmc: tegra: document Tegra194 compatible string

SDHCI controller of Tegra194 is similar to SDHCI controller in Tegra186. This patch documents Tegra194 sdhci compatible string. Signed-off-by: Sowjanya Komatineni --- Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation

[PATCH V3 05/10] arm64: tegra: fix default tap and trim values

Default tap and trim values are incorrect for Tegra186 SDMMC4. This patch fixes it. Tested-by: Jon Hunter Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186

[PATCH V3 08/10] mmc: cqhci: add CQHCI_SSC1 register CBC field mask

This patch adds define for CBC field mask of the register CQHCI_SSC1. Tested-by: Jon Hunter Acked-by: Adrian Hunter Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/cqhci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index

[PATCH V3 10/10] arm64: tegra: enable command queue for tegra186 sdmmc4

This patch enables command queue support for Tegra186 SDMMC4. Tested-by: Jon Hunter Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia

[PATCH V3 09/10] mmc: tegra: fix CQE enable and resume sequence

sandisk emmc device when status command is sent during the transfer of last data block due to marginal timing. Tested-by: Jon Hunter Acked-by: Adrian Hunter Signed-off-by: Sowjanya Komatineni --- drivers/mmc/host/sdhci-tegra.c | 72 -- 1 file changed, 62

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