Hi,
Kindly review the patch.
Thanks
Srikanth
On Tue, Nov 18, 2014 at 10:09 AM, Srikanth Thokala
wrote:
> In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
> match the sequence of events described below it. To match the
> sequence of events, the values of 'A' and '
Hi,
Kindly review the patch.
Thanks
Srikanth
On Tue, Nov 18, 2014 at 10:09 AM, Srikanth Thokala
sriku.li...@gmail.com wrote:
In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
match the sequence of events described below it. To match the
sequence of events, the values
In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
match the sequence of events described below it. To match the
sequence of events, the values of 'A' and 'B' should be loaded
into 'x' and 'y' respectively.
Signed-off-by: Srikanth Thokala
---
Documentation/memory-barriers.txt
In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
match the sequence of events described below it. To match the
sequence of events, the values of 'A' and 'B' should be loaded
into 'x' and 'y' respectively.
Signed-off-by: Srikanth Thokala sriku.li...@gmail.com
---
Documentation
Hi,
On Wed, Nov 12, 2014 at 12:26 PM, Srikanth Thokala
wrote:
> Hi,
>
> On Wed, Nov 12, 2014 at 12:47 AM, wrote:
>> From: Suravee Suthikulpanit
>>
>> This patch introduces a new DT binding, msi-parent, which can
>> be used to specify MSI-parent phandle for
Hi,
On Wed, Nov 12, 2014 at 12:47 AM, wrote:
> From: Suravee Suthikulpanit
>
> This patch introduces a new DT binding, msi-parent, which can
> be used to specify MSI-parent phandle for a particular PCI
> generic host controller.
>
> Also, it implements and registers set_msi_parent callback.
>
Hi,
On Wed, Nov 12, 2014 at 12:47 AM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch introduces a new DT binding, msi-parent, which can
be used to specify MSI-parent phandle for a particular PCI
generic host controller.
Also, it
Hi,
On Wed, Nov 12, 2014 at 12:26 PM, Srikanth Thokala
sriku.li...@gmail.com wrote:
Hi,
On Wed, Nov 12, 2014 at 12:47 AM, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch introduces a new DT binding, msi-parent, which can
be used
Hi Quentin,
On Fri, Nov 7, 2014 at 1:36 PM, Quentin Lambert
wrote:
> Simplify a trivial if-return sequence. Possibly combine with a
> preceding function call.
> Generated by: scripts/coccinelle/misc/simple_return.cocci
>
> Signed-off-by: Quentin Lambert
> ---
>
> Changes in v2:
> - remove a
Hi Quentin,
On Fri, Nov 7, 2014 at 1:36 PM, Quentin Lambert
lambert.quen...@gmail.com wrote:
Simplify a trivial if-return sequence. Possibly combine with a
preceding function call.
Generated by: scripts/coccinelle/misc/simple_return.cocci
Signed-off-by: Quentin Lambert
Hi Mark,
Thanks for reviewing patch.
I should have made a note that the binding patch is applied. I will
make a note of this and add to next versions.
Thanks
Srikanth
On Wed, Oct 15, 2014 at 6:15 PM, Mark Rutland wrote:
> Hi,
>
> On Wed, Oct 15, 2014 at 01:00:36PM +0100, Srikant
-by: Srikanth Thokala
---
Changes in v4:
- Add direction field to VDMA descriptor structure and removed from
channel structure to avoid duplication.
- Check for DMA idle condition before changing the configuration.
- Residue is being calculated in complete_descriptor() and is reported
to slave driver
-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v4:
- Add direction field to VDMA descriptor structure and removed from
channel structure to avoid duplication.
- Check for DMA idle condition before changing the configuration.
- Residue is being calculated in complete_descriptor() and is reported
, Srikanth Thokala wrote:
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type target peripherals.
This module works on Zynq (ARM Based SoC) and Microblaze platforms
Hi Vinod,
On Tue, Sep 9, 2014 at 9:27 PM, Vinod Koul wrote:
> On Tue, Sep 09, 2014 at 12:52:16AM +0530, Srikanth Thokala wrote:
>> Hi Vinod,
>>
>> On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul wrote:
>> > On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth
Hi Vinod,
On Tue, Sep 9, 2014 at 9:27 PM, Vinod Koul vinod.k...@intel.com wrote:
On Tue, Sep 09, 2014 at 12:52:16AM +0530, Srikanth Thokala wrote:
Hi Vinod,
On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul vinod.k...@intel.com wrote:
On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth Thokala
Hi Vinod,
On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul wrote:
> On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth Thokala wrote:
>> Hi Vinod,
>>
>> Apologies for the delay.
>>
>> On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul wrote:
>> > On Mon, Jul 28,
Hi Vinod,
On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul vinod.k...@intel.com wrote:
On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth Thokala wrote:
Hi Vinod,
Apologies for the delay.
On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jul 28, 2014 at 05:47
On Wed, Sep 3, 2014 at 11:35 PM, Bjorn Helgaas wrote:
> On Wed, Aug 20, 2014 at 09:56:02PM +0530, Srikanth Thokala wrote:
>> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>>
>> Signed-off-by: Srikanth Thokala
>> Acked-by: Arnd Bergmann
>
> App
On Wed, Sep 3, 2014 at 11:35 PM, Bjorn Helgaas bhelg...@google.com wrote:
On Wed, Aug 20, 2014 at 09:56:02PM +0530, Srikanth Thokala wrote:
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
Hi Bjorn,
I fixed the mentioned issues with build-bot in v7. Could you please
take this patch?
Thanks
Srikanth
On Wed, Aug 20, 2014 at 9:56 PM, Srikanth Thokala wrote:
> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>
> Signed-off-by: Srikanth Thokala
> Acked-by: A
Hi Vinod,
Apologies for the delay.
On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul wrote:
> On Mon, Jul 28, 2014 at 05:47:49PM +0530, Srikanth Thokala wrote:
>> +struct xilinx_dma_chan {
>> + struct xilinx_dma_device *xdev;
>> + u32 ctrl_offset;
>> + spinl
Hi Vinod,
Apologies for the delay.
On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Jul 28, 2014 at 05:47:49PM +0530, Srikanth Thokala wrote:
+struct xilinx_dma_chan {
+ struct xilinx_dma_device *xdev;
+ u32 ctrl_offset;
+ spinlock_t lock
Hi Bjorn,
I fixed the mentioned issues with build-bot in v7. Could you please
take this patch?
Thanks
Srikanth
On Wed, Aug 20, 2014 at 9:56 PM, Srikanth Thokala stho...@xilinx.com wrote:
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
Acked-by: Arnd Bergmann
---
Changes in v7:
- Removed errors reported from build-bot. The errors are
mainly due to same CONFIG_PCI_XILINX flag being used for
Zynq and Microblaze platforms. So
Hi Bjorn,
On Tue, Aug 19, 2014 at 12:19 AM, Bjorn Helgaas wrote:
> On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote:
>> Hi Michal,
>>
>> On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote:
>> > Hi Bjorn,
>> >
>> > On 07/30/2014
Hi Bjorn,
On Tue, Aug 19, 2014 at 12:19 AM, Bjorn Helgaas bhelg...@google.com wrote:
On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote:
Hi Michal,
On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek mon...@monstr.eu wrote:
Hi Bjorn,
On 07/30/2014 01:24 PM, Srikanth Thokala
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
Changes in v7:
- Removed errors reported from build-bot. The errors are
mainly due to same CONFIG_PCI_XILINX flag being used for
Zynq
Hi Varka Bhadram,
On Tue, Aug 5, 2014 at 5:29 PM, Varka Bhadram wrote:
> On 08/05/2014 05:09 PM, Srikanth Thokala wrote:
>>
>> Device-tree binding documentation of Xilinx Central DMA Engine
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes in v2
Hi Michal,
On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote:
> Hi Bjorn,
>
> On 07/30/2014 01:24 PM, Srikanth Thokala wrote:
>> Hi Arnd,
>>
>> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote:
>>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrot
Hi Michal,
On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek mon...@monstr.eu wrote:
Hi Bjorn,
On 07/30/2014 01:24 PM, Srikanth Thokala wrote:
Hi Arnd,
On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote:
On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
Hi Arnd and Rob
Hi Varka Bhadram,
On Tue, Aug 5, 2014 at 5:29 PM, Varka Bhadram varkabhad...@gmail.com wrote:
On 08/05/2014 05:09 PM, Srikanth Thokala wrote:
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v2:
- Change
) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
---
Changes in v2:
- Rebased on 3.16-rc7.
---
drivers/dma/Kconfig | 12 +
drivers/dma/xilinx/Makefile |1 +
drivers/dma/xilinx/xilinx_cdma.c | 998 ++
include/linux/amba/xilinx_dma.h
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v2:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
---
.../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
Acked-by: Arnd Bergmann
---
NOTE: The AXI PCIe IP doesn't support I/O space, so this
driver has no support for I/O space.
Changes in v6:
- Added Ack from Arnd. Thanks Arnd.
- Rebased on 3.16-rc7
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
NOTE: The AXI PCIe IP doesn't support I/O space, so this
driver has no support for I/O space.
Changes in v6:
- Added Ack from Arnd. Thanks Arnd
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v2:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
---
.../devicetree/bindings/dma/xilinx/xilinx_cdma.txt
) and Microblaze platforms.
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v2:
- Rebased on 3.16-rc7.
---
drivers/dma/Kconfig | 12 +
drivers/dma/xilinx/Makefile |1 +
drivers/dma/xilinx/xilinx_cdma.c | 998 ++
include/linux/amba
Hi,
Kindly review this patch and please provide your inputs.
Thanks
Srikanth
On Mon, Jul 28, 2014 at 5:47 PM, Srikanth Thokala wrote:
> This is the driver for the AXI Direct Memory Access (AXI DMA)
> core, which is a soft Xilinx IP core that provides high-
> bandwidth direct memo
Hi,
Kindly review this patch and please provide your inputs.
Thanks
Srikanth
On Mon, Jul 28, 2014 at 5:47 PM, Srikanth Thokala stho...@xilinx.com wrote:
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct
Hi Arnd,
On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote:
> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
>> Hi Arnd and Rob,
>>
>> I discussed with Bjorn and we believe this patch is in good shape to
>> apply. And Bjorn requires ACKs to apply this pa
Hi Arnd,
On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote:
On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
Hi Arnd and Rob,
I discussed with Bjorn and we believe this patch is in good shape to
apply. And Bjorn requires ACKs to apply this patch. So, could you
guys
On Mon, Jul 28, 2014 at 5:58 PM, Arnd Bergmann wrote:
> On Monday 28 July 2014 17:47:48 Srikanth Thokala wrote:
>> Device-tree binding documentation of Xilinx DMA Engine
>>
>> Signed-off-by: Srikanth Thokala
>
> Looks ok to me,
>
> Acked-by: Arnd
Hi Arnd and Rob,
I discussed with Bjorn and we believe this patch is in good shape to
apply. And Bjorn requires ACKs to apply this patch. So, could you
guys please review this patch and provided your ACKs to this patch.
Thanks
Srikanth
On Wed, Jul 23, 2014 at 9:33 PM, Srikanth Thokala wrote
-by: Srikanth Thokala
---
Changes in v3:
- Rebased on 3.16-rc7
Changes in v2:
- Simplified the logic to set SOP and APP words in prep_slave_sg().
- Corrected function description comments to match the return type.
- Fixed some minor comments as suggested by Andy, Thanks.
---
drivers/dma/Kconfig
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v3:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v3:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx
-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v3:
- Rebased on 3.16-rc7
Changes in v2:
- Simplified the logic to set SOP and APP words in prep_slave_sg().
- Corrected function description comments to match the return type.
- Fixed some minor comments as suggested by Andy, Thanks.
---
drivers/dma
Hi Arnd and Rob,
I discussed with Bjorn and we believe this patch is in good shape to
apply. And Bjorn requires ACKs to apply this patch. So, could you
guys please review this patch and provided your ACKs to this patch.
Thanks
Srikanth
On Wed, Jul 23, 2014 at 9:33 PM, Srikanth Thokala stho
On Mon, Jul 28, 2014 at 5:58 PM, Arnd Bergmann a...@arndb.de wrote:
On Monday 28 July 2014 17:47:48 Srikanth Thokala wrote:
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Looks ok to me,
Acked-by: Arnd Bergmann a...@arndb.de
Hi Andreas,
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Friday, July 25, 2014 3:10 PM
> To: Andreas Färber; mon...@monstr.eu; Srikanth Thokala
> Cc: Vinod Koul; Michal Simek; Andreas Olofsson; Matteo Vit; Sean Rickerd;
> devicet.
Hi Andreas,
-Original Message-
From: Michal Simek [mailto:michal.si...@xilinx.com]
Sent: Friday, July 25, 2014 3:10 PM
To: Andreas Färber; mon...@monstr.eu; Srikanth Thokala
Cc: Vinod Koul; Michal Simek; Andreas Olofsson; Matteo Vit; Sean Rickerd;
devicet...@vger.kernel.org; linux
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up
Hi Bjorn,
On Wed, Jul 16, 2014 at 11:08 PM, Bjorn Helgaas wrote:
> On Thu, Jul 03, 2014 at 09:57:34AM +0530, Srikanth Thokala wrote:
>> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes i
Hi Bjorn,
On Wed, Jul 16, 2014 at 11:08 PM, Bjorn Helgaas bhelg...@google.com wrote:
On Thu, Jul 03, 2014 at 09:57:34AM +0530, Srikanth Thokala wrote:
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v4
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Wednesday, May 21, 2014 1:23 PM
> To: Srikanth Thokala
> Cc: Bjorn Helgaas; will.dea...@arm.com; Michal Simek; linux-
> ker...@vger.kernel.org; linux-...@vger.kernel.org
> Subject: Re:
-Original Message-
From: Arnd Bergmann [mailto:a...@arndb.de]
Sent: Wednesday, May 21, 2014 1:23 PM
To: Srikanth Thokala
Cc: Bjorn Helgaas; will.dea...@arm.com; Michal Simek; linux-
ker...@vger.kernel.org; linux-...@vger.kernel.org
Subject: Re: [PATCH] PCI: Generic Configuration
Hi Arnd,
On Mon, May 19, 2014 at 10:33 PM, Arnd Bergmann wrote:
> On Sunday 18 May 2014 19:38:45 Srikanth Thokala wrote:
>> +
>> + if (cfg->ops->is_valid_cfg_access) {
>> + if (!cfg->ops->is_valid_cfg_access(bus, devfn)) {
>> +
Hi Arnd,
On Mon, May 19, 2014 at 10:33 PM, Arnd Bergmann a...@arndb.de wrote:
On Sunday 18 May 2014 19:38:45 Srikanth Thokala wrote:
+
+ if (cfg-ops-is_valid_cfg_access) {
+ if (!cfg-ops-is_valid_cfg_access(bus, devfn)) {
+ *val = PCI_CFG_INVALID_DEVFN
This patch adds support for a generic CAM and ECAM configuration
space accesses.
Signed-off-by: Srikanth Thokala
---
This patch is created with reference from Will's patch series:
1/3 - "ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM"
2/3 - "PCI: A
This patch adds support for a generic CAM and ECAM configuration
space accesses.
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
This patch is created with reference from Will's patch series:
1/3 - ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM
2/3 - PCI: ARM: add
On Wed, May 7, 2014 at 8:05 PM, Arnd Bergmann wrote:
> On Wednesday 07 May 2014 17:21:13 Srikanth Thokala wrote:
>> On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann wrote:
>> > On Tuesday 15 April 2014, Srikanth Thokala wrote:
>> >> +/**
>> >> + * xilin
On Wed, May 7, 2014 at 8:05 PM, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 07 May 2014 17:21:13 Srikanth Thokala wrote:
On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 15 April 2014, Srikanth Thokala wrote:
+/**
+ * xilinx_pcie_get_config_base - Get
On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann wrote:
> On Tuesday 15 April 2014, Srikanth Thokala wrote:
>> +Required properties:
>> +- #address-cells: Address representation for root ports, set to <3>
>> +- #size-cells: Size representation for root ports, set to
On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 15 April 2014, Srikanth Thokala wrote:
+Required properties:
+- #address-cells: Address representation for root ports, set to 3
+- #size-cells: Size representation for root ports, set to 2
+- #interrupt-cells
On Thu, May 1, 2014 at 3:11 AM, Bjorn Helgaas wrote:
> On Tue, Apr 15, 2014 at 05:08:31PM +0530, Srikanth Thokala wrote:
>> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes in v3:
>> - Re
On Thu, May 1, 2014 at 3:11 AM, Bjorn Helgaas bhelg...@google.com wrote:
On Tue, Apr 15, 2014 at 05:08:31PM +0530, Srikanth Thokala wrote:
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v3:
- Rebased on v3.15.0
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Acked-by: Jassi Brar
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and we are also
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
Acked-by: Rob Herring
---
Changes in v8:
Fixed typos as suggested by Rob, Thanks.
Changes in v7:
None
Changes in v6:
None
Changes in v5:
None
Changes in v4:
None
Changes in v3:
None
Changes in v2
Hi,
Kindly review the driver and please let me know if you have any comments.
Thanks
Srikanth
On Tue, Apr 15, 2014 at 5:08 PM, Srikanth Thokala wrote:
> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>
> Signed-off-by: Srikanth Thokala
> ---
> Changes in v3:
> -
Hi,
Kindly review the driver and please let me know if you have any comments.
Thanks
Srikanth
On Tue, Apr 15, 2014 at 5:08 PM, Srikanth Thokala stho...@xilinx.com wrote:
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Acked-by: Rob Herring r...@kernel.org
---
Changes in v8:
Fixed typos as suggested by Rob, Thanks.
Changes in v7:
None
Changes in v6:
None
Changes in v5:
None
Changes in v4:
None
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala stho...@xilinx.com
Acked-by: Jassi Brar jassisinghb...@gmail.com
Reviewed-by: Levente Kurusa le...@linux.com
---
NOTE:
- Created a separate directory 'dma
On Wed, Apr 16, 2014 at 5:01 PM, Vinod Koul wrote:
> On Tue, Apr 01, 2014 at 05:57:04PM +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Direct Memory Access (AXI DMA)
>> core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct memory
On Wed, Apr 16, 2014 at 5:01 PM, Vinod Koul vinod.k...@intel.com wrote:
On Tue, Apr 01, 2014 at 05:57:04PM +0530, Srikanth Thokala wrote:
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access
On Wed, Apr 16, 2014 at 3:56 PM, Vinod Koul wrote:
> On Wed, Apr 16, 2014 at 03:41:34PM +0530, Srikanth Thokala wrote:
>> On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul wrote:
>> > On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
>> >> This is the d
On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul wrote:
> On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Video Direct Memory Access (AXI
>> VDMA) core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct
On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul vinod.k...@intel.com wrote:
On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
This is the driver for the AXI Video Direct Memory Access (AXI
VDMA) core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access
On Wed, Apr 16, 2014 at 3:56 PM, Vinod Koul vinod.k...@intel.com wrote:
On Wed, Apr 16, 2014 at 03:41:34PM +0530, Srikanth Thokala wrote:
On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul vinod.k...@intel.com wrote:
On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource
Hi Jonathan,
On Tue, Apr 8, 2014 at 8:14 PM, Jonathan Corbet wrote:
> On Mon, 7 Apr 2014 20:22:54 +0530
> Srikanth Thokala wrote:
>
>> Kindly review this driver and please let me know if you have any comments.
>
> Here's some comments from a quick look at the patch
Hi Jonathan,
On Tue, Apr 8, 2014 at 8:14 PM, Jonathan Corbet cor...@lwn.net wrote:
On Mon, 7 Apr 2014 20:22:54 +0530
Srikanth Thokala stho...@xilinx.com wrote:
Kindly review this driver and please let me know if you have any comments.
Here's some comments from a quick look at the patch
Hi,
Kindly review this driver and please let me know if you have any comments.
Thanks
Srikanth
On Mon, Mar 31, 2014 at 7:24 PM, Srikanth Thokala wrote:
> This is the driver for the AXI Central Direct Memory Access (AXI
> CDMA) core, which is a soft Xilinx IP core that provides high-ban
Hi,
Kindly review this driver patch and please let me know if you have any comments.
Srikanth
On Tue, Apr 1, 2014 at 5:57 PM, Srikanth Thokala wrote:
> This is the driver for the AXI Direct Memory Access (AXI DMA)
> core, which is a soft Xilinx IP core that provides high-
> bandwid
Hi,
Kindly review this driver patch and please let me know if you have any comments.
Srikanth
On Tue, Apr 1, 2014 at 5:57 PM, Srikanth Thokala stho...@xilinx.com wrote:
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high
Hi,
Kindly review this driver and please let me know if you have any comments.
Thanks
Srikanth
On Mon, Mar 31, 2014 at 7:24 PM, Srikanth Thokala stho...@xilinx.com wrote:
This is the driver for the AXI Central Direct Memory Access (AXI
CDMA) core, which is a soft Xilinx IP core that provides
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx
-by: Srikanth Thokala
---
Note:
- This driver patch is created on top of earlier series,
1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation"
2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support"
- Rebased on v3.14.0-rc8
Changes in v2:
- Simplified the logi
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree
-by: Srikanth Thokala stho...@xilinx.com
---
Note:
- This driver patch is created on top of earlier series,
1/2 - dma: Add Xilinx Video DMA DT Binding Documentation
2/2 - dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
- Rebased on v3.14.0-rc8
Changes in v2:
- Simplified the logic
) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
---
NOTE:
- This driver patch is created on top of earlier series,
1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation"
2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support"
- Rebased on v3.14.0-
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala
---
.../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
On Mon, Mar 31, 2014 at 3:00 PM, Andy Shevchenko
wrote:
> On Sat, 2014-03-29 at 20:58 +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Direct Memory Access (AXI DMA)
>> core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct memory
On Mon, Mar 31, 2014 at 3:00 PM, Andy Shevchenko
andriy.shevche...@linux.intel.com wrote:
On Sat, 2014-03-29 at 20:58 +0530, Srikanth Thokala wrote:
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
.../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx
) and Microblaze platforms.
Signed-off-by: Srikanth Thokala stho...@xilinx.com
---
NOTE:
- This driver patch is created on top of earlier series,
1/2 - dma: Add Xilinx Video DMA DT Binding Documentation
2/2 - dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
- Rebased on v3.14.0-rc8
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