and
secondary cores as expected.
HWCAPs show no PAC support and kernel instructions are being treated as
NOPs.
Tested-by: Srinivas Ramana
).
HWCAPs show no BTI support and kernel instructions are being treated as
NOPs.
We don't have plan to repeat the test on v5 as there are not major
changes here.
Tested-by: Srinivas Ramana
Hi Marc,
On 1/11/2021 5:40 AM, Marc Zyngier wrote:
Hi Srinivas,
On 2021-01-09 00:29, Srinivas Ramana wrote:
This patchset adds a control function for cpufeature framework
so that the feature can be controlled at runtime.
Defer PAC on boot core and use the filter function added to disable
PAC
Hi Catalin,
On 1/11/2021 10:41 AM, Catalin Marinas wrote:
Hi Marc,
On Mon, Jan 11, 2021 at 01:27:59PM +, Marc Zyngier wrote:
Add a facility to globally override a feature, no matter what
the HW says. Yes, this is dangerous.
Yeah, it's dangerous. We can make it less so if we only allow
Defer enabling pointer authentication on boot core until
after its required to be enabled by cpufeature framework.
This will help in controlling the feature dynamically
with a boot parameter.
Signed-off-by: Ajay Patil
Signed-off-by: Prasad Sodagudi
Signed-off-by: Srinivas Ramana
---
arch
Add support to control turning off the pointer authentication
using a kernel command line early param.
This will help control pointer authentication feature for both kernel
and userspace without kernel changes.
Signed-off-by: Ajay Patil
Signed-off-by: Prasad Sodagudi
Signed-off-by: Srinivas
Add a filter function to cpufeature so that it can be used
when dynamic control of the feature is required.
Signed-off-by: Ajay Patil
Signed-off-by: Prasad Sodagudi
Signed-off-by: Srinivas Ramana
---
arch/arm64/include/asm/cpufeature.h | 8 +++-
arch/arm64/kernel/cpufeature.c | 15
...@arm.com/
Srinivas Ramana (3):
arm64: Defer enabling pointer authentication on boot core
arm64: cpufeature: Add a filter function to cpufeature
arm64: Enable control of pointer authentication using early param
Documentation/admin-guide/kernel-parameters.txt | 6 +++
arch/arm64/include/asm
Commit-ID: bddda606ec76550dd63592e32a6e87e7d32583f7
Gitweb: https://git.kernel.org/tip/bddda606ec76550dd63592e32a6e87e7d32583f7
Author: Srinivas Ramana
AuthorDate: Thu, 20 Dec 2018 19:05:57 +0530
Committer: Thomas Gleixner
CommitDate: Tue, 15 Jan 2019 11:23:27 +0100
genirq: Make sure
On 12/20/2018 7:05 PM, Srinivas Ramana wrote:
If the default_affinity is managed/initialized by a system and
all the cpus present in irq_default_affinity are hotplugged out
we may end up passing a cpumask of 0 to irq_do_set_affinity().
Fix this by falling back to cpu_online_mask in case
-by: Srinivas Ramana
---
kernel/irq/manage.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
index 9dbdccab3b6a..5c0ba5ca5930 100644
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -393,6 +393,9 @@ int irq_setup_affinity(struct irq_desc *desc
interrupts gets cleared.
Signed-off-by: Srinivas Ramana <sram...@codeaurora.org>
---
drivers/pinctrl/qcom/pinctrl-msm.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c
b/drivers/pinctrl/qcom/pinctrl-msm.c
index 7a9605
interrupts gets cleared.
Signed-off-by: Srinivas Ramana
---
drivers/pinctrl/qcom/pinctrl-msm.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c
b/drivers/pinctrl/qcom/pinctrl-msm.c
index 7a960590ecaa..de7c65c15f9e 100644
On 03/22/2017 07:15 PM, Srinivas Ramana wrote:
On 03/22/2017 06:10 PM, Will Deacon wrote:
On Wed, Mar 22, 2017 at 12:16:24PM +, Ard Biesheuvel wrote:
On 22 March 2017 at 11:38, Srinivas Ramana <sram...@codeaurora.org>
wrote:
From: Neeraj Upadhyay <neer...@codeaurora.org>
If
On 03/22/2017 07:15 PM, Srinivas Ramana wrote:
On 03/22/2017 06:10 PM, Will Deacon wrote:
On Wed, Mar 22, 2017 at 12:16:24PM +, Ard Biesheuvel wrote:
On 22 March 2017 at 11:38, Srinivas Ramana
wrote:
From: Neeraj Upadhyay
If kernel image extends across alignment boundary, existing
code
On 03/22/2017 06:10 PM, Will Deacon wrote:
On Wed, Mar 22, 2017 at 12:16:24PM +, Ard Biesheuvel wrote:
On 22 March 2017 at 11:38, Srinivas Ramana <sram...@codeaurora.org> wrote:
From: Neeraj Upadhyay <neer...@codeaurora.org>
If kernel image extends across alignment boundary, e
On 03/22/2017 06:10 PM, Will Deacon wrote:
On Wed, Mar 22, 2017 at 12:16:24PM +, Ard Biesheuvel wrote:
On 22 March 2017 at 11:38, Srinivas Ramana wrote:
From: Neeraj Upadhyay
If kernel image extends across alignment boundary, existing
code increases the KASLR offset by size of kernel
ABLE_SHIFT = 0x3fe7d
new offset w/ rounding up = 0x1f3800
(_text + offset) >> SWAPPER_TABLE_SHIFT = 0x3fe7d
(_end + offset) >> SWAPPER_TABLE_SHIFT = 0x3fe7d
Fixes: f80fb3a3d508 ("arm64: add support for kernel ASLR")
Signed-off-by: Neeraj Upadhyay <neer...@codeaurora
w/ rounding up = 0x1f3800
(_text + offset) >> SWAPPER_TABLE_SHIFT = 0x3fe7d
(_end + offset) >> SWAPPER_TABLE_SHIFT = 0x3fe7d
Fixes: f80fb3a3d508 ("arm64: add support for kernel ASLR")
Signed-off-by: Neeraj Upadhyay
Signed-off-by: Srinivas Ramana
---
arch/arm6
4: add support for kernel ASLR")
Signed-off-by: Neeraj Upadhyay <neer...@codeaurora.org>
Signed-off-by: Srinivas Ramana <sram...@codeaurora.org>
---
arch/arm64/kernel/kaslr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/kaslr.c b/arch/arm64/kernel/kasl
w/ 2MB correction (before mask) = 0x1f37819b00
new offset w/ 2MB correction (after mask) = 0x1f3800
(_text + offset) >> SWAPPER_TABLE_SHIFT = 0x3fe7d
(_end + offset) >> SWAPPER_TABLE_SHIFT = 0x3fe7d
Fixes: f80fb3a3d508 ("arm64: add support for kernel ASLR")
Signe
On 12/12/2016 04:12 PM, Will Deacon wrote:
On Mon, Dec 12, 2016 at 10:31:52AM +0530, Srinivas Ramana wrote:
On 12/06/2016 05:43 PM, Will Deacon wrote:
On Sun, Dec 04, 2016 at 02:06:23PM +0530, Srinivas Ramana wrote:
On 12/02/2016 04:38 PM, Will Deacon wrote:
On Fri, Dec 02, 2016 at 01:44
On 12/12/2016 04:12 PM, Will Deacon wrote:
On Mon, Dec 12, 2016 at 10:31:52AM +0530, Srinivas Ramana wrote:
On 12/06/2016 05:43 PM, Will Deacon wrote:
On Sun, Dec 04, 2016 at 02:06:23PM +0530, Srinivas Ramana wrote:
On 12/02/2016 04:38 PM, Will Deacon wrote:
On Fri, Dec 02, 2016 at 01:44
On 12/06/2016 05:43 PM, Will Deacon wrote:
On Sun, Dec 04, 2016 at 02:06:23PM +0530, Srinivas Ramana wrote:
On 12/02/2016 04:38 PM, Will Deacon wrote:
On Fri, Dec 02, 2016 at 01:44:55PM +0530, Srinivas Ramana wrote:
Extend the trace_clock to support the arch timer cycle
counter so that we can
On 12/06/2016 05:43 PM, Will Deacon wrote:
On Sun, Dec 04, 2016 at 02:06:23PM +0530, Srinivas Ramana wrote:
On 12/02/2016 04:38 PM, Will Deacon wrote:
On Fri, Dec 02, 2016 at 01:44:55PM +0530, Srinivas Ramana wrote:
Extend the trace_clock to support the arch timer cycle
counter so that we can
On 12/02/2016 04:38 PM, Will Deacon wrote:
On Fri, Dec 02, 2016 at 01:44:55PM +0530, Srinivas Ramana wrote:
Extend the trace_clock to support the arch timer cycle
counter so that we can get the monotonic cycle count
in the traces. This will help in correlating the traces with the
timestamps
On 12/02/2016 04:38 PM, Will Deacon wrote:
On Fri, Dec 02, 2016 at 01:44:55PM +0530, Srinivas Ramana wrote:
Extend the trace_clock to support the arch timer cycle
counter so that we can get the monotonic cycle count
in the traces. This will help in correlating the traces with the
timestamps
-by: Srinivas Ramana <sram...@codeaurora.org>
---
arch/arm64/include/asm/Kbuild| 1 -
arch/arm64/include/asm/trace_clock.h | 20
2 files changed, 20 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/include/asm/trace_clock.h
diff --git a/arch/arm64/inclu
-by: Srinivas Ramana
---
arch/arm64/include/asm/Kbuild| 1 -
arch/arm64/include/asm/trace_clock.h | 20
2 files changed, 20 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/include/asm/trace_clock.h
diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include
mpressor: reset ttbcr for VMSA ARMv7
cores")
Acked-by: Robin Murphy <robin.mur...@arm.com>
Signed-off-by: Srinivas Ramana <sram...@codeaurora.org>
---
arch/arm/boot/compressed/head.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/compressed/head.S b
mpressor: reset ttbcr for VMSA ARMv7
cores")
Acked-by: Robin Murphy
Signed-off-by: Srinivas Ramana
---
arch/arm/boot/compressed/head.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index af11c2f8f3b7.
Hi Robin,
On 09/13/2016 08:22 PM, Srinivas Ramana wrote:
On 09/12/2016 11:21 PM, Robin Murphy wrote:
On 12/09/16 07:57, Srinivas Ramana wrote:
If the bootloader uses the long descriptor format and jumps to
kernel decompressor code, TTBCR may not be in a right state.
Before enabling the MMU
Hi Robin,
On 09/13/2016 08:22 PM, Srinivas Ramana wrote:
On 09/12/2016 11:21 PM, Robin Murphy wrote:
On 12/09/16 07:57, Srinivas Ramana wrote:
If the bootloader uses the long descriptor format and jumps to
kernel decompressor code, TTBCR may not be in a right state.
Before enabling the MMU
On 09/12/2016 11:21 PM, Robin Murphy wrote:
On 12/09/16 07:57, Srinivas Ramana wrote:
If the bootloader uses the long descriptor format and jumps to
kernel decompressor code, TTBCR may not be in a right state.
Before enabling the MMU, it is required to clear the TTBCR.PD0
field to use TTBR0
On 09/12/2016 11:21 PM, Robin Murphy wrote:
On 12/09/16 07:57, Srinivas Ramana wrote:
If the bootloader uses the long descriptor format and jumps to
kernel decompressor code, TTBCR may not be in a right state.
Before enabling the MMU, it is required to clear the TTBCR.PD0
field to use TTBR0
reset ttbcr for VMSA ARMv7 cores")' does the reset of TTBCR.N, but
doesn't consider all the bits for the size of TTBCR.N.
Clear TTBCR.PD0 field and reset all the three bits of TTBCR.N to
indicate the use of TTBR0 and the correct base address width.
Signed-off-by: Srinivas Ramana <sram...@c
reset ttbcr for VMSA ARMv7 cores")' does the reset of TTBCR.N, but
doesn't consider all the bits for the size of TTBCR.N.
Clear TTBCR.PD0 field and reset all the three bits of TTBCR.N to
indicate the use of TTBR0 and the correct base address width.
Signed-off-by: Srinivas Ramana
---
arc
On 09/09/2016 11:06 PM, Nicolas Pitre wrote:
On Fri, 9 Sep 2016, Srinivas Ramana wrote:
Hello,
While trying to boot arm-32 bit kernel, I came across a problem where TTBCR is
in improper state. If the bootloader uses the long descriptor format and jumps
to kernel decompressor code, TTBCR may
On 09/09/2016 11:06 PM, Nicolas Pitre wrote:
On Fri, 9 Sep 2016, Srinivas Ramana wrote:
Hello,
While trying to boot arm-32 bit kernel, I came across a problem where TTBCR is
in improper state. If the bootloader uses the long descriptor format and jumps
to kernel decompressor code, TTBCR may
On 09/09/2016 11:06 PM, Nicolas Pitre wrote:
On Fri, 9 Sep 2016, Srinivas Ramana wrote:
Hello,
While trying to boot arm-32 bit kernel, I came across a problem where TTBCR is
in improper state. If the bootloader uses the long descriptor format and jumps
to kernel decompressor code, TTBCR may
On 09/09/2016 11:06 PM, Nicolas Pitre wrote:
On Fri, 9 Sep 2016, Srinivas Ramana wrote:
Hello,
While trying to boot arm-32 bit kernel, I came across a problem where TTBCR is
in improper state. If the bootloader uses the long descriptor format and jumps
to kernel decompressor code, TTBCR may
Hello,
While trying to boot arm-32 bit kernel, I came across a problem where
TTBCR is in improper state. If the bootloader uses the long descriptor
format and jumps to kernel decompressor code, TTBCR may not be in the
right state. So, as soon as the MMU is enabled, execution can not
proceed
Hello,
While trying to boot arm-32 bit kernel, I came across a problem where
TTBCR is in improper state. If the bootloader uses the long descriptor
format and jumps to kernel decompressor code, TTBCR may not be in the
right state. So, as soon as the MMU is enabled, execution can not
proceed
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