This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
Reviewed-by: Rob Herring
---
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++
1 file changed, 64 insertions
Signed-off-by: Stefan Agner
---
MAINTAINERS |7 +
drivers/mtd/nand/raw/Kconfig |6 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/tegra_nand.c | 1248 +
4 files changed, 1262 insertions(+)
create mode 100644
Signed-off-by: Stefan Agner
---
MAINTAINERS |7 +
drivers/mtd/nand/raw/Kconfig |6 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/tegra_nand.c | 1248 +
4 files changed, 1262 insertions(+)
create mode 100644
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b/arch/arm/boot/dts
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b/arch/arm/boot/dts
From: Lucas Stach
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 15
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
---
Documentation/devicetree/bindings/mtd/nand.txt | 2 +-
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h| 1 +
3 files
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
Reviewed-by: Boris Brezillon
---
Documentation/devicetree/bindings/mtd/nand.txt | 2 +-
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h| 1 +
3 files
From: Lucas Stach
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 15
ty
- Clear interrupts and reinit wait queues in case command/DMA times out
- Set default MTD name after nand_set_flash_node
- Move MODULE_DEVICE_TABLE after declaration of tegra_nand_of_match
- Make (rs|bch)_strength static
Lucas Stach (1):
ARM: dts: tegra: add Tegra20 NAND flash controller node
Stefa
ty
- Clear interrupts and reinit wait queues in case command/DMA times out
- Set default MTD name after nand_set_flash_node
- Move MODULE_DEVICE_TABLE after declaration of tegra_nand_of_match
- Make (rs|bch)_strength static
Lucas Stach (1):
ARM: dts: tegra: add Tegra20 NAND flash controller node
Stefa
On 11.06.2018 14:42, Clément Péron wrote:
> Hi Stefan,
>
>
>> > +
>> > +#define EPITCR 0x00
>> > +#define EPITSR 0x04
>> > +#define EPITLR 0x08
>> > +#define EPITCMPR 0x0c
>> > +#define
On 11.06.2018 14:42, Clément Péron wrote:
> Hi Stefan,
>
>
>> > +
>> > +#define EPITCR 0x00
>> > +#define EPITSR 0x04
>> > +#define EPITLR 0x08
>> > +#define EPITCMPR 0x0c
>> > +#define
On 07.06.2018 16:05, Clément Péron wrote:
> From: Colin Didier
>
> Add driver for NXP's EPIT timer used in i.MX SoC.
>
> Signed-off-by: Colin Didier
> Signed-off-by: Clément Peron
> ---
> drivers/clocksource/Kconfig | 11 ++
> drivers/clocksource/Makefile | 1 +
>
On 07.06.2018 16:05, Clément Péron wrote:
> From: Colin Didier
>
> Add driver for NXP's EPIT timer used in i.MX SoC.
>
> Signed-off-by: Colin Didier
> Signed-off-by: Clément Peron
> ---
> drivers/clocksource/Kconfig | 11 ++
> drivers/clocksource/Makefile | 1 +
>
On 09.06.2018 14:21, Dmitry Osipenko wrote:
> On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
>> On 01.06.2018 11:20, Dmitry Osipenko wrote:
>> > On 01.06.2018 01:16, Stefan Agner wrote:
>> >> Add support for the NAND flash controller foun
On 09.06.2018 14:21, Dmitry Osipenko wrote:
> On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
>> On 01.06.2018 11:20, Dmitry Osipenko wrote:
>> > On 01.06.2018 01:16, Stefan Agner wrote:
>> >> Add support for the NAND flash controller foun
On 09.06.2018 08:41, Boris Brezillon wrote:
> On Sat, 09 Jun 2018 08:23:51 +0200
> Stefan Agner wrote:
>
>> On 09.06.2018 07:52, Boris Brezillon wrote:
>> > On Fri, 08 Jun 2018 23:51:01 +0200
>> > Stefan Agner wrote:
>> >
>> >
>
On 09.06.2018 08:41, Boris Brezillon wrote:
> On Sat, 09 Jun 2018 08:23:51 +0200
> Stefan Agner wrote:
>
>> On 09.06.2018 07:52, Boris Brezillon wrote:
>> > On Fri, 08 Jun 2018 23:51:01 +0200
>> > Stefan Agner wrote:
>> >
>> >
>
On 09.06.2018 07:52, Boris Brezillon wrote:
> On Fri, 08 Jun 2018 23:51:01 +0200
> Stefan Agner wrote:
>
>
>> >
>> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
>> > {
>> >int err;
>> >
>> >disabl
On 09.06.2018 07:52, Boris Brezillon wrote:
> On Fri, 08 Jun 2018 23:51:01 +0200
> Stefan Agner wrote:
>
>
>> >
>> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
>> > {
>> >int err;
>> >
>> >disabl
On 01.06.2018 11:20, Dmitry Osipenko wrote:
> On 01.06.2018 01:16, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers ar
On 01.06.2018 11:20, Dmitry Osipenko wrote:
> On 01.06.2018 01:16, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers ar
o wrote:
>> > > On 01.06.2018 10:30, Boris Brezillon wrote:
>> > > > On Fri, 1 Jun 2018 00:16:34 +0200
>> > > > Stefan Agner wrote:
>> > > >
>> > > >> This adds the devicetree binding for the Tegra 2 N
o wrote:
>> > > On 01.06.2018 10:30, Boris Brezillon wrote:
>> > > > On Fri, 1 Jun 2018 00:16:34 +0200
>> > > > Stefan Agner wrote:
>> > > >
>> > > >> This adds the devicetree binding for the Tegra 2 N
On 05.06.2018 08:27, Masahiro Yamada wrote:
> 2018-06-05 14:50 GMT+09:00 Stefan Agner :
>> On 05.06.2018 02:07, Masahiro Yamada wrote:
>>> Hi Stefan
>>>
>>> 2018-06-05 6:49 GMT+09:00 Stefan Agner :
>>>> Hi Masahiro,
>>>>
>>>&g
On 05.06.2018 08:27, Masahiro Yamada wrote:
> 2018-06-05 14:50 GMT+09:00 Stefan Agner :
>> On 05.06.2018 02:07, Masahiro Yamada wrote:
>>> Hi Stefan
>>>
>>> 2018-06-05 6:49 GMT+09:00 Stefan Agner :
>>>> Hi Masahiro,
>>>>
>>>&g
On 05.06.2018 02:07, Masahiro Yamada wrote:
> Hi Stefan
>
> 2018-06-05 6:49 GMT+09:00 Stefan Agner :
>> Hi Masahiro,
>>
>> On 28.05.2018 11:22, Masahiro Yamada wrote:
>>> This will be useful to specify the required compiler version,
>>> like this:
On 05.06.2018 02:07, Masahiro Yamada wrote:
> Hi Stefan
>
> 2018-06-05 6:49 GMT+09:00 Stefan Agner :
>> Hi Masahiro,
>>
>> On 28.05.2018 11:22, Masahiro Yamada wrote:
>>> This will be useful to specify the required compiler version,
>>> like this:
Hi Masahiro,
On 28.05.2018 11:22, Masahiro Yamada wrote:
> This will be useful to specify the required compiler version,
> like this:
>
> config FOO
> bool "Use Foo"
> depends on GCC_VERSION >= 40800
> help
> This feature requires GCC 4.8 or newer.
>
I tried
Hi Masahiro,
On 28.05.2018 11:22, Masahiro Yamada wrote:
> This will be useful to specify the required compiler version,
> like this:
>
> config FOO
> bool "Use Foo"
> depends on GCC_VERSION >= 40800
> help
> This feature requires GCC 4.8 or newer.
>
I tried
Hi Randolph,
On 04.06.2018 19:16, Randolph Maaßen wrote:
> Am Freitag, den 01.06.2018, 00:16 +0200 schrieb Stefan Agner:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Re
Hi Randolph,
On 04.06.2018 19:16, Randolph Maaßen wrote:
> Am Freitag, den 01.06.2018, 00:16 +0200 schrieb Stefan Agner:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Re
On 01.06.2018 11:25, Boris Brezillon wrote:
> On Fri, 1 Jun 2018 09:26:00 +0200
> Boris Brezillon wrote:
>
>> On Fri, 1 Jun 2018 00:16:32 +0200
>> Stefan Agner wrote:
>>
>> > Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
>> >
>
On 01.06.2018 11:25, Boris Brezillon wrote:
> On Fri, 1 Jun 2018 09:26:00 +0200
> Boris Brezillon wrote:
>
>> On Fri, 1 Jun 2018 00:16:32 +0200
>> Stefan Agner wrote:
>>
>> > Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
>> >
>
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++
1 file changed, 64 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++
1 file changed, 64 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mtd
Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.
Signed-off-by: Stefan Agner
---
Documentation/devicetree/bindings/mtd/nand.txt | 4
drivers/mtd
Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.
Signed-off-by: Stefan Agner
---
Documentation/devicetree/bindings/mtd/nand.txt | 4
drivers/mtd
From: Lucas Stach
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b
From: Lucas Stach
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index
ut
- Unify tegra_nand_(read|write)_page in tegra_nand_page_xfer
Lucas Stach (2):
ARM: dts: tegra: add Tegra20 NAND flash controller node
ARM: dts: tegra: enable NAND flash on Colibri T20
Stefan Agner (4):
mtd: rawnand: add Reed-Solomon error correction algorithm
mtd: rawnand: add an option to sp
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index
ut
- Unify tegra_nand_(read|write)_page in tegra_nand_page_xfer
Lucas Stach (2):
ARM: dts: tegra: add Tegra20 NAND flash controller node
ARM: dts: tegra: enable NAND flash on Colibri T20
Stefan Agner (4):
mtd: rawnand: add Reed-Solomon error correction algorithm
mtd: rawnand: add an option to sp
From: Lucas Stach
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 15
Signed-off-by: Stefan Agner
---
MAINTAINERS |7 +
drivers/mtd/nand/raw/Kconfig |6 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/tegra_nand.c | 1143 +
4 files changed, 1157 insertions(+)
create mode 100644
From: Lucas Stach
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 15
Signed-off-by: Stefan Agner
---
MAINTAINERS |7 +
drivers/mtd/nand/raw/Kconfig |6 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/tegra_nand.c | 1143 +
4 files changed, 1157 insertions(+)
create mode 100644
On 31.05.2018 22:30, Boris Brezillon wrote:
> On Thu, 31 May 2018 19:54:08 +0200
> Stefan Agner wrote:
>
>> >> +
>> >> + mtd->dev.parent = >dev;
>> >> + mtd->name = "tegra_nand";
>> >
>> > I just figured it was
On 31.05.2018 22:30, Boris Brezillon wrote:
> On Thu, 31 May 2018 19:54:08 +0200
> Stefan Agner wrote:
>
>> >> +
>> >> + mtd->dev.parent = >dev;
>> >> + mtd->name = "tegra_nand";
>> >
>> > I just figured it was
n Tue, 22 May 2018 14:07:06 +0200, Stefan Agner
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode.
n Tue, 22 May 2018 14:07:06 +0200, Stefan Agner
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode.
On 31.05.2018 11:37, Stefan Agner wrote:
> On 27.05.2018 23:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>
On 31.05.2018 11:37, Stefan Agner wrote:
> On 27.05.2018 23:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>
On 27.05.2018 23:54, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware EC
On 27.05.2018 23:54, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware EC
On 29.05.2018 09:48, Peter De Schrijver wrote:
> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote:
>> On 28.05.2018 09:55, Peter De Schrijver wrote:
>> > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> >> From: Lucas Stach
>> >&
On 29.05.2018 09:48, Peter De Schrijver wrote:
> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote:
>> On 28.05.2018 09:55, Peter De Schrijver wrote:
>> > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> >> From: Lucas Stach
>> >&
On 28.05.2018 09:55, Peter De Schrijver wrote:
> On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> From: Lucas Stach <d...@lynxeye.de>
>>
>> Set up the NAND Flash controller clock to run at 150MHz
>> instead of the rate set by the bootloader. Thi
On 28.05.2018 09:55, Peter De Schrijver wrote:
> On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> From: Lucas Stach
>>
>> Set up the NAND Flash controller clock to run at 150MHz
>> instead of the rate set by the bootloader. This is a
>> conserv
On 28.05.2018 13:57, Dmitry Osipenko wrote:
> On 28.05.2018 00:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers ar
On 28.05.2018 13:57, Dmitry Osipenko wrote:
> On 28.05.2018 00:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers ar
On 28.05.2018 00:19, Miquel Raynal wrote:
> Hi Stefan,
>
> A few more comments here.
>
> On Sun, 27 May 2018 23:54:39 +0200, Stefan Agner <ste...@agner.ch>
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs
On 28.05.2018 00:19, Miquel Raynal wrote:
> Hi Stefan,
>
> A few more comments here.
>
> On Sun, 27 May 2018 23:54:39 +0200, Stefan Agner
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not
or the work though!
> Miquèl
>
> On Tue, 22 May 2018 14:07:06 +0200, Stefan Agner <ste...@agner.ch>
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature.
or the work though!
> Miquèl
>
> On Tue, 22 May 2018 14:07:06 +0200, Stefan Agner
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operation
From: Lucas Stach <d...@lynxeye.de>
Set up the NAND Flash controller clock to run at 150MHz
instead of the rate set by the bootloader. This is a
conservative rate which also yields good performance.
Signed-off-by: Lucas Stach <d...@lynxeye.de>
Signed-off-by: Stefan Agner <
From: Lucas Stach <d...@lynxeye.de>
Add basic controller description to be extended
by individual boards.
Signed-off-by: Lucas Stach <d...@lynxeye.de>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
arch/arm/boot/dts/tegra20.dtsi | 13 +
1 file changed, 13 i
<d...@lynxeye.de>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
MAINTAINERS | 7 +
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/tegra_nand.c | 999 ++
4 files c
From: Lucas Stach
Set up the NAND Flash controller clock to run at 150MHz
instead of the rate set by the bootloader. This is a
conservative rate which also yields good performance.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
drivers/clk/tegra/clk-tegra20.c | 1 +
1 file
From: Lucas Stach
Add basic controller description to be extended
by individual boards.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot
Signed-off-by: Stefan Agner
---
MAINTAINERS | 7 +
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/tegra_nand.c | 999 ++
4 files changed, 1013 insertions(+)
create mode 100644 drivers
gra: add Tegra20 NAND flash controller node
ARM: tegra: enable NAND flash on Colibri T20
Stefan Agner (2):
mtd: rawnand: add Reed-Solomon error correction algorithm
mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
.../bindings/mtd/nvidia,tegra20-nand.txt | 62 ++
MAINTAIN
From: Lucas Stach <d...@lynxeye.de>
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach <d...@lynxeye.de>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 i
gra: add Tegra20 NAND flash controller node
ARM: tegra: enable NAND flash on Colibri T20
Stefan Agner (2):
mtd: rawnand: add Reed-Solomon error correction algorithm
mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
.../bindings/mtd/nvidia,tegra20-nand.txt | 62 ++
MAINTAIN
From: Lucas Stach
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
b
From: Lucas Stach <d...@lynxeye.de>
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach <d...@lynxeye.de>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
.../bindings/mtd/nvidia,tegra20-nand.txt | 62 +++
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/na
From: Lucas Stach
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach
Signed-off-by: Stefan Agner
---
.../bindings/mtd/nvidia,tegra20-nand.txt | 62 +++
1 file changed, 62 insertions(+)
create mode 100644
Documentation
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index
e:
>>
>> > On Sun, 27 May 2018 16:18:32 +0200
>> > Miquel Raynal <miquel.ray...@bootlin.com> wrote:
>> >
>> > > Hi Stefan,
>> > >
>> > > On Thu, 24 May 2018 14:19:18 +0200, Stefan Agner <ste...@agner.ch>
>> > > wro
>> > Miquel Raynal wrote:
>> >
>> > > Hi Stefan,
>> > >
>> > > On Thu, 24 May 2018 14:19:18 +0200, Stefan Agner
>> > > wrote:
>> > >
>> > > > On 24.05.2018 13:53, Boris Brezillon wrote:
>> &
On 24.05.2018 14:41, Boris Brezillon wrote:
> On Thu, 24 May 2018 14:23:56 +0200
> Boris Brezillon <boris.brezil...@bootlin.com> wrote:
>
>> On Thu, 24 May 2018 13:09:53 +0200
>> Stefan Agner <ste...@agner.ch> wrote:
>>
>> > On 24.05.2018 10:56, B
On 24.05.2018 14:41, Boris Brezillon wrote:
> On Thu, 24 May 2018 14:23:56 +0200
> Boris Brezillon wrote:
>
>> On Thu, 24 May 2018 13:09:53 +0200
>> Stefan Agner wrote:
>>
>> > On 24.05.2018 10:56, Boris Brezillon wrote:
>> > > On Thu, 24 Ma
On 24.05.2018 13:53, Boris Brezillon wrote:
> Hi Benjamin,
>
> On Thu, 24 May 2018 13:30:14 +0200
> Benjamin Lindqvist wrote:
>
>> Hi Stefan,
>>
>> It seems to me that a probe similar to what the BootROM does shouldn't
>> be awfully complicated to implement - just
On 24.05.2018 13:53, Boris Brezillon wrote:
> Hi Benjamin,
>
> On Thu, 24 May 2018 13:30:14 +0200
> Benjamin Lindqvist wrote:
>
>> Hi Stefan,
>>
>> It seems to me that a probe similar to what the BootROM does shouldn't
>> be awfully complicated to implement - just cycle through the switch
>>
On 24.05.2018 10:56, Boris Brezillon wrote:
> On Thu, 24 May 2018 10:46:27 +0200
> Stefan Agner <ste...@agner.ch> wrote:
>
>> Hi Boris,
>>
>> Thanks for the initial review! One small question below:
>>
>> On 23.05.2018 16:18, Boris Brezillon wrote:
>
On 24.05.2018 10:56, Boris Brezillon wrote:
> On Thu, 24 May 2018 10:46:27 +0200
> Stefan Agner wrote:
>
>> Hi Boris,
>>
>> Thanks for the initial review! One small question below:
>>
>> On 23.05.2018 16:18, Boris Brezillon wrote:
>> > Hi Stef
On 24.05.2018 09:45, Benjamin Lindqvist wrote:
> Hi Stefan (and all),
>
> First off, I apoloigize in advance if I'm deviating from common
> kernel mailing list courtesy -- this is my first time responding.
> I just have a comment on the NAND driver that I'd like to bring
> to the public.
>
On 24.05.2018 09:45, Benjamin Lindqvist wrote:
> Hi Stefan (and all),
>
> First off, I apoloigize in advance if I'm deviating from common
> kernel mailing list courtesy -- this is my first time responding.
> I just have a comment on the NAND driver that I'd like to bring
> to the public.
>
ny.dtb: Warning (unit_address_vs_reg):
> /memory: node has a reg or ranges property, but no unit name
>
> The DTB after the change is the same as before except adding
> unit-address to /memory node.
>
> Signed-off-by: Krzysztof Kozlowski <k...@kernel.org>
>
Looks good to m
ny.dtb: Warning (unit_address_vs_reg):
> /memory: node has a reg or ranges property, but no unit name
>
> The DTB after the change is the same as before except adding
> unit-address to /memory node.
>
> Signed-off-by: Krzysztof Kozlowski
>
Looks good to me! Thanks!
R
ed-off-by: Krzysztof Kozlowski <k...@kernel.org>
That looks good!
Reviewed-by: Stefan Agner <ste...@agner.ch>
Also works fine with full memory available on a 512MiB Colibri T20 using
downstream U-Boot 2016.11.
Tested-by: Stefan Agner <ste...@agner.ch>
--
Stefan
>
> ---
>
igned-off-by: Krzysztof Kozlowski
That looks good!
Reviewed-by: Stefan Agner
Also works fine with full memory available on a 512MiB Colibri T20 using
downstream U-Boot 2016.11.
Tested-by: Stefan Agner
--
Stefan
>
> ---
>
> RFT:
> Not tested on 512 MB module as I have only the 256
Hi Boris,
Thanks for the initial review! One small question below:
On 23.05.2018 16:18, Boris Brezillon wrote:
> Hi Stefan,
>
> On Tue, 22 May 2018 14:07:06 +0200
> Stefan Agner <ste...@agner.ch> wrote:
>> +
>> +struct tegra_nand {
>> +void __
Hi Boris,
Thanks for the initial review! One small question below:
On 23.05.2018 16:18, Boris Brezillon wrote:
> Hi Stefan,
>
> On Tue, 22 May 2018 14:07:06 +0200
> Stefan Agner wrote:
>> +
>> +struct tegra_nand {
>> +void __iomem *regs;
>> +struc
On 23.05.2018 11:56, Krzysztof Kozlowski wrote:
> Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
> (with 1024 MB NAND) flavors. Both of them will use the same DTSI
> expecting the bootloader to do the fixup of /memory node. However in
> case it does not happen, let's stay on
On 23.05.2018 11:56, Krzysztof Kozlowski wrote:
> Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
> (with 1024 MB NAND) flavors. Both of them will use the same DTSI
> expecting the bootloader to do the fixup of /memory node. However in
> case it does not happen, let's stay on
On 23.05.2018 11:56, Krzysztof Kozlowski wrote:
> Add a generic /memory node in each Tegra DTSI (with empty reg property,
> to be overidden by each DTS) and set proper unit address for /memory
> nodes to fix the DTC warnings:
>
> arch/arm/boot/dts/tegra20-harmony.dtb: Warning
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