Quoting Adam Ford (2021-02-07 10:51:39)
> There are two registers which can set the load capacitance for
> XTAL1 and XTAL2. These are optional registers when using an
> external crystal. Parse the device tree and set the
> corresponding registers accordingly.
>
> Signed-off-by: Adam Ford
> ---
Quoting Adam Ford (2021-02-07 10:51:38)
> There are two registers which can set the load capacitance for
> XTAL1 and XTAL2. These are optional registers when using an
> external crystal. Since XTAL1 and XTAL2 will set to the same value,
> update the binding to support a single property called
>
Quoting Lee Jones (2021-01-26 04:45:40)
> Fixes the following W=1 kernel build warning(s):
>
> drivers/clk/zynqmp/divider.c:46: warning: Function parameter or member
> 'max_div' not described in 'zynqmp_clk_divider'
>
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: M
r member 'flags'
> not described in 'xgene_clk_pmd'
>
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Loc Ho
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
Quoting Lee Jones (2021-01-26 04:45:38)
> Fixes the following W=1 kernel build warning(s):
>
> drivers/clk/spear/spear1310_clock.c:385:13: warning: no previous prototype
> for ‘spear1310_clk_init’ [-Wmissing-prototypes]
> drivers/clk/spear/spear1340_clock.c:442:13: warning: no previous
Quoting Lee Jones (2021-01-26 04:45:37)
> Fixes the following W=1 kernel build warning(s):
>
> drivers/clk/qcom/clk-rpm.c:453:29: warning: ‘clk_rpm_branch_ops’ defined but
> not used [-Wunused-const-variable=]
>
> Cc: Andy Gross
> Cc: Bjorn Andersson
> Cc: Michael
:77:32: warning:
> ‘mmcc_xo_mmpll0_1_2_gpll0_map’ defined but not used [-Wunused-const-variable=]
>
> Cc: Andy Gross
> Cc: Bjorn Andersson
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-arm-...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
but not
> used [-Wunused-const-variable=]
>
> Cc: Avi Fishman
> Cc: Tomer Maimon
> Cc: Tali Perry
> Cc: Patrick Venture
> Cc: Nancy Yuen
> Cc: Benjamin Fair
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Nuvoton Technologies
> Cc: open...@lists.ozla
Quoting Lee Jones (2021-01-26 04:45:33)
> Fixes the following W=1 kernel build warning(s):
>
> drivers/clk/clk-fixed-mmio.c:62: warning: Function parameter or member
> 'pdev' not described in 'of_fixed_mmio_clk_probe'
>
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc
xen_round_rate'
>
> Cc: Tero Kristo
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-o...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
> Cc: Andy Gross
> Cc: Bjorn Andersson
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-arm-...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
t; Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Cc: linux-...@vger.kernel.org
> Cc: linux-te...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
riable]
>
> Cc: Peter De Schrijver
> Cc: Prashant Gaikwad
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Cc: linux-...@vger.kernel.org
> Cc: linux-te...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-arm-...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
> 'parent_rate' not described in 'omap3_clkoutx2_recalc'
> drivers/clk/ti/dpll3xxx.c:755: warning: Excess function parameter 'clk'
> description in 'omap3_clkoutx2_recalc'
>
> Cc: Tero Kristo
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-o...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
meter or member
> 'parent_rate' not described in 'omap2_dpll_round_rate'
> drivers/clk/ti/clkt_dpll.c:284: warning: Excess function parameter 'clk'
> description in 'omap2_dpll_round_rate'
>
> Cc: Tero Kristo
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Richard Woodruff
_register_zynq_pll'
> drivers/clk/zynq/pll.c:187: warning: Function parameter or member
> 'lock_index' not described in 'clk_register_zynq_pll'
> drivers/clk/zynq/pll.c:187: warning: Function parameter or member 'lock' not
> described in 'clk_register_zynq_pll'
>
> Cc: Michael T
set but not used
> [-Wunused-but-set-variable]
>
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Michal Simek
> Cc: "Sören Brinkmann"
> Cc: linux-...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
ction parameter 'clk'
> description in 'omap36xx_gate_clk_enable_with_hsdiv_restore'
>
> Cc: Tero Kristo
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-o...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
rning: cannot understand function
> prototype: 'const struct icst_params icst525_apcp_cm_params = '
>
> Cc: Linus Walleij
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
> description in '_register_dpll'
>
> Cc: Tero Kristo
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-o...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
parameter 'clk'
> description in 'omap2_init_clk_clkdm'
>
> Cc: Tero Kristo
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-o...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
s/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member 'pe'
> not described in 'st_clk_quadfs_fsynth'
> drivers/clk/st/clkgen-fsyn.c:466: warning: Function parameter or member
> 'sdiv' not described in 'st_clk_quadfs_fsynth'
>
> Cc: Michael Turquette
> Cc: Stephen B
Quoting Lee Jones (2021-01-20 01:30:31)
> And remove an incorrect entry.
>
> Fixes the following W=1 kernel build warning(s):
>
> drivers/clk/st/clkgen-pll.c:142: warning: cannot understand function
> prototype: 'struct clkgen_pll '
>
> Cc: Michael Turquette
> Cc:
ction parameter or member
> 'ratio_state_offset' not described in 'cpu_dfs_regs'
> drivers/clk/mvebu/ap-cpu-clk.c:52: warning: Function parameter or member
> 'ratio_state_cluster_offset' not described in 'cpu_dfs_regs'
>
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Julia Lawal
]
>
> Cc: Dinh Nguyen
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
Cc: Dinh Nguyen
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
_fu540’ defined but
> not used [-Wunused-const-variable=]
>
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Paul Walmsley
> Cc: Palmer Dabbelt
> Cc: Pragnesh Patel
> Cc: Zong Li
> Cc: linux-...@vger.kernel.org
> Cc: linux-ri...@lists.infradead.org
> Signed-off-by: Lee Jones
> ---
Applied to clk-next
Quoting Lee Jones (2021-01-20 01:30:25)
> Fixes the following W=1 kernel build warning(s):
>
> drivers/clk/bcm/clk-iproc-pll.c:712: warning: Function parameter or member
> 'pll' not described in 'iproc_pll_sw_cfg'
>
> Cc: Michael Turquette
> Cc: Stephen Boyd
>
Quoting Lee Jones (2021-01-26 04:45:27)
> Fixes the following W=1 kernel build warning(s):
>
> drivers/clk/clkdev.c: In function ‘vclkdev_alloc’:
> drivers/clk/clkdev.c:173:3: warning: function ‘vclkdev_alloc’ might be a
> candidate for ‘gnu_printf’ format attribute
Quoting Viresh Kumar (2021-01-31 20:22:58)
> Not all devices that need to use OPP core need to have clocks, a missing
> clock is fine in which case -ENOENT shall be returned by clk_get().
>
> Anything else is an error and must be handled properly.
>
> Reported-by: Dmitry Osipenko
>
Quoting Matthias Kaehlcke (2021-02-10 14:20:18)
>
> On Wed, Feb 10, 2021 at 10:06:45PM +0100, Krzysztof Kozlowski wrote:
> >
> > This looks hackish... what if later we have something else than hub?
> > Another if()?
> >
> > What if hub could be connected to something else than XHCI controller?
Quoting Michael Tretter (2021-02-10 23:39:06)
> On Wed, 10 Feb 2021 19:28:18 -0800, Stephen Boyd wrote:
> > Quoting Colin King (2021-02-10 10:49:38)
> > > From: Colin Ian King
> > >
> > > The pointer 'divider' has previously been null checked followed by
>
Quoting Greg Kroah-Hartman (2021-02-11 06:23:10)
> On Wed, Feb 10, 2021 at 04:36:08PM -0800, Stephen Boyd wrote:
> > Quoting Greg Kroah-Hartman (2020-12-09 06:51:33)
> > > On Tue, Dec 08, 2020 at 01:20:56PM -0800, Kees Cook wrote:
> > > > On Mon, Dec 07, 2020 at
Quoting Colin King (2021-02-10 10:49:38)
> From: Colin Ian King
>
> The pointer 'divider' has previously been null checked followed by
> a return, hence the subsequent null check is redundant deadcode
> that can be removed. Clean up the code and remove it.
>
> Fixes: 9c789deea206 ("soc:
Quoting Laurent Pinchart (2021-01-23 10:42:27)
> Hi Stephen,
>
> On Tue, Jun 25, 2019 at 08:52:45PM -0700, Stephen Boyd wrote:
> > Quoting Weiyi Lu (2019-06-25 18:05:22)
> > > On Tue, 2019-06-25 at 15:14 -0700, Stephen Boyd wrote:
> > > > Quoting Weiyi Lu
ned-off-by: JC Kuo
> Acked-by: Thierry Reding
> ---
Acked-by: Stephen Boyd
driver to enable
>PLLE hardware sequencer at proper time.
>
> 2. tegra210_plle_hw_sequence_is_enabled() for XUSB PADCTL driver to
>check whether PLLE hardware sequencer has been enabled or not.
>
> Signed-off-by: JC Kuo
> Acked-by: Thierry Reding
> ---
Acked-by: Stephen Boyd
Quoting Dinh Nguyen (2021-01-05 11:29:56)
> Add support for Intel's eASIC N5X platform. The clock manager driver for
> the N5X is very similar to the Agilex platform, we can re-use most of
> the Agilex clock driver.
>
> This patch makes the necessary changes for the driver to differentiate
>
Quoting Daniel Palmer (2021-02-10 18:28:40)
> Hi Stephen,
>
> On Wed, 10 Feb 2021 at 11:29, Stephen Boyd wrote:
> > The child clks should be using clk_parent_data to point to the parent
> > clks through DT. That way the name of the clk doesn't matter except for
> > deb
g far away it sets the switch bit to 0. For now this driver
exposes a single sensor, but it could be expanded in the future via more
MKBP bits if desired.
Cc: Dmitry Torokhov
Cc: Benson Leung
Cc: Guenter Roeck
Cc: Douglas Anderson
Cc: Gwendal Grignou
Reviewed-by: Enric Balletbo i Serra
Signed-off-b
Roeck
Cc: Douglas Anderson
Cc: Gwendal Grignou
Cc:
Reviewed-by: Rob Herring
Cc: Enric Balletbo i Serra
Signed-off-by: Stephen Boyd
---
.../google,cros-ec-mkbp-proximity.yaml| 37 +++
.../bindings/mfd/google,cros-ec.yaml | 7
2 files changed, 44
Some cros ECs support a front proximity MKBP event via
'EC_MKBP_FRONT_PROXIMITY'. Add this define so it can be used in a
future patch.
Cc: Dmitry Torokhov
Cc: Benson Leung
Cc: Guenter Roeck
Cc: Douglas Anderson
Cc: Gwendal Grignou
Acked-by: Enric Balletbo i Serra
Signed-off-by: Stephen Boyd
* Dropped CONFIG_OF usage
* Sorted includes
[1] https://lore.kernel.org/r/20201205004709.3126266-1-swb...@chromium.org
Cc: Dmitry Torokhov
Cc: Benson Leung
Cc: Guenter Roeck
Cc: Douglas Anderson
Cc: Gwendal Grignou
Cc:
Cc: Rob Herring
Cc: Enric Balletbo i Serra
Stephen Boyd (3):
platform
Quoting Adam Ford (2021-02-10 12:40:38)
> On Wed, Feb 10, 2021 at 2:18 PM Rob Herring wrote:
> >
> > On Sun, Feb 07, 2021 at 12:51:38PM -0600, Adam Ford wrote:
> > > There are two registers which can set the load capacitance for
> > > XTAL1 and XTAL2. These are optional registers when using an
>
Quoting Maxime Ripard (2021-02-10 02:29:04)
> Hi Mike, Stephen,
>
> On Tue, Feb 09, 2021 at 06:58:56PM +0100, Jernej Skrabec wrote:
> > CLK_SET_RATE_PARENT flag is checked on parent clock instead of current
> > one. Fix that.
> >
> > Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent
which calls
into regular instrumentable text section as safe.
The instrumentation markers are only active when CONFIG_DEBUG_ENTRY is
enabled as the end marker emits a NOP to prevent the compiler from merging
the annotation points. This means the objtool verification requires a
kernel comp
Quoting Gwendal Grignou (2021-02-10 00:29:45)
> On Tue, Feb 9, 2021 at 6:51 PM Stephen Boyd wrote:
> > + if (event_type == EC_MKBP_EVENT_SWITCH) {
> > + data = container_of(nb, struct cros_ec_mkbp_proximity_data,
> > +
Some cros ECs support a front proximity MKBP event via
'EC_MKBP_FRONT_PROXIMITY'. Add this define so it can be used in a
future patch.
Cc: Dmitry Torokhov
Cc: Benson Leung
Cc: Guenter Roeck
Cc: Douglas Anderson
Cc: Gwendal Grignou
Acked-by: Enric Balletbo i Serra
Signed-off-by: Stephen Boyd
g far away it sets the switch bit to 0. For now this driver
exposes a single sensor, but it could be expanded in the future via more
MKBP bits if desired.
Cc: Dmitry Torokhov
Cc: Benson Leung
Cc: Guenter Roeck
Cc: Douglas Anderson
Cc: Gwendal Grignou
Reviewed-by: Enric Balletbo i Serra
Signed-off-b
Roeck
Cc: Douglas Anderson
Cc: Gwendal Grignou
Cc:
Cc: Rob Herring
Cc: Enric Balletbo i Serra
Signed-off-by: Stephen Boyd
---
Changes from v4:
* Reduced example in iio binding and moved to mfd
* Dropped unevaluatedProperties
.../google,cros-ec-mkbp-proximity.yaml| 37
...@chromium.org
Cc: Dmitry Torokhov
Cc: Benson Leung
Cc: Guenter Roeck
Cc: Douglas Anderson
Cc: Gwendal Grignou
Cc:
Cc: Rob Herring
Cc: Enric Balletbo i Serra
Stephen Boyd (3):
platform/chrome: cros_ec: Add SW_FRONT_PROXIMITY MKBP define
dt-bindings: iio: Add cros ec proximity yaml doc
iio
Quoting Stephen Boyd (2021-02-06 19:21:39)
> Quoting Jonathan Cameron (2021-02-06 08:17:11)
> > On Tue, 2 Feb 2021 10:44:34 -0800
> > Stephen Boyd wrote:
> >
> > > +static struct platform_driver cros_ec_mkbp_proximity_driver = {
> > > + .driver = {
&g
Quoting Rob Herring (2021-02-09 13:13:47)
> On Tue, Feb 02, 2021 at 10:44:33AM -0800, Stephen Boyd wrote:
> > +description: Name for proximity sensor
> > +
> > +required:
> > + - compatible
> > +
> > +unevaluatedProperties: false
> > +a
Quoting Daniel Palmer (2020-12-21 00:51:56)
> Hi Stephen,
>
> On Mon, 21 Dec 2020 at 03:44, Stephen Boyd wrote:
> >
> > Quoting Daniel Palmer (2020-12-19 22:35:41)
> > > Hi Stephen,
> > >
> > > On Sun, 20 Dec 2020 at 12:39, Step
gt;
> Signed-off-by: Marek Behún
> Signed-off-by: Pali Rohár
> Fixes: 61c40f35f5cd ("clk: mvebu: armada-37xx-periph: Fix switching CPU rate
> from 300Mhz to 1.2GHz")
> Cc: sta...@vger.kernel.org
> ---
Acked-by: Stephen Boyd
armada-37xx-periph: add DVFS support for
> cpu clocks")
> Cc: sta...@vger.kernel.org # 61c40f35f5cd ("clk: mvebu: armada-37xx-periph:
> Fix switching CPU rate from 300Mhz to 1.2GHz")
> ---
Acked-by: Stephen Boyd
After this was fixed in the cpufreq driver, this method is not
> needed anymore.
>
> Signed-off-by: Marek Behún
> Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for
> cpu clocks")
> Cc: Gregory CLEMENT
> Cc: Miquel Raynal
> ---
Acked-by: Stephen Boyd
Quoting Tudor Ambarus (2021-02-03 07:43:32)
> These are all "early clocks" that require initialization just at
> of_clk_init() time. Use CLK_OF_DECLARE() to declare them.
>
> This also fixes a problem that was spotted when fw_devlink was
> set to 'on' by default: the boards failed to boot. The
Quoting tudor.amba...@microchip.com (2021-02-08 01:49:45)
> Hi, Michael, Stephen,
>
> Do you plan to take this patch for v5.12?
> If fw_devlink will remain set to ON for v5.12, some of our boards will
> no longer boot without this patch.
Is fw_devlink defaulted to on for v5.12?
Quoting gabriel.fernan...@foss.st.com (2021-01-26 01:01:08)
> From: Gabriel Fernandez
>
> 'ck_rtc' has multiple clocks as input (ck_hsi, ck_lsi, and ck_hse).
> A divider is available only on the specific rtc input for ck_hse.
> This Merge will facilitate to have a more coherent clock tree
> in
Quoting Saravana Kannan (2021-01-28 09:01:41)
> On Thu, Jan 28, 2021 at 2:45 AM Tudor Ambarus
> wrote:
> >
> > The sama5d2 requires the clock provider initialized before timers.
> > We can't use a platform driver for the sama5d2-pmc driver, as the
> > platform_bus_init() is called later on, after
Quoting (2021-01-31 09:04:28)
> This clock must be always enabled to allow access to any registers in
> fsys1 CMU. Until proper solution based on runtime PM is applied
> (similar to what was done for Exynos5433), fix this by calling
> clk_prepare_enable() directly from clock provider driver.
>
>
Quoting Enric Balletbo i Serra (2021-02-03 02:54:23)
> If MT8183 SoC support is enabled, almost all machines will use topckgen,
> apmixedsys, infracfg, mcucfg and subsystem clocks, so it feels wrong to
> require each one to select that symbols manually.
>
> Instead, enable it whenever
Quoting Alexandru Ardelean (2021-02-01 07:12:45)
> No major functional change. Noticed while checking the driver code that
> this could be used.
> Saves two lines.
>
> Signed-off-by: Alexandru Ardelean
> ---
Applied to clk-next
Quoting Alexandru Ardelean (2021-02-01 07:12:44)
> The axi-clkgen driver now supports ZynqMP (UltraScale) as well, however the
> driver needs to use different PFD & VCO limits.
>
> For ZynqMP, these needs to be selected by using the
> 'adi,zynqmp-axi-clkgen-2.00.a' string.
>
> Signed-off-by:
Quoting Alexandru Ardelean (2021-02-01 07:12:43)
> For ZynqMP (Ultrascale) the PFD and VCO limits are different. In order to
> support these, this change adds a compatible string (i.e.
> 'adi,zynqmp-axi-clkgen-2.00.a') which will take into account for these
> limits and apply them.
>
>
Quoting Alexandru Ardelean (2021-02-01 07:12:42)
> The intent is to be able to run this driver to access the IP core in setups
> where FPGA board is also connected via a PCIe bus. In such cases the number
> of combinations explodes, where the host system can be an x86 with Xilinx
>
Quoting Weiyi Lu (2020-12-22 05:09:25)
> This series is based on v5.10-rc1.
>
The DT bindings fail, can you fix and resend?
Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml:
'additionalProperties' is a required property
Quoting Maulik Shah (2021-02-04 06:21:46)
> From: Mahesh Sivasubramanian
>
> Let's add a driver to read the stats from remote processor and
> export to debugfs.
>
> The driver creates "qcom_sleep_stats" directory in debugfs and
> adds files for various low power mode available. Below is sample
Quoting Maulik Shah (2021-02-04 06:21:45)
> +
> +description:
> + Always On Processor/Resource Power Manager maintains statistics of the SoC
> + sleep modes involving powering down of the rails and oscillator clock.
> +
> + Statistics includes SoC sleep mode type, number of times low power mode
Quoting Hsin-Hsiung Wang (2021-02-06 21:19:13)
> diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
> index a53bad541f1a..418848840999 100644
> --- a/drivers/spmi/Kconfig
> +++ b/drivers/spmi/Kconfig
> @@ -25,4 +25,13 @@ config SPMI_MSM_PMIC_ARB
> This is required for communicating
Quoting Mauro Carvalho Chehab (2021-01-29 11:51:57)
> The Hisilicon 6421v600 SPMI driver is ready for mainstream.
>
> So, move it from staging.
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
Acked-by: Stephen Boyd
Rob had some comments on the binding that don't look to be a
Quoting Subbaraman Narayanamurthy (2021-02-08 11:33:04)
> Currently, when handling the SPMI summary interrupt, the hw_irq
> number is calculated based on SID, Peripheral ID, IRQ index and
> APID. This is then passed to irq_find_mapping() to see if a
> mapping exists for this hw_irq and if
ned-off-by: JC Kuo
> Acked-by: Thierry Reding
> ---
Acked-by: Stephen Boyd
Quoting Abel Vesa (2021-01-13 04:53:08)
> Add a section for NXP i.MX clock drivers and list myself
> as the maintainer.
>
> Signed-off-by: Abel Vesa
> ---
Applied to clk-next
driver to enable
>PLLE hardware sequencer at proper time.
>
> 2. tegra210_plle_hw_sequence_is_enabled() for XUSB PADCTL driver to
>check whether PLLE hardware sequencer has been enabled or not.
>
> Signed-off-by: JC Kuo
> Acked-by: Thierry Reding
> ---
Acked-by: Stephen Boyd
Quoting Jernej Skrabec (2021-02-08 04:17:48)
> CLK_SET_RATE_PARENT flag is checked on parent clock instead of current
> one. Fix that.
>
> Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when
> allowed")
> Reviewed-by: Chen-Yu Tsai
> Tested-by: Andre Heider
> Signed-off-by:
Quoting Joe Perches (2021-02-06 21:06:54)
> On Sat, 2021-02-06 at 20:18 -0800, Stephen Boyd wrote:
> > A missing semicolon here causes my external display to stop working.
> > Indeed, missing the semicolon on the return statement leads to
> > dp_panel_update_tu_timings()
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:59)
> The GPU PLL0 is not a fixed PLL and the rate can be set on it:
> this is necessary especially on boards which bootloader is setting
> a very low rate on this PLL before booting Linux, which would be
> unsuitable for postdividing to reach
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:59)
> The GPU PLL0 is not a fixed PLL and the rate can be set on it:
> this is necessary especially on boards which bootloader is setting
> a very low rate on this PLL before booting Linux, which would be
> unsuitable for postdividing to reach
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:58)
> The GPU GX GDSC has GPU_GX_BCR reset and gfx3d_clk CXC, as stated
> on downstream kernels (and as verified upstream, because otherwise
> random lockups happen).
> Also, add PWRSTS_RET and NO_RET_PERIPH: also as found downstream,
> and also
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:57)
> This GDSC enables (or cuts!) power to the Multimedia Subsystem IOMMU
> (mmss smmu), which has bootloader pre-set secure contexts.
> In the event of a complete power loss, the secure contexts will be
> reset and the hypervisor will crash
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:56)
> Hardware clock gating is supported on some of the clocks declared in
> there: ignoring that it does exist may lead to unstabilities on some
> firmwares.
> Add the HWCG registers where applicable to stop potential crashes.
>
> This was
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:55)
> The pixel and byte clocks rate should not be cached, as a VCO shutdown
> may clear the frequency setup and this may not be set again due to the
> cached rate being present.
> This will also be useful when shadow clocks will be implemented
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:55)
> The pixel and byte clocks rate should not be cached, as a VCO shutdown
> may clear the frequency setup and this may not be set again due to the
> cached rate being present.
> This will also be useful when shadow clocks will be implemented
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:53)
> The GPU IOMMU depends on this clock and the hypervisor will crash
> the SoC if this clock gets disabled because the secure contexts
> that have been set on this IOMMU by the bootloader will become
> unaccessible (or they get reset).
> Mark
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:54)
> All of the GPLLs in the MSM8998 Global Clock Controller are Fabia PLLs
> and not generic alphas: this was producing bad effects over the entire
> clock tree of MSM8998, where any GPLL child clock was declaring a false
> clock rate, due to
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:52)
> To achieve CPR-Hardened functionality this clock must be on: add it
> in order to be able to get it managed by the CPR3 driver.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
Applied to clk-next
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:51)
> Add new clock definition to gcc-msm8998 dt-bindings
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
Applied to clk-next
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:50)
> This clock enables the GPLL0 output to the multimedia subsystem
> clock controller.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
Applied to clk-next
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:49)
> Add new clock definition to gcc-msm8998 dt-bindings.
>
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
Applied to clk-next
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:53)
> The GPU IOMMU depends on this clock and the hypervisor will crash
> the SoC if this clock gets disabled because the secure contexts
> that have been set on this IOMMU by the bootloader will become
> unaccessible (or they get reset).
> Mark
Quoting Konrad Dybcio (2021-01-30 17:30:09)
> Add support for RPM-managed clocks on the MDM9607 platform.
>
> Signed-off-by: Konrad Dybcio
> ---
> .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
> drivers/clk/qcom/clk-smd-rpm.c| 32 +++
> 2 files changed,
Quoting Vinod Koul (2021-01-26 23:08:07)
> Driver uses regval variable for holding register values, replace with a
> shorter one val
>
> Suggested-by: Stephen Boyd
> Reviewed-by: Bjorn Andersson
> Signed-off-by: Vinod Koul
> ---
Applied to clk-next
Quoting Vinod Koul (2021-01-26 23:08:11)
> From: Vivek Aknurwar
>
> This adds Global Clock controller (GCC) driver for SM8350 SoC
>
> Signed-off-by: Vivek Aknurwar
> Signed-off-by: Jeevan Shriram
> [vkoul: rebase and tidy up for upstream]
> Signed-off-by: Vinod Koul
> Reviewed-by: Bjorn
Quoting Vinod Koul (2021-01-26 23:08:09)
> From: Vivek Aknurwar
>
> Lucid 5LPE is a slightly different Lucid PLL with different offsets and
> porgramming sequence so add support for these
>
> Signed-off-by: Vivek Aknurwar
> Signed-off-by: Jeevan Shriram
> [vkoul: rebase and tidy up for
Quoting Vinod Koul (2021-01-26 23:08:08)
> Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but
> with different registers. Modularize these by moving out latch and latch
> ack bits so that we can reuse the function.
>
> Suggested-by: AngeloGioacchino Del Regno
>
>
Quoting Vinod Koul (2021-01-26 23:08:10)
> Add device tree bindings for global clock controller on SM8350 SoCs.
>
> Reviewed-by: Rob Herring
> Reviewed-by: Bjorn Andersson
> Signed-off-by: Vinod Koul
> ---
Applied to clk-next
Quoting Bjorn Andersson (2021-01-25 20:31:55)
> Add clocks, resets and some of the GDSC provided by the global clock
> controller found in the Qualcomm SC8180x platform.
>
> Signed-off-by: Bjorn Andersson
> ---
Applied to clk-next
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