On 8/10/2017 9:46 AM, Ingo Molnar wrote:
>
> * Matt Fleming <m...@codeblueprint.co.uk> wrote:
>
>> On Wed, 02 Aug, at 11:41:38AM, Stuart Hayes wrote:
>>> (Resend because I mistyped the maintainer's email address the first time.)
>>>
>>> The ker
On 8/10/2017 9:46 AM, Ingo Molnar wrote:
>
> * Matt Fleming wrote:
>
>> On Wed, 02 Aug, at 11:41:38AM, Stuart Hayes wrote:
>>> (Resend because I mistyped the maintainer's email address the first time.)
>>>
>>> The kernel's EFI stub locates and co
update [mem 0x60ef4000-0x60f4cfff] usable ==> usable
...
PM: Registered nosave memory: [mem 0x-0x0fff]
PM: Registered nosave memory: [mem 0x000a-0x000f]
PM: Registered nosave memory: [mem 0x6cf6e000-0x6f3ccfff]
Signed-off-by: Stuart Hayes <stuart.w.ha...@gmail.com>
update [mem 0x60ef4000-0x60f4cfff] usable ==> usable
...
PM: Registered nosave memory: [mem 0x-0x0fff]
PM: Registered nosave memory: [mem 0x000a-0x000f]
PM: Registered nosave memory: [mem 0x6cf6e000-0x6f3ccfff]
Signed-off-by: Stuart Hayes
---
Changes in V2:
Update the
=> usable
e820: update [mem 0x60f4d000-0x60fa5fff] usable ==> usable
e820: update [mem 0x60ef4000-0x60f4cfff] usable ==> usable
...
PM: Registered nosave memory: [mem 0x-0x0fff]
PM: Registered nosave memory: [mem 0x000a-0x000f]
PM: Registered nosave memory: [mem 0x6cf6e00
=> usable
e820: update [mem 0x60f4d000-0x60fa5fff] usable ==> usable
e820: update [mem 0x60ef4000-0x60f4cfff] usable ==> usable
...
PM: Registered nosave memory: [mem 0x-0x0fff]
PM: Registered nosave memory: [mem 0x000a-0x000f]
PM: Registered nosave memory: [mem 0x6cf6e00
update [mem 0x60ef4000-0x60f4cfff] usable ==> usable
...
PM: Registered nosave memory: [mem 0x-0x0fff]
PM: Registered nosave memory: [mem 0x000a-0x000f]
PM: Registered nosave memory: [mem 0x6cf6e000-0x6f3ccfff]
Signed-off-by: Stuart Hayes <stuart.w.ha...@gmail.com
update [mem 0x60ef4000-0x60f4cfff] usable ==> usable
...
PM: Registered nosave memory: [mem 0x-0x0fff]
PM: Registered nosave memory: [mem 0x000a-0x000f]
PM: Registered nosave memory: [mem 0x6cf6e000-0x6f3ccfff]
Signed-off-by: Stuart Hayes
---
--- linux-4.13-rc2/arch/x86/boot
On 5/26/2016 11:38 AM, Stuart Hayes wrote:
Add the Microsoft _DSM command set to the white list of NVDIMM command sets.
This command set is documented at
https://msdn.microsoft.com/library/windows/hardware/mt604741.
Signed-off-by: Stuart Hayes <stuart.w.ha...@gmail.com>
---
driver
On 5/26/2016 11:38 AM, Stuart Hayes wrote:
Add the Microsoft _DSM command set to the white list of NVDIMM command sets.
This command set is documented at
https://msdn.microsoft.com/library/windows/hardware/mt604741.
Signed-off-by: Stuart Hayes
---
drivers/acpi/nfit.c| 9
Add the Microsoft _DSM command set to the white list of NVDIMM command sets.
This command set is documented at
https://msdn.microsoft.com/library/windows/hardware/mt604741.
Signed-off-by: Stuart Hayes <stuart.w.ha...@gmail.com>
---
drivers/acpi/nfit.c| 9 ++---
drivers/acpi/
Add the Microsoft _DSM command set to the white list of NVDIMM command sets.
This command set is documented at
https://msdn.microsoft.com/library/windows/hardware/mt604741.
Signed-off-by: Stuart Hayes
---
drivers/acpi/nfit.c| 9 ++---
drivers/acpi/nfit.h| 4
include
>>
>> Linux drivers no longer use MTRR so why is the cleanup needed, ie, what would
>> happen if the cleanup is just skipped in your case ?
>
> The infiniband & video drivers still use MTRR (or at least it was my
> understanding that they do). In any case, Stuart -- could you try booting
>
>>
>> Linux drivers no longer use MTRR so why is the cleanup needed, ie, what would
>> happen if the cleanup is just skipped in your case ?
>
> The infiniband & video drivers still use MTRR (or at least it was my
> understanding that they do). In any case, Stuart -- could you try booting
>
of, say, 256GB, and ten variable
MTRRs (such as some recent Intel CPUs have), it is not possible to set up
the MTRRs to cover all of memory.
Signed-off-by: Stuart Hayes
---
--- linux-4.2-rc7/arch/x86/kernel/cpu/mtrr/cleanup.c.orig 2015-08-16
18:34:13.0 -0500
+++ linux-4.2-rc7/arch
of, say, 256GB, and ten variable
MTRRs (such as some recent Intel CPUs have), it is not possible to set up
the MTRRs to cover all of memory.
Signed-off-by: Stuart Hayes <stuart.w.ha...@gmail.com>
---
--- linux-4.2-rc7/arch/x86/kernel/cpu/mtrr/cleanup.c.orig 2015-08-16
18:34:13.0
On 7/8/2014 5:38 PM, H. Peter Anvin wrote:
> On 07/08/2014 03:34 PM, Stuart Hayes wrote:
>>
>> I haven't received any responses... is there a problem with the patch? Also
>> CCing a couple people.
>>
>
> I was on vacation last week and am still catching u
On 7/8/2014 5:38 PM, H. Peter Anvin wrote:
On 07/08/2014 03:34 PM, Stuart Hayes wrote:
I haven't received any responses... is there a problem with the patch? Also
CCing a couple people.
I was on vacation last week and am still catching up.
It would also help if you describe the real
On 7/2/2014 8:47 PM, Stuart Hayes wrote:
> A page fault can crash the kernel very early if an NX bit is set in a
> page table entry, if the CPU doesn't support NX (or if NX support is
> disabled in the CPU). Move the call to x86_configure_nx() earlier
> than parse_setup_data(), sinc
not mapping the pages at all.
Signed-off-by: Stuart Hayes
---
--- linux-3.16-rc3/arch/x86/mm/pageattr.c.orig 2014-07-02 12:04:49.244288159
-0400
+++ linux-3.16-rc3/arch/x86/mm/pageattr.c 2014-07-02 12:05:55.808290437
-0400
@@ -1862,10 +1862,7 @@ int kernel_map_pages_in_pgd(pgd_t *pgd
not mapping the pages at all.
Signed-off-by: Stuart Hayes stuart.w.ha...@gmail.com
---
--- linux-3.16-rc3/arch/x86/mm/pageattr.c.orig 2014-07-02 12:04:49.244288159
-0400
+++ linux-3.16-rc3/arch/x86/mm/pageattr.c 2014-07-02 12:05:55.808290437
-0400
@@ -1862,10 +1862,7 @@ int
On 7/2/2014 8:47 PM, Stuart Hayes wrote:
A page fault can crash the kernel very early if an NX bit is set in a
page table entry, if the CPU doesn't support NX (or if NX support is
disabled in the CPU). Move the call to x86_configure_nx() earlier
than parse_setup_data(), since that calls
A page fault can crash the kernel very early if an NX bit is set in a
page table entry, if the CPU doesn't support NX (or if NX support is
disabled in the CPU). Move the call to x86_configure_nx() earlier
than parse_setup_data(), since that calls early_memremap().
Signed-off-by: Stuart Hayes
A page fault can crash the kernel very early if an NX bit is set in a
page table entry, if the CPU doesn't support NX (or if NX support is
disabled in the CPU). Move the call to x86_configure_nx() earlier
than parse_setup_data(), since that calls early_memremap().
Signed-off-by: Stuart Hayes
Commit-ID: 6c6c0d5a1c949d2e084706f9e5fb1fccc175b265
Gitweb: http://git.kernel.org/tip/6c6c0d5a1c949d2e084706f9e5fb1fccc175b265
Author: Stuart Hayes
AuthorDate: Tue, 29 Apr 2014 17:55:02 -0500
Committer: Thomas Gleixner
CommitDate: Wed, 30 Apr 2014 12:34:51 +0200
hrtimer: Prevent all
Commit-ID: 6c6c0d5a1c949d2e084706f9e5fb1fccc175b265
Gitweb: http://git.kernel.org/tip/6c6c0d5a1c949d2e084706f9e5fb1fccc175b265
Author: Stuart Hayes stuart.w.ha...@gmail.com
AuthorDate: Tue, 29 Apr 2014 17:55:02 -0500
Committer: Thomas Gleixner t...@linutronix.de
CommitDate: Wed, 30 Apr
event device
interrupts occur and no timer expiration functions are run.
Signed-off-by: Stuart Hayes
---
--- linux-3.15-rc3/kernel_orig/hrtimer.c2014-04-29 13:10:58.087832963
-0400
+++ linux-3.15-rc3/kernel/hrtimer.c 2014-04-29 15:42:49.581084736 -0400
@@ -569,6 +569,15
event device
interrupts occur and no timer expiration functions are run.
Signed-off-by: Stuart Hayes stuart.w.ha...@gmail.com
---
--- linux-3.15-rc3/kernel_orig/hrtimer.c2014-04-29 13:10:58.087832963
-0400
+++ linux-3.15-rc3/kernel/hrtimer.c 2014-04-29 15:42:49.581084736 -0400
Andi Kleen wrote:
> I personally wouldn't like doing this NX cleanup very late like you did but
> instead directly after the early NX setup.
I've thought about it more, and come up with another patch. All it does is
sets up the PTEs correctly from the beginning, breaking up large pages if
Andi Kleen wrote:
I personally wouldn't like doing this NX cleanup very late like you did but
instead directly after the early NX setup.
I've thought about it more, and come up with another patch. All it does is
sets up the PTEs correctly from the beginning, breaking up large pages if
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