Michael S. Tsirkin
Cc: Yishai Hadas
Cc: Alex Williamson
Cc: Jean-Philippe Brucker
Reviewed-by: Jean-Philippe Brucker
Acked-by: Michael S. Tsirkin
Signed-off-by: Suzuki K Poulose
---
Changes since v1:
- Fix description for the "Fixes" tag format
- Collect Tags from Jean-Philippe and
On 19/04/2021 14:21, Yicong Yang wrote:
On 2021/4/19 19:17, Suzuki K Poulose wrote:
On 17/04/2021 11:17, Yicong Yang wrote:
[RESEND with perf and coresight folks Cc'ed]
HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
integrated Endpoint (RCiEP) device, providing
On 17/04/2021 11:17, Yicong Yang wrote:
[RESEND with perf and coresight folks Cc'ed]
HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
integrated Endpoint (RCiEP) device, providing the capability
to dynamically monitor and tune the PCIe traffic (tune),
and trace the TLP headers
Hi
On 15/04/2021 10:33, Tao Zhang wrote:
Current coresight implementation only supports enabling source
ETMs or STM. This patch adds support to enable more kinds of
coresight source to sink paths. We build a path from source to
sink when any source is enabled and store it in a list. When the
On 14/04/2021 15:39, James Clark wrote:
The following attribute is set when synthesising samples in
timed decoding mode:
attr.sample_type |= PERF_SAMPLE_TIME;
This results in new samples that appear to have timestamps but
because we don't assign any timestamps to the samples, when the
On 09/04/2021 11:37, Mike Leach wrote:
Adds in handlers to allow the ETMv4 to use the complex configuration
support. Features and configurations can be loaded and selected in the
device.
Signed-off-by: Mike Leach
Reviewed-by: Mathieu Poirier
---
drivers/hwtracing/coresight/Makefile
Document the device tree bindings for Trace Buffer Extension (TRBE).
Cc: Anshuman Khandual
Cc: Mathieu Poirier
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Rob Herring
Signed-off-by: Suzuki K Poulose
---
.../devicetree/bindings/arm/trbe.yaml | 49
From: Anshuman Khandual
Add documentation for the TRBE under trace/coresight.
Cc: Jonathan Corbet
Cc: linux-...@vger.kernel.org
Reviewed-by: Mathieu Poirier
Signed-off-by: Anshuman Khandual
[ Split from the TRBE driver patch ]
Signed-off-by: Suzuki K Poulose
---
.../trace/coresight
From: Anshuman Khandual
Add sysfs ABI documentation for the TRBE devices.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Jonathan Corbet
Cc: linux-...@vger.kernel.org
Reviewed-by: Mathieu Poirier
Signed-off-by: Anshuman Khandual
[ Split from the TRBE driver patch ]
Signed-off-by: Suzuki K Poulose
Herring
Signed-off-by: Suzuki K Poulose
---
.../devicetree/bindings/arm/ete.yaml | 75 +++
MAINTAINERS | 1 +
2 files changed, 76 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml
diff --git a/Documentation
errors and when the buffer
is full. Overall implementation here is inspired from the Arm SPE driver.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
[ Mark the buffer truncated on WRAP event, error code cleanup ]
Signed-off-by: Suzuki K Poulose
s centrally handled by the etm-perf.
Cc: Mathieu Poirier
Cc: Anshuman Khandual
Cc: Leo Yan
Cc: Mike Leach
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../hwtracing/coresight/coresight-etm-perf.c | 59 +--
1 file changed, 54
device. But such connections are not present for certain
percpu source and sink devices which are exclusively linked and dependent.
Build the path directly and skip connection scanning for such devices.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Tested-by: Suzuki K Poulose
Reviewed
.
Cc: Mike Leach
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/Kconfig | 10 ++--
.../coresight/coresight-etm4x-core.c | 58 ++-
.../coresight/coresight-etm4x-sysfs.c | 19
ETE may not implement the OS lock and instead could rely on
the PE OS Lock for the trace unit access. This is indicated
by the TRCOLSR.OSM == 0b100. Add support for handling the
PE OS lock
Cc: Mike Leach
Reviewed-by: mike.leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 32 +++
drivers/hwtracing/coresight/coresight-etm4x.h | 54 +++
2 files changed, 77 insertions(+), 9 deletions(-)
diff --git a/drivers/hwtracing
this is mandatory, the device will not be usable
as before this patch. Updating the DT bindings to Yaml and enabling
the schema checks can detect such issues with the DT.
Cc: Mike Leach
Cc: Leo Yan
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight
Marc Zyngier
Cc: Mark Rutland
Cc: Anshuman Khandual
Acked-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/el2_setup.h | 13
arch/arm64/include/asm/kvm_arm.h | 2 ++
arch/arm64/include/asm/kvm_host.h | 3 +++
arch/arm64/kernel/hyp-stub.S
If the CPU implements Arm v8.4 Trace filter controls (FEAT_TRF),
move the ETM to trace prohibited region using TRFCR, while disabling.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Anshuman Khandual
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
for a single
event is complex and is not something that we expect
on a sane configuration.
Cc: Anshuman Khandual
Reviewed-by: Mathieu Poirier
Reviewed-by: Mike Leach
Tested-by: Linu Cherian
Signed-off-by: Suzuki K Poulose
---
.../hwtracing/coresight/coresight-etm-perf.c | 60 +
From: Anshuman Khandual
This adds TRBE related registers and corresponding feature macros.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Reviewed-by: Suzuki K Poulose
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Acked-by: Catalin Marinas
Signed-off-by: Anshuman Khandual
tsb csync synchronizes the trace operation of instructions.
The instruction is a nop when FEAT_TRF is not implemented.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Catalin Marinas
Cc: Will Deacon
Acked-by: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/barrier.h | 1
. This will also be useful
for adding the TRBE support.
Cc: Marc Zyngier
Cc: Will Deacon
Cc: Alexandru Elisei
Cc: James Morse
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_host.h | 5 +
arch/arm64/kvm/arm.c | 2 ++
arch/arm64/kvm/debug.c | 23
Rather than falling to an "unhandled access", inject add an explicit
"undefined access" for TRFCR_EL1 access from the guest.
Cc: Marc Zyngier
Cc: Will Deacon
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/kvm/sys_regs.c | 1 +
1 file changed, 1 inse
Cc: Peter Zijlstra
Cc: Mike Leach
Cc: Mathieu Poirier
Cc: Leo Yan
Cc: Anshuman Khandual
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
include/uapi/linux/perf_event.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/uapi/linux/per
arm.com
Cc: mike.le...@linaro.org
Cc: a...@kernel.org
Cc: jo...@redhat.com
Cc: Mathieu Poirier
Reviewed by: Mike Leach
Acked-by: Peter Ziljstra
Signed-off-by: Suzuki K Poulose
---
include/uapi/linux/perf_event.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
m Suzuki apart from splitting of the
ETE DTS patch
- TRBE changes have been captured in the respective patches
RFC:
https://lore.kernel.org/linux-arm-kernel/1605012309-24812-1-git-send-email-anshuman.khand...@arm.com/
Cc: Will Deacon
Cc: Marc Zyngier
Cc: Peter Zilstra
Cc: Mathieu Poirier
Cc: Su
On 30/03/2021 13:15, Marc Zyngier wrote:
On Tue, 30 Mar 2021 12:12:49 +0100,
Suzuki K Poulose wrote:
Hi Marc
On 30/03/2021 11:12, Marc Zyngier wrote:
Hi Suzuki,
[+ Alex]
On Tue, 23 Mar 2021 12:06:35 +,
Suzuki K Poulose wrote:
For a nvhe host, the EL2 must allow the EL1&a
Hi Marc
On 30/03/2021 11:12, Marc Zyngier wrote:
Hi Suzuki,
[+ Alex]
On Tue, 23 Mar 2021 12:06:35 +,
Suzuki K Poulose wrote:
For a nvhe host, the EL2 must allow the EL1&0 translation
regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must
be saved/restored over a trip to the g
On 26/03/2021 16:55, Mathieu Poirier wrote:
On Tue, Mar 23, 2021 at 12:06:35PM +, Suzuki K Poulose wrote:
For a nvhe host, the EL2 must allow the EL1&0 translation
regime for TraceBuffer (MDCR_EL2.E2TB == 0b11). This must
be saved/restored over a trip to the guest. Also, before
ente
On 23/03/2021 08:11, Qi Liu wrote:
Fix the following checkpatch warning:
WARNING: 'compoment' may be misspelled - perhaps 'component'?
Fixes: 8e264c52e1da ("coresight: core: Allow the coresight core driver to be built
as a module")
Signed-off-by: Qi Liu
---
On 24/03/2021 16:30, Marc Zyngier wrote:
On Wed, 24 Mar 2021 16:25:12 +,
Suzuki K Poulose wrote:
On 24/03/2021 16:16, Marc Zyngier wrote:
On Wed, 24 Mar 2021 15:51:14 +,
Suzuki K Poulose wrote:
On 24/03/2021 13:49, Marc Zyngier wrote:
On Wed, 24 Mar 2021 09:39:13 +,
Suzuki K
On 24/03/2021 16:16, Marc Zyngier wrote:
On Wed, 24 Mar 2021 15:51:14 +,
Suzuki K Poulose wrote:
On 24/03/2021 13:49, Marc Zyngier wrote:
On Wed, 24 Mar 2021 09:39:13 +,
Suzuki K Poulose wrote:
On 23/03/2021 18:21, Catalin Marinas wrote:
Hi Suzuki?
On Tue, Mar 23, 2021 at 12:06
On 24/03/2021 13:49, Marc Zyngier wrote:
On Wed, 24 Mar 2021 09:39:13 +,
Suzuki K Poulose wrote:
On 23/03/2021 18:21, Catalin Marinas wrote:
Hi Suzuki?
On Tue, Mar 23, 2021 at 12:06:33PM +, Suzuki K Poulose wrote:
tsb csync synchronizes the trace operation of instructions
On 23/03/2021 18:21, Catalin Marinas wrote:
Hi Suzuki?
On Tue, Mar 23, 2021 at 12:06:33PM +, Suzuki K Poulose wrote:
tsb csync synchronizes the trace operation of instructions.
The instruction is a nop when FEAT_TRF is not implemented.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Catalin
On 23/03/2021 16:34, Marc Zyngier wrote:
On Tue, 23 Mar 2021 12:06:28 +, Suzuki K Poulose wrote:
This series enables future IP trace features Embedded Trace Extension
(ETE) and Trace Buffer Extension (TRBE). This series applies on
v5.12-rc4 + some patches queued. A standalone tree is also
errors and when the buffer
is full. Overall implementation here is inspired from the Arm SPE driver.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
[ Mark the buffer truncated on WRAP event, error code cleanup ]
Signed-off-by: Suzuki K Poulose
From: Anshuman Khandual
Add documentation for the TRBE under trace/coresight.
Cc: Jonathan Corbet
Cc: linux-...@vger.kernel.org
Reviewed-by: Mathieu Poirier
Signed-off-by: Anshuman Khandual
[ Split from the TRBE driver patch ]
Signed-off-by: Suzuki K Poulose
---
.../trace/coresight
Document the device tree bindings for Trace Buffer Extension (TRBE).
Cc: Anshuman Khandual
Cc: Mathieu Poirier
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Rob Herring
Signed-off-by: Suzuki K Poulose
---
.../devicetree/bindings/arm/trbe.yaml | 49
From: Anshuman Khandual
Add sysfs ABI documentation for the TRBE devices.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Jonathan Corbet
Cc: linux-...@vger.kernel.org
Reviewed-by: Mathieu Poirier
Signed-off-by: Anshuman Khandual
[ Split from the TRBE driver patch ]
Signed-off-by: Suzuki K Poulose
device. But such connections are not present for certain
percpu source and sink devices which are exclusively linked and dependent.
Build the path directly and skip connection scanning for such devices.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Tested-by: Suzuki K Poulose
Reviewed
Signed-off-by: Suzuki K Poulose
---
Changes since v4:
- Fix the out-ports definition (Rob Herring)
---
.../devicetree/bindings/arm/ete.yaml | 75 +++
MAINTAINERS | 1 +
2 files changed, 76 insertions(+)
create mode 100644 Documentation
.
ETE shares most of the registers with ETMv4 except for some and
also adds some new registers. Re-arrange the ETMv4x list
to share the common definitions and add the ETE sysreg support.
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v4
s centrally handled by the etm-perf.
Cc: Mathieu Poirier
Cc: Anshuman Khandual
Cc: Leo Yan
Cc: Mike Leach
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../hwtracing/coresight/coresight-etm-perf.c | 59 +--
1 file changed, 54
ETE may not implement the OS lock and instead could rely on
the PE OS Lock for the trace unit access. This is indicated
by the TRCOLSR.OSM == 0b100. Add support for handling the
PE OS lock
Cc: Mike Leach
Reviewed-by: mike.leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
If the CPU implements Arm v8.4 Trace filter controls (FEAT_TRF),
move the ETM to trace prohibited region using TRFCR, while disabling.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Anshuman Khandual
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
this is mandatory, the device will not be usable
as before this patch. Updating the DT bindings to Yaml and enabling
the schema checks can detect such issues with the DT.
Cc: Mike Leach
Cc: Leo Yan
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight
for a single
event is complex and is not something that we expect
on a sane configuration.
Cc: Anshuman Khandual
Reviewed-by: Mathieu Poirier
Reviewed-by: Mike Leach
Tested-by: Linu Cherian
Signed-off-by: Suzuki K Poulose
---
.../hwtracing/coresight/coresight-etm-perf.c | 60 +
From: Anshuman Khandual
This adds TRBE related registers and corresponding feature macros.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Reviewed-by: Suzuki K Poulose
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Acked-by: Catalin Marinas
Signed-off-by: Anshuman Khandual
hile we are in EL1 by clearing the TRFCR_EL1.
For vhe, the EL2 must prevent the EL1 access to the Trace
Buffer.
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: Anshuman Khandual
Acked-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include
the CPUs.
Cc: Marc Zyngier
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Mark Rutland
Signed-off-by: Suzuki K Poulose
--
Note: Marc has indicated that he will be picking this patch
I have included in the series for ease of testing.
---
arch/arm64/kernel/cpufeature.c | 1 -
1 file changed, 1 deletion
arm.com
Cc: mike.le...@linaro.org
Cc: a...@kernel.org
Cc: jo...@redhat.com
Cc: Mathieu Poirier
Reviewed by: Mike Leach
Acked-by: Peter Ziljstra
Signed-off-by: Suzuki K Poulose
---
include/uapi/linux/perf_event.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
with
the filtering controls set by a nvhe host.
Cc: Marc Zyngier
Cc: Will Deacon
Cc: Mark Rutland
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
Note: Marc has indicated that this will be queued for 5.12.
I have included this in the series for the sake of constructing
a full tree from
tsb csync synchronizes the trace operation of instructions.
The instruction is a nop when FEAT_TRF is not implemented.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/barrier.h | 1 +
1 file changed, 1
Cc: Peter Zijlstra
Cc: Mike Leach
Cc: Mathieu Poirier
Cc: Leo Yan
Cc: Anshuman Khandual
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
include/uapi/linux/perf_event.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/uapi/linux/per
- TRBE changes have been captured in the respective patches
RFC:
https://lore.kernel.org/linux-arm-kernel/1605012309-24812-1-git-send-email-anshuman.khand...@arm.com/
Cc: Will Deacon
Cc: Marc Zyngier
Cc: Peter Zilstra
Cc: Mathieu Poirier
Cc: Suzuki K Poulose
Cc: Mike Leach
Cc: Linu Cheri
On 23/03/2021 08:11, Qi Liu wrote:
Fix the following checkpatch warning:
WARNING: 'compoment' may be misspelled - perhaps 'component'?
Fixes: 8e264c52e1da ("coresight: core: Allow the coresight core driver to be built
as a module")
I will queue this one, dropping the above Fixes tag. In
On 23/03/2021 07:54, Zou Wei wrote:
Fix the following sparse warning:
drivers/hwtracing/coresight/coresight-etm-perf.c:61:25: warning: symbol
'format_attr_contextid' was not declared. Should it be static?
A fix is already queued in coresight/next.
Thanks
Suzuki
On 23/03/2021 09:16, Marc Zyngier wrote:
Hi Suzuki,
On 2021-03-22 22:24, Suzuki K Poulose wrote:
Hi Marc,
On 25/02/2021 19:35, Suzuki K Poulose wrote:
Disable guest access to the Trace Filter control registers.
We do not advertise the Trace filter feature to the guest
(ID_AA64DFR0_EL1
On 22/03/2021 21:24, Mathieu Poirier wrote:
On Fri, Mar 19, 2021 at 11:55:10AM +, Mike Leach wrote:
HI Suzuki,
On Fri, 19 Mar 2021 at 10:30, Suzuki K Poulose wrote:
Hi Mike
On 8 Mar 2021, at 17:26, Mike Leach wrote:
Hi Suzuki,
On Thu, 25 Feb 2021 at 19:36, Suzuki K Poulose wrote
On 22/03/2021 17:28, Rob Herring wrote:
On Mon, Mar 22, 2021 at 10:53 AM Suzuki K Poulose
wrote:
Hi Rob
On 06/03/2021 21:06, Rob Herring wrote:
On Thu, Feb 25, 2021 at 07:35:39PM +, Suzuki K Poulose wrote:
Document the device tree bindings for Embedded Trace Extensions.
ETE can
Hi Marc,
On 25/02/2021 19:35, Suzuki K Poulose wrote:
Disable guest access to the Trace Filter control registers.
We do not advertise the Trace filter feature to the guest
(ID_AA64DFR0_EL1: TRACE_FILT is cleared) already, but the guest
can still access the TRFCR_EL1 unless we trap
Will, Catalin,
On 25/02/2021 19:35, Suzuki K Poulose wrote:
Currently we advertise the ID_AA6DFR0_EL1.TRACEVER for the guest,
when the trace register accesses are trapped (CPTR_EL2.TTA == 1).
So, the guest will get an undefined instruction, if trusts the
ID registers and access one of the trace
Hi Mike
On 08/03/2021 17:26, Mike Leach wrote:
Hi,
On Thu, 25 Feb 2021 at 19:36, Suzuki K Poulose wrote:
From: Anshuman Khandual
Add support for dedicated sinks that are bound to individual CPUs. (e.g,
TRBE). To allow quicker access to the sink for a given CPU bound source,
keep a percpu
Hi Rob
On 06/03/2021 21:06, Rob Herring wrote:
On Thu, Feb 25, 2021 at 07:35:39PM +, Suzuki K Poulose wrote:
Document the device tree bindings for Embedded Trace Extensions.
ETE can be connected to legacy coresight components and thus
could optionally contain a connection graph
On 22/03/2021 13:11, Qi Liu wrote:
Fix up one typo: compoment->component.
Fixes: 8e264c52e1da ("coresight: core: Allow the coresight core driver to be built
as a module")
Signed-off-by: Qi Liu
Thanks for the patch. I will queue this.
On 16/03/2021 17:04, Mathieu Poirier wrote:
On Thu, Feb 25, 2021 at 07:35:26PM +, Suzuki K Poulose wrote:
CoreSight PMU supports aux-buffer for the ETM tracing. The trace
generated by the ETM (associated with individual CPUs, like Intel PT)
is captured by a separate IP (CoreSight TMC-ETR
Hi Mathieu,
> On 18 Mar 2021, at 18:08, Mathieu Poirier wrote:
>
> Good morning,
>
> On Thu, Feb 25, 2021 at 07:35:42PM +, Suzuki K Poulose wrote:
>> From: Anshuman Khandual
>>
>> Trace Buffer Extension (TRBE) implements a trace buffer per CPU whic
Hi Mike
> On 8 Mar 2021, at 17:26, Mike Leach wrote:
>
> Hi Suzuki,
>
> On Thu, 25 Feb 2021 at 19:36, Suzuki K Poulose wrote:
>>
>> From: Anshuman Khandual
>>
>> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
>>
On 3/16/21 8:23 PM, Mathieu Poirier wrote:
On Thu, Feb 25, 2021 at 07:35:34PM +, Suzuki K Poulose wrote:
When a sink is not specified by the user, the etm perf driver
finds a suitable sink automatically, based on the first ETM
where this event could be scheduled. Then we allocate the
sink
Hi Mathieu
On 3/16/21 7:30 PM, Mathieu Poirier wrote:
On Thu, Feb 25, 2021 at 07:35:33PM +, Suzuki K Poulose wrote:
If the CPU implements Arm v8.4 Trace filter controls (FEAT_TRF),
move the ETM to trace prohibited region using TRFCR, while disabling.
Cc: Mathieu Poirier
Cc: Mike Leach
this
commit marks it static.
Reported-by: Hulk Robot
Signed-off-by: Wei Yongjun
Reviewed-by: Suzuki K Poulose
On 1/28/21 5:09 PM, Mike Leach wrote:
Preload set of configurations.
This patch creates a small set of preloaded configurations and features
that are available immediately after coresight has been initialised.
The current set provides a strobing feature for ETMv4, that creates a
periodic
On 1/28/21 5:09 PM, Mike Leach wrote:
Adds in handlers to allow the ETMv4 to use the complex configuration
support. Features and configurations can be loaded and selected in the
device.
Signed-off-by: Mike Leach
---
drivers/hwtracing/coresight/Makefile | 3 +-
On 1/28/21 5:09 PM, Mike Leach wrote:
Add calls to activate the selected configuration as perf starts
and stops the tracing session.
Signed-off-by: Mike Leach
Reviewed-by: Suzuki K Poulose
On 1/28/21 5:09 PM, Mike Leach wrote:
Configurations are first activated, then when any coresight device is
enabled, the active configurations are checked and any matching
one is enabled.
This patch provides the activation / enable API.
Signed-off-by: Mike Leach
---
On 3/4/21 2:19 PM, Mike Leach wrote:
Hi Suzuki,
On Thu, 4 Mar 2021 at 12:13, Suzuki K Poulose wrote:
On 1/28/21 5:09 PM, Mike Leach wrote:
Loaded coresight configurations are registered in the cs_etm\cs_config sub
directory. This extends the etm-perf code to handle these registrations
On 1/28/21 5:09 PM, Mike Leach wrote:
Loaded coresight configurations are registered in the cs_etm\cs_config sub
directory. This extends the etm-perf code to handle these registrations,
and the cs_syscfg driver to perform the registration on load.
Signed-off-by: Mike Leach
---
On 1/28/21 5:09 PM, Mike Leach wrote:
Adds a set of generic support functions that allow devices to set and save
features values on the device, and enable and disable configurations.
Additional functions for other common operations including feature
reset.
Signed-off-by: Mike Leach
---
On 1/28/21 5:09 PM, Mike Leach wrote:
Creates an system management API to allow complex configurations and
features to be programmed into a CoreSight infrastructure.
A feature is defined as a programming set for a device or class of
devices.
A configuration is a set of features across the
Hi Mike
There are some minor comments on the naming scheme of the structures,
which I think might improve the code readability.
e.g, in general anything that is associated with a csdev could be named
as such csdev_*, rather than cscfg_*_csdev. The latter kind of implies
"cscfg" is the "primary"
On 1/28/21 5:09 PM, Mike Leach wrote:
Creates an system management API to allow complex configurations and
features to be programmed into a CoreSight infrastructure.
A feature is defined as a programming set for a device or class of
devices.
A configuration is a set of features across the
On 1/28/21 5:09 PM, Mike Leach wrote:
Creates an system management API to allow complex configurations and
features to be programmed into a CoreSight infrastructure.
A feature is defined as a programming set for a device or class of
devices.
A configuration is a set of features across the
On 1/28/21 5:09 PM, Mike Leach wrote:
Creates an system management API to allow complex configurations and
features to be programmed into a CoreSight infrastructure.
A feature is defined as a programming set for a device or class of
devices.
A configuration is a set of features across the
Hi Alex
On 3/1/21 4:32 PM, Alexandru Elisei wrote:
Hello Suzuki,
On 2/25/21 7:35 PM, Suzuki K Poulose wrote:
The nvhe hyp saves the SPE context, flushing any unwritten
Perhaps that can be reworded to "The nVHE world switch code saves [..]".
Sure
Also, according to my und
device. But such connections are not present for certain
percpu source and sink devices which are exclusively linked and dependent.
Build the path directly and skip connection scanning for such devices.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Tested-by: Suzuki K Poulose
Reviewed
to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Suzuki-K-Poulose/arm64-coresight-Add-support-for-ETE-and-TRBE/20210226-035447
base: https
Document the device tree bindings for Trace Buffer Extension (TRBE).
Cc: Anshuman Khandual
Cc: Mathieu Poirier
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Reviewed-by: Rob Herring
Signed-off-by: Suzuki K Poulose
---
.../devicetree/bindings/arm/trbe.yaml | 49
errors and when the buffer
is full. Overall implementation here is inspired from the Arm SPE driver.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
Signed-off-by: Suzuki K Poulose
---
Changes:
- Replaced TRBLIMITR_LIMIT_SHIFT with TRBBASER_BASE_SHIFT
Signed-off-by: Suzuki K Poulose
---
Changes:
- Fix out-ports defintion
---
.../devicetree/bindings/arm/ete.yaml | 71 +++
1 file changed, 71 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml
diff --git a/Documentation/devicetree/bindings/arm
s centrally handled by the etm-perf.
Cc: Mathieu Poirier
Cc: Anshuman Khandual
Cc: Leo Yan
Cc: Mike Leach
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes :
- Added WARN_ON() as suggested by Mathieu
---
.../hwtracing/coresight/coresight-etm-p
device. But such connections are not present for certain
percpu source and sink devices which are exclusively linked and dependent.
Build the path directly and skip connection scanning for such devices.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Tested-by: Suzuki K Poulose
Reviewed
From: Anshuman Khandual
This adds TRBE related registers and corresponding feature macros.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Reviewed-by: Suzuki K Poulose
Reviewed-by: Mike Leach
Acked-by: Catalin Marinas
Signed-off-by: Anshuman Khandual
Signed-off-by: Suzuki K
for a single
event is complex and is not something that we expect
on a sane configuration.
Cc: Mathieu Poirier
Cc: Mike Leach
Tested-by: Linu Cherian
Signed-off-by: Suzuki K Poulose
---
Changes:
- Rename sinks_match => sinks_compatible
- Tighten the check by matching the sink subtype
- Use
with
the filtering controls set by a nvhe host.
Cc: Marc Zyngier
Cc: Will Deacon
Cc: Mark Rutland
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
---
New patch
---
arch/arm64/include/asm/kvm_arm.h | 1 +
arch/arm64/kvm/debug.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch
hile we are in EL1 by clearing the TRFCR_EL1.
For vhe, the EL2 must prevent the EL1 access to the Trace
Buffer.
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Mark Rutland
cc: Anshuman Khandual
Signed-off-by: Suzuki K Poulose
---
Changes
- Rebased to linux-next.
- Re-enable
this is mandatory, the device will not be usable
as before this patch. Updating the DT bindings to Yaml and enabling
the schema checks can detect such issues with the DT.
Cc: Mike Leach
Cc: Leo Yan
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight
.
Cc: Mike Leach
Reviewed-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes:
- Addressed style related comments
- Moved sysreg list macro definition the previous patch
---
drivers/hwtracing/coresight/Kconfig | 10 ++--
.../coresight/coresight
-by: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes:
- Fix alignment and switch pr_warn_ratelimited()
- Move NOP case list macro here
---
.../coresight/coresight-etm4x-core.c | 32 +++
drivers/hwtracing/coresight/coresight-etm4x.h | 54
tsb csync synchronizes the trace operation of instructions.
The instruction is a nop when FEAT_TRF is not implemented.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Suzuki K Poulose
---
New patch, split from the TRBE driver for ease of merging
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