If the CPU implements Arm v8.4 Trace filter controls (FEAT_TRF),
move the ETM to trace prohibited region using TRFCR, while disabling.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Anshuman Khandual
Signed-off-by: Suzuki K Poulose
---
New patch
---
.../coresight/coresight-etm4x-core.c | 21
ETE may not implement the OS lock and instead could rely on
the PE OS Lock for the trace unit access. This is indicated
by the TRCOLSR.OSM == 0b100. Add support for handling the
PE OS lock
Cc: Mike Leach
Reviewed-by: mike.leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
t;KVM: arm64: Improve debug register save/restore flow")
Cc: sta...@vger.kernel.org
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Mark Rutland
Cc: Alexandru Elisei
Signed-off-by: Suzuki K Poulose
---
New patch.
---
arch/arm64/include/asm/kvm_hyp.h | 5 +
arm.com
Cc: mike.le...@linaro.org
Cc: a...@kernel.org
Cc: jo...@redhat.com
Cc: Mathieu Poirier
Reviewed by: Mike Leach
Acked-by: Peter Ziljstra
Signed-off-by: Suzuki K Poulose
---
include/uapi/linux/perf_event.h | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git
captured in the respective patches
Changes in RFC:
https://lore.kernel.org/linux-arm-kernel/1605012309-24812-1-git-send-email-anshuman.khand...@arm.com/
Cc: Will Deacon
Cc: Marc Zyngier
Cc: Peter Zilstra
Cc: Mathieu Poirier
Cc: Suzuki K Poulose
Cc: Mike Leach
Cc: Linu Cherian
Cc
the CPUs.
Cc: Marc Zyngier
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Mark Rutland
Signed-off-by: Suzuki K Poulose
---
New patch
---
arch/arm64/kernel/cpufeature.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 066030717a4c
Cc: Peter Zijlstra
Cc: Mike Leach
Cc: Mathieu Poirier
Cc: Leo Yan
Cc: Anshuman Khandual
Reviewed-by: Mike Leach
Signed-off-by: Suzuki K Poulose
---
Changes from previous:
- Split from the coresight driver specific code
for ease of merging
---
include/uapi/linux/perf_event.h | 4
On 2/25/21 9:42 AM, Arnd Bergmann wrote:
From: Arnd Bergmann
clang-12 fails to build the etm4x driver with -fsanitize=array-bounds:
:1:7: error: expected constant expression in '.inst' directive
.inst (0xd520|2) << 19) | ((1) << 16) | (((0x160 + (i * 4) >> 2))) >> 7) &
On 2/18/21 6:33 PM, Rob Herring wrote:
On Wed, Feb 10, 2021 at 12:33:44PM +, Suzuki K Poulose wrote:
Hi Rob
On 2/9/21 7:00 PM, Rob Herring wrote:
On Wed, Jan 27, 2021 at 02:25:30PM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose
Document the device tree bindings for Embedded
On 2/18/21 2:30 PM, Mike Leach wrote:
HI Suzuki,
On Thu, 18 Feb 2021 at 07:50, Suzuki K Poulose wrote:
Hi Mike
On 2/16/21 9:00 AM, Mike Leach wrote:
Hi Anshuman,
There have been plenty of detailed comments so I will restrict mine to
a few general issues:-
1) Currently there appears
Hi Mike
On 2/12/21 5:30 PM, Mike Leach wrote:
Hi Suzuki,
On Fri, 12 Feb 2021 at 15:36, Suzuki K Poulose wrote:
Hi Mike
On 2/12/21 10:34 AM, Mike Leach wrote:
Hi Mathieu, Suzuki,
Sorry for the really late response on this patch, but I noticed a
problem while doing a review of the ETE
. The TRBE can also generate a CPU
private interrupt (PPI) on address translation errors and when the buffer
is full. Overall implementation here is inspired from the Arm SPE driver.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
---
Changes in V3:
- Ad
.
Cc: Catalin Marinas
Cc: Mike Leach
Cc: Will Deacon
Reviewed-by: Mathieu Poirier
Signed-off-by: Jonathan Zhou
[ Move the trace filtering setup etm_init_arch_data() and
clean ups]
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 25 +++
1
t and guest, the two configs "contextid1" and
+"contextid2" can be set at the same time:
+
+ perf record -e cs_etm/contextid1,contextid2/u -- vm
+
Reviewed-by: Suzuki K Poulose
On 2/6/21 3:08 PM, Leo Yan wrote:
This patch adds helper function cs_etm__get_pid_fmt(), by passing
parameter "traceID", it returns the PID format.
Signed-off-by: Leo Yan
Reviewed-by: Suzuki K Poulose
Hi Rob
On 2/9/21 7:00 PM, Rob Herring wrote:
On Wed, Jan 27, 2021 at 02:25:30PM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose
Document the device tree bindings for Embedded Trace Extensions.
ETE can be connected to legacy coresight components and thus
could optionally contain
On 2/4/21 4:09 AM, Leo Yan wrote:
Hi Mike,
On Wed, Feb 03, 2021 at 05:39:54PM +, Mike Leach wrote:
[...]
+2.2) Tracing PID
+
+When the kernel is running at EL2 with Virtualization Host Extensions (VHE),
+perf records CONTEXTIDR_EL2 in the trace data and can be used as PID when
+decoding;
On 2/4/21 4:00 AM, Leo Yan wrote:
On Tue, Feb 02, 2021 at 11:29:47PM +, Suzuki Kuruppassery Poulose wrote:
On 2/2/21 4:38 PM, Leo Yan wrote:
From: Suzuki K Poulose
The PID of the task could be traced as VMID when the kernel is running
at EL2. Teach the decoder to look for VMID when
On 2/4/21 3:47 AM, Leo Yan wrote:
On Tue, Feb 02, 2021 at 11:19:22PM +, Suzuki Kuruppassery Poulose wrote:
On 2/2/21 4:38 PM, Leo Yan wrote:
This patch adds helper function cs_etm__get_pid_fmt(), by passing
parameter "traceID", it returns the PID format.
Signed-off-by: Leo Yan
---
On 2/3/21 7:05 PM, Mathieu Poirier wrote:
On Wed, Jan 27, 2021 at 02:25:31PM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose
The context associated with an ETM for a given perf event
includes :
- handle -> the perf output handle for the AUX buffer.
- the path for the tr
On 2/2/21 5:52 PM, Mathieu Poirier wrote:
On Wed, Jan 27, 2021 at 02:25:28PM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose
Add support for handling the system registers for Embedded Trace
Extensions (ETE). ETE shares most of the registers with ETMv4 except
for some and also adds some
On 2/2/21 4:38 PM, Leo Yan wrote:
From: Suzuki K Poulose
The PID of the task could be traced as VMID when the kernel is running
at EL2. Teach the decoder to look for VMID when the CONTEXTIDR (Arm32)
or CONTEXTIDR_EL1 (Arm64) is invalid but we have a valid VMID.
Cc: Mike Leach
Cc: Mathieu
s_etm/contextid1,contextid2/u -- vm
Otherwise looks good to me.
With the above fixed,
Reviewed-by: Suzuki K Poulose
On 2/2/21 4:38 PM, Leo Yan wrote:
This patch adds helper function cs_etm__get_pid_fmt(), by passing
parameter "traceID", it returns the PID format.
Signed-off-by: Leo Yan
---
tools/perf/util/cs-etm.c | 43
tools/perf/util/cs-etm.h | 1 +
2 files
On 2/2/21 4:38 PM, Leo Yan wrote:
From: Suzuki K Poulose
When the kernel is running at EL2, the PID is stored in CONTEXTIDR_EL2.
So, tracing CONTEXTIDR_EL1 doesn't give us the pid of the process.
Thus we should trace the VMID with VMIDOPT set to trace CONTEXTIDR_EL2
instead of CONTEXTIDR_EL1
the background info for
these bits are coming from ETMv3.5/PTM. Afterwards, we should take
these options as general knobs, and if there have any confliction with
ETMv3.5/PTM, should consider to define saperate macros for ETMv3.5/PTM
ETMCR config bits.
Suggested-by: Suzuki K Poulose
Signed-off-by: Leo Yan
On 2/2/21 6:56 PM, Mathieu Poirier wrote:
On Wed, Jan 27, 2021 at 02:25:29PM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose
Add ETE as one of the supported device types we support
with ETM4x driver. The devices are named following the
existing convention as ete.
ETE mandates
On 2/2/21 4:33 PM, Mike Leach wrote:
Hi,
On Tue, 2 Feb 2021 at 09:42, Suzuki K Poulose wrote:
On 2/1/21 11:17 PM, Mathieu Poirier wrote:
Hi Anshuman,
I have started reviewing this set. As it is quite voluminous comments will
come over serveral days. I will let you know when I am done
Hi Mike
On 2/2/21 11:10 AM, Mike Leach wrote:
Hi Ansuman,
On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
wrote:
From: Suzuki K Poulose
If a graph node is not found for a given node, of_get_next_endpoint()
will emit the following error message :
OF: graph: no port node found
On 2/1/21 11:17 PM, Mathieu Poirier wrote:
Hi Anshuman,
I have started reviewing this set. As it is quite voluminous comments will
come over serveral days. I will let you know when I am done.
On Wed, Jan 27, 2021 at 02:25:25PM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose
When
On 1/28/21 9:46 AM, Marc Zyngier wrote:
On 2021-01-28 09:34, Suzuki K Poulose wrote:
On 1/27/21 9:58 AM, Marc Zyngier wrote:
On 2021-01-27 08:55, Anshuman Khandual wrote:
From: Suzuki K Poulose
When the kernel is booted at EL2 in a nvhe configuration,
enable the TRBE access to the EL1
On 1/27/21 9:58 AM, Marc Zyngier wrote:
On 2021-01-27 08:55, Anshuman Khandual wrote:
From: Suzuki K Poulose
When the kernel is booted at EL2 in a nvhe configuration,
enable the TRBE access to the EL1. The EL1 still can't trace
EL2, unless EL2 permits explicitly via TRFCR_EL2.E2TRE.
Cc
On 1/27/21 8:55 AM, Anshuman Khandual wrote:
This adds TRBE related registers and corresponding feature macros.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Cc: Catalin Marinas
Cc: Mark Rutland
Cc: Will Deacon
Signed-off-by: Anshuman Khandual
Reviewed-by: Suzuki K
between a
source and a sink device. But such connections are not present for certain
percpu source and sink devices which are exclusively linked and dependent.
Build the path directly and skip connection scanning for such devices.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Signed-off
TRCSTALLCTLR register is only implemented if
TRCIDR3.STALLCTL == 0b1
Make sure the driver touches the register only it is implemented.
Cc: sta...@vger.kernel.org
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Leo Yan
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- Ignore STALLCTL
On 1/27/21 5:43 PM, Mathieu Poirier wrote:
Good day,
On Wed, Jan 27, 2021 at 12:00:32PM +, Suzuki K Poulose wrote:
TRCSTALLCTLR register is only implemented if
TRCIDR3.STALLCTL == 0b1
Make sure the driver touches the register only it is implemented.
Cc: sta...@vger.kernel.org
Cc
Hi Peter
On 1/27/21 12:54 PM, Peter Zijlstra wrote:
On Wed, Jan 27, 2021 at 02:25:38PM +0530, Anshuman Khandual wrote:
It is possible to have a
perf session where some events end up collecting the trace
in TMC-ETR while the others in TRBE. Thus we need a way
to identify the type of the trace
TRCSTALLCTLR register is only implemented if
TRCIDR3.STALLCTL == 0b1
Make sure the driver touches the register only it is implemented.
Cc: sta...@vger.kernel.org
Cc: Mathieu Poirier
Cc: Leo Yan
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
Changes since v1:
- No change
ges look good for the drivers/hwtracing/coresight/*
Acked-by: Suzuki K Poulose
Hi Peter
On 1/25/21 10:25 AM, Peter Zijlstra wrote:
On Fri, Jan 22, 2021 at 03:18:29PM +, Suzuki K Poulose wrote:
CoreSight PMU supports aux-buffer for the ETM tracing. The trace
generated by the ETM (associated with individual CPUs, like Intel PT)
is captured by a separate IP (CoreSight
On 1/25/21 10:20 PM, Suzuki K Poulose wrote:
Hi Rob
On 1/25/21 7:22 PM, Rob Herring wrote:
On Wed, Jan 13, 2021 at 09:48:13AM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose
Document the device tree bindings for Embedded Trace Extensions.
ETE can be connected to legacy coresight
Hi Rob
On 1/25/21 7:22 PM, Rob Herring wrote:
On Wed, Jan 13, 2021 at 09:48:13AM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose
Document the device tree bindings for Embedded Trace Extensions.
ETE can be connected to legacy coresight components and thus
could optionally contain
On 1/25/21 6:49 PM, Mathieu Poirier wrote:
On Sun, Jan 10, 2021 at 10:48:22PM +, Suzuki K Poulose wrote:
CoreSight ETMv4.4 obsoletes memory mapped access to ETM and
mandates the system instructions for registers.
This also implies that they may not be on the amba bus.
Right now all
atic const struct arm64_ftr_bits ftr_raz[] = {
#define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, _override)
+struct arm64_ftr_override id_aa64mmfr1_override;
Does this need to be ro_after_init ?
Otherwise, looks good to me:
Acked-by: Suzuki K Poulose
previous patch and thus we are covered.
Reviewed-by: Suzuki K Poulose
is yet, so we are pretty safe. For now.
Signed-off-by: Marc Zyngier
Reviewed-by: Suzuki K Poulose
ing this.
[1]
https://lkml.kernel.org/r/1610511498-4058-1-git-send-email-anshuman.khand...@arm.com
Suzuki K Poulose (1):
perf: Handle multiple formatted AUX records
drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++
include/linux/coresight.h| 1 +
include/uap
the trace for each AUX record.
This patch adds a new flag to indicate the trace format
for the given record. Also, includes the changes that
demonstrates how this can be used in the CoreSight PMU
to solve the problem.
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm-
On 1/19/21 9:51 AM, Sai Prakash Ranjan wrote:
Hi Al,
On 2021-01-19 14:06, Al Grant wrote:
Hi Sai,
From: saiprakash.ranjan=codeaurora@mg.codeaurora.org
Hi Mathieu,
On 2021-01-19 01:53, Mathieu Poirier wrote:
> On Fri, Jan 15, 2021 at 11:16:24AM +0530, Sai Prakash Ranjan wrote:
>> Hello
Hi Mathieu
On 1/15/21 10:30 PM, Mathieu Poirier wrote:
Hey guys,
On Sat, Jan 09, 2021 at 03:44:29PM +0800, Leo Yan wrote:
From: Suzuki K Poulose
When the kernel is running at EL2, the PID is stored in CONTEXTIDR_EL2.
So, tracing CONTEXTIDR_EL1 doesn't give us the pid of the process.
Thus we
On 1/15/21 2:36 AM, Anshuman Khandual wrote:
On 1/13/21 3:13 PM, Suzuki K Poulose wrote:
On 1/13/21 4:18 AM, Anshuman Khandual wrote:
Add support for dedicated sinks that are bound to individual CPUs. (e.g,
TRBE). To allow quicker access to the sink for a given CPU bound source,
keep
On 1/15/21 5:29 AM, Anshuman Khandual wrote:
On 1/13/21 8:58 PM, Suzuki K Poulose wrote:
Hi Anshuman,
The driver looks overall good to me. Please find some minor comments below
On 1/13/21 4:18 AM, Anshuman Khandual wrote:
Trace Buffer Extension (TRBE) implements a trace buffer per CPU
On 1/14/21 2:07 PM, Rob Herring wrote:
On Wed, Jan 13, 2021 at 09:48:18AM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose
Document the device tree bindings for Trace Buffer Extension (TRBE).
Cc: Anshuman Khandual
Cc: Mathieu Poirier
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
Hi Rob
On 1/13/21 3:45 PM, Rob Herring wrote:
On Wed, 13 Jan 2021 09:48:18 +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose
Document the device tree bindings for Trace Buffer Extension (TRBE).
Cc: Anshuman Khandual
Cc: Mathieu Poirier
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
private interrupt (PPI) on address translation errors and when the buffer
is full. Overall implementation here is inspired from the Arm SPE driver.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Signed-off-by: Anshuman
: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
Reviewed-by: Suzuki K Poulose
between a
source and a sink device. But such connections are not present for certain
percpu source and sink devices which are exclusively linked and dependent.
Build the path directly and skip connection scanning for such devices.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Signed-off
On 1/13/21 4:18 AM, Anshuman Khandual wrote:
This adds TRBE related registers and corresponding feature macros.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/sysreg.h | 49 +
1
On 1/12/21 11:51 AM, Marc Zyngier wrote:
On 2021-01-12 11:50, Marc Zyngier wrote:
Hi Suzuki,
On 2021-01-12 09:17, Suzuki K Poulose wrote:
Hi Marc,
On 1/11/21 7:48 PM, Marc Zyngier wrote:
[...]
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 894af60b9669
On 1/12/21 11:50 AM, Marc Zyngier wrote:
Hi Suzuki,
On 2021-01-12 09:17, Suzuki K Poulose wrote:
Hi Marc,
On 1/11/21 7:48 PM, Marc Zyngier wrote:
[...]
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 894af60b9669..00d99e593b65 100644
--- a/arch/arm64
On 1/12/21 8:58 AM, Leo Yan wrote:
Hi Mike,
On Mon, Jan 11, 2021 at 04:22:39PM +, Mike Leach wrote:
[...]
diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
index b0e35eec6499..927c6285ce5d 100644
--- a/include/linux/coresight-pmu.h
+++
Hi Marc,
On 1/11/21 7:48 PM, Marc Zyngier wrote:
Hi Catalin,
On 2021-01-11 18:41, Catalin Marinas wrote:
Hi Marc,
On Mon, Jan 11, 2021 at 01:27:59PM +, Marc Zyngier wrote:
Add a facility to globally override a feature, no matter what
the HW says. Yes, this is dangerous.
Yeah, it's
Hi Leo
On 1/9/21 7:44 AM, Leo Yan wrote:
From: Suzuki K Poulose
The pid of the task could be traced as VMID when the kernel is
running at EL2. Teach the decoder to look for vmid when the
context_id is invalid but we have a valid VMID.
Thank you again for cleaning up this ! Please see one
On 1/9/21 7:44 AM, Leo Yan wrote:
This patch adds helper function cs_etm__get_pid_fmt(), by passing
parameter "traceID", it returns the corresponding PID format.
Signed-off-by: Leo Yan
Acked-by: Suzuki K Poulose
---
tools/perf/util/cs-etm.c | 18 ++
tools/pe
(ETM_OPT_CTXTID), this info will be delivered to the decoder to
extract PID from packet's field "context_id".
Signed-off-by: Leo Yan
Acked-by: Suzuki K Poulose
---
tools/perf/util/cs-etm.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tools/perf/util/cs-etm.c b/
Hi Leo,
On 1/9/21 7:44 AM, Leo Yan wrote:
It's possible for CoreSight to trace PID in either CONTEXTIDR_EL1 or
CONTEXTIDR_EL2, the PID format info is used to distinguish the PID
is traced in which register.
This patch saves PID format into the metadata when record.
The patch looks good to
, this patch calculates per CPU
metadata array size on the runtime, the calculation is based on the
info stored in the data file so that it's reliable.
Signed-off-by: Leo Yan
Looks good to me.
Acked-by: Suzuki K Poulose
As we are about define a switch..case table for individual register
access by offset for implementing the system instruction support,
document the possible set of registers for each group to make
it easier to correlate.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Convert the generic CLAIM tag management APIs to use the
device access layer abstraction.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since V3:
- Removed WARN_ON(!csdev) check. (Mathieu)
- Fixed indentation (Mathieu)
---
drivers/hwtracing
-by: Suzuki K Poulose
---
Changes since v5:
- Move the trcdevarch to mgmt/ instead of the trcidr (Mike L)
- Add sysfs documentation for the new register (Mike L)
---
.../ABI/testing/sysfs-bus-coresight-devices-etm4x | 8
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 1
In preparation to detect the support for system instruction
support, move the detection of the device access to the target
CPU.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v3
- Name constructs etm4_xx instead of etm_** (Mathieu
Add support for devices with system instruction access only.
They don't have a memory mapped interface and thus are not
AMBA devices. System register access is not permitted to
TRCPDCR and thus skip access to them.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
-by: Suzuki K Poulose
---
arch/arm64/include/asm/sysreg.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 8b5e7e5c3cc8..4acff97519b9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
CoreSight ETM with system register access may not have a
memory mapped i/o access. Refactor the ETM specific probing
into a common routine to allow reusing the code for such ETMs.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v4:
- Refactor
users by
shifting to their field.
No functional changes intended.
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v3:
- Fix errors in victlr ns_mask setting.
Changes since v2:
- Fix the duplicate shift. More commentary
---
.../coresight/coresight-etm4x-core.c
the PID from the HW, as the
PID could be overridden by DT for broken devices. So, use the
PID from AMBA layer if available.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: liuqi...@huawei.com
Signed-off-by: Suzuki K Poulose
---
Changes since v7:
- Fixed typo in commit description
---
drivers/hwtracing
As per the specification any update to the TRCPRGCTLR must be synchronized
by a context synchronization event (in our case an explicist ISB) before
the TRCSTATR is checked.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight
Convert the generic routines to use the new access abstraction layer
gradually, starting with coresigth_timeout.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v4:
- Remove stacking of parameters in coresight.h
Changes since v3:
- Fix style
As we are about to add support for sysreg access to ETM4.4+ components,
make sure that we read the registers only on the host CPU.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-sysfs.c | 23 ---
1 file
ETM v4.4 onwards adds support for system instruction access
to the ETM. Detect the support on an ETM and switch to using the
mode when available.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 39
We have been using TRCIDR1 for detecting the ETM version. This
is in preparation for the future IP support.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 46 +--
1 file changed, 23 insertions
-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++--
drivers/hwtracing/coresight/coresight-etm4x.h | 6 --
2 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
b/drivers/hwtracing
by adding helpers.
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 60 ++-
2 files changed, 58 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing
Document the bindings for ETMs with system register accesses.
Cc: devicet...@vger.kernel.org
Cc: Mathieu Poirier
Cc: Mike Leach
Acked-by: Rob Herring
Signed-off-by: Suzuki K Poulose
---
Documentation/devicetree/bindings/arm/coresight.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion
Cc: Mike Leach
Cc: Will Deacon
Reviewed-by: Mathieu Poirier
Signed-off-by: Jonathan Zhou
[ Move the trace filtering setup etm_init_arch_data() and
clean ups]
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 25 +++
1 file changed, 25
The Software lock is not implemented for system instructions
based accesses. So, skip the lock register access in such
cases.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Change since v6:
- Fixed indentation
---
.../coresight/coresight-etm4x-core.c
.
Fixes: 02510a5aa78df45 ("coresight: etm4x: Add support to skip trace unit power
up")
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Sai Prakash Ranjan
Cc: Tingwei Zhang
Reviewed-by: Sai Prakash Ranjan
Tested-by: Sai Prakash Ranjan
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing
Define the fields of the DEVARCH register for identifying
a component as an ETMv4.x unit. Going forward, we use the
DEVARCH register for the component identification, rather
than the TRCIDR3.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight
.
All registers are accessible via the memory-mapped interface.
However, some registers are not accessible via the system
instructions. This list is then used to further filter out
the files we expose via sysfs.
Cc: Mike Leach
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Changes since v6
not be accessed.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
New patch in v7
---
.../coresight/coresight-etm4x-sysfs.c | 51 +++
drivers/hwtracing/coresight/coresight-etm4x.h | 6 +++
2 files changed, 57 insertions(+)
diff --git a/drivers
viewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
.../coresight/coresight-etm4x-core.c | 327 +-
.../coresight/coresight-etm4x-sysfs.c | 9 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 24 ++
3 files changed, 188 insertions(+), 172 del
used for determining
a given attribute must be "visible" via sysfs.
Cc: Mathieu Poirier
Cc: Mike Leach
Signed-off-by: Suzuki K Poulose
---
New patch in v7
---
.../coresight/coresight-etm4x-sysfs.c | 115 +-
1 file changed, 57 insertions(+), 58 deletions(-)
TRCSSPCICR is present only if all of the following are true:
TRCIDR4.NUMSSCC > n.
TRCIDR4.NUMPC > 0b .
TRCSSCSR.PC == 0b1
Add a helper function to check all the conditions.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
C
in the access directly
to avoid having to deal with the un-initialised csdev.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
drivers/hwtracing/coresight/coresight-tpiu.c | 30 +---
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git
\
+case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; }
I don't know a way to fix the warning without loosing the code
readability, which I believe is crucial for such a construct.
Jonathan Zhou (2):
arm64: Add TRFCR_ELx definitions
coresight: Add support for v8.4
layer for the accesses
to a given device.
Cc: Mike Leach
Reviewed-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
---
Change since v6:
- Fix code indentation in coresight.h (Mathieu Poirier)
Change since v3
- Dropped csa argument to read()/write().
- Addressed comments on spacing and adding
/21 9:08 AM, Suzuki K Poulose wrote:
Hi Mathieu
On 1/8/21 1:09 AM, Mathieu Poirier wrote:
Hi Suzuki,
On Thu, Jan 07, 2021 at 12:38:33PM +, Suzuki K Poulose wrote:
CoreSight ETMv4.4 obsoletes memory mapped access to ETM and
mandates the system instructions for registers.
This also implies
Hi Mathieu
On 1/8/21 1:09 AM, Mathieu Poirier wrote:
Hi Suzuki,
On Thu, Jan 07, 2021 at 12:38:33PM +, Suzuki K Poulose wrote:
CoreSight ETMv4.4 obsoletes memory mapped access to ETM and
mandates the system instructions for registers.
This also implies that they may not be on the amba bus
: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
---
Changes in V1:
- TRBE DT entry has been renamed as 'arm, trace-buffer-extension'
Documentation/devicetree/bindings/arm/trbe.txt | 20
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings
On 1/6/21 11:50 AM, Anshuman Khandual wrote:
On 1/5/21 5:07 PM, Suzuki K Poulose wrote:
On 1/5/21 9:29 AM, Anshuman Khandual wrote:
...
+{
+ struct trbe_buf *buf = etm_perf_sink_config(handle);
+ unsigned long offset;
+
+ if (buf->snapshot)
+ offset = trbe_snapshot_off
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