On 02/03/15 14:17, Beata Michalska wrote:
> From: Tomasz Figa
>
> Add clock controller for CMU ISP clock domain on Exynos3250,
> providing clocks for FIMC-IS subsystem.
>
> [b.michalska:use samsung_cmu_register_one to register
> the provider; updated DT binding documentation]
Thanks for moving
>
> Signed-off-by: Andrzej Hajda
Reviewed-by: Sylwester Nawrocki
> ---
> arch/arm/mach-exynos/pm_domains.c | 27 +++
> 1 file changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-exynos/pm_domains.c
> b/arch/arm/mach
nd we'll need
to address those dependencies somehow.
Anyway, the subject patch looks OK to me, given that support for clocks/
clock-names in the exynos power domain device nodes has been merged
for quite long already.
The entire feature has been merged without PM or clk subsystem
maintainer ACK, I do
Hi,
On 04/03/15 13:24, Kishon Vijay Abraham I wrote:
> This patch doesn't apply on 4.0-rc1. Can to refresh it to mainline
> latest?
It depends on Axel's previous patch: "phy: exynos-mipi-video: Fixup
the test for state->regmap". Are there any issues even with that patch
applied ?
--
Thanks
Sylw
() instead and return proper return value.
>
> Signed-off-by: Axel Lin
Reviewed-by: Sylwester Nawrocki
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1 seems devastated as far as exynos4 is concerned, it may take
some time until I get around and fix all the issues so I tested your
patch on v3.19. It all works well as expected.
Acked-by: Sylwester Nawrocki
Tested-by: Sylwester Nawrocki
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On 26/02/15 04:48, Axel Lin wrote:
> syscon_regmap_lookup_by_phandle() returns ERR_PTR on error.
> Thus don't use null test against state->regmap.
>
> Signed-off-by: Axel Lin
Thanks for the patch, I had this on my todo list.
Acked-by: Sylwester Nawrocki
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On 20/02/15 01:36, Andreas Färber wrote:
>>> >> So it seems the mclk is not always set up properly by the kernel,
>>> >> relying on firmware. Who's in charge of setting that clock up?
>> >
>> > Right, it seems audio is only working due the firmware doing some previous
>> > setup. Probably it works
On 10/02/15 14:14, Krzysztof Kozlowski wrote:
> On wto, 2015-02-10 at 14:00 +0100, Sylwester Nawrocki wrote:
>> > On 10/02/15 13:46, Javier Martinez Canillas wrote:
>>>>>> > >>>> This debugfs code iterates over list of generic_pm_domains
>>>
On 10/02/15 13:46, Javier Martinez Canillas wrote:
This debugfs code iterates over list of generic_pm_domains (gpd_list). I
>> > cannot find function for translating from genpd to its platform device
>> > so only genpd->name can be printed.
>>> >>
>>> >> Then why power domains a
et_sys() so export
> __clk_free_clk() to clkdev.c and do the same thing, except let's
> do some more inline functions to make this code #ifdef free.
>
> This fixes the above crash, properly calls __clk_get() when
> of_clk_get_from_provider() is called, and cleans up the clk
> structu
On 05/02/15 20:44, Sylwester Nawrocki wrote:
>> +void __clk_put(struct clk *clk)
>> > +{
>> > + if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
>> > + return;
>> > +
>> > + clk_core_put(clk->core);
>> > + kfree(clk);
>
> Why d
Hi Mike,
This pull request includes driver for clock controller of the Exynos
5433 SoC. As the hardware is quite complex, with many peripherals and
corresponding clock management units the driver is rather huge. I guess
it will require a bit more cleanups than last time to balance lines
intr
Hi Tomeu,
On 23/01/15 12:03, Tomeu Vizoso wrote:
> int __clk_get(struct clk *clk)
> {
> - if (clk) {
> - if (!try_module_get(clk->owner))
> + struct clk_core *core = !clk ? NULL : clk->core;
> +
> + if (core) {
> + if (!try_module_get(core->owner))
>
On 05/02/15 08:44, Pankaj Dubey wrote:
>> +static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
>> > +
>> > + /* ENABLE_PCLK_APOLLO */
>> > + GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
>> > + "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
>> > +
Hi Chanwoo,
On 02/02/15 15:23, Chanwoo Choi wrote:
> +/*
> + * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
> + * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
> + */
> +static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
> + PLL_35XX_RATE(25, 625, 6, 0),
>
Hi Chanwoo,
On 02/02/15 15:24, Chanwoo Choi wrote:
> This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
> which contain global data buses clocked at up the 400MHz. These blocks
> transfer data between DRAM and various sub-blocks. These clock domains
> also contain global periph
On 03/02/15 13:17, Sylwester Nawrocki wrote:
>> diff --git a/drivers/clk/samsung/clk-exynos5433.c
>> b/drivers/clk/samsung/clk-exynos5433.c
>> > index 3d6164e..cf3f0ac 100644
>> > --- a/drivers/clk/samsung/clk-exynos5433.c
>> > +++ b/drivers/clk/samsung
MIF's clocks
> related to CMU_DISP should be always on state.
Are you sure we need to add anything to CMU_MIF in this patch ?
> Also, CMU_DISP must need the source clock of 'sclk_hdmi_spdif_disp'
> from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI.
>
Hi Chanwoo,
On 02/02/15 16:51, Chanwoo Choi wrote:
> On Mon, Feb 2, 2015 at 11:40 PM, Sylwester Nawrocki
> wrote:
>> > On 02/02/15 15:08, Chanwoo Choi wrote:
>> >
>>> >> OK, I'll add more following information:
>>> >> I'll send
On 02/02/15 15:08, Chanwoo Choi wrote:
> OK, I'll add more following information:
> I'll send only patch1 with following information.
>
> + - clocks: list of clock identifiers which are fed as the input to
> + the given clock controller. Please refer the next section to
> + find the i
Hi Chanwoo,
On 02/02/15 14:01, Chanwoo Choi wrote:
> This patch adds devicetree binding document for Exynos5433 SoC system clock
> controller.
>
> Cc: Sylwester Nawrocki
> Cc: Tomasz Figa
> Signed-off-by: Chanwoo Choi
> Acked-by: Inki Dae
> ---
> .../devicetre
Hi Chanwoo,
On 23/01/15 21:54, Chanwoo Choi wrote:
> On Sat, Jan 24, 2015 at 2:40 AM, Sylwester Nawrocki
> wrote:
>> On 21/01/15 07:26, Chanwoo Choi wrote:
>>> +/* list of all parent clock list */
>>
>>> +PNAME(mout_bus_pll_user_p) = { "fin_pll"
Hi Chanwoo,
On 29/01/15 00:38, Chanwoo Choi wrote:
...
Right. current samsung clock drivers cannot show the hierarchy among clock
domains in DT.
>> IOW, there is currently
>> no way to ensure proper registration order of the CMUs (clock domains).
>> This may be impo
Hi Mike,
The following changes since commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672:
Linux 3.19-rc1 (2014-12-20 17:08:50 -0800)
are available in the git repository at:
git://linuxtv.org/snawrocki/samsung.git tags/v3.20-exynos-clk
for you to fetch changes up to e64fb42da4c6c713cfc7cad607e
On 23/01/15 06:03, Inha Song wrote:
> +static int trats2_aif1_startup(struct snd_pcm_substream *substream)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct trats2_machine_priv *priv = snd_soc_card_get_drvdata(rtd->card);
> + int ret;
> +
> + ret = clk_p
Hi,
On 23/01/15 14:05, Baluta, Teodora wrote:
...
>>> So why not v4l? These are effectively image sensors..
>>
>> Well, here's why I don't think v4l would be the best option:
>>
>> - an image scanner could be implemented in the v4l subsystem, but
>> it seems far more compl
On 21/01/15 07:26, Chanwoo Choi wrote:
> +/* list of all parent clock list */
> +PNAME(mout_bus_pll_user_p) = { "fin_pll", "sclk_bus_pll", };
...
> +
> +static struct samsung_mux_clock top_mux_clks[] __initdata = {
> + MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
> +
On 23/01/15 08:44, Chanwoo Choi wrote:
>>> + cmu_top: clock-controller@0x1003 {
>>> >> +compatible = "samsung,exynos5433-cmu-top";
>>> >> +reg = <0x1003 0x0c04>;
>>> >> +#clock-cells = <1>;
>>> >> +};
>>> >> +
>>> >> +cmu_fs
On 23/01/15 06:03, Inha Song wrote:
> This patch add Trats2 audio subsystem bindings document.
>
> Signed-off-by: Inha Song
Reviewed-by: Sylwester Nawrocki
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On 23/01/15 06:03, Inha Song wrote:
> This patch add WM1811 audio codec, I2S interface and the sound
> machine nodes to enable audio on exynos4412-trats2 board.
>
> Signed-off-by: Inha Song
Reviewed-by: Sylwester Nawrocki
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Hi Chanwoo,
On 21/01/15 07:26, Chanwoo Choi wrote:
> This patch adds the support for CMU (Clock Management Units) of Exynos5433
> which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
> (PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
> for Exynos
On 22/01/15 12:18, Inha Song wrote:
> This patch set clock out parent to XUSBXTI.
>
> Signed-off-by: Inha Song
> ---
> arch/arm/boot/dts/exynos4.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
> index b8168f1..020bb
On 22/01/15 12:18, Inha Song wrote:
> This patch add Trats2 audio subsystem bindings document.
>
> Signed-off-by: Inha Song
Acked-by: Sylwester Nawrocki
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On 22/01/15 12:17, Inha Song wrote:
> diff --git a/sound/soc/samsung/Kconfig b/sound/soc/samsung/Kconfig
> index fc67f97..8031423 100644
> --- a/sound/soc/samsung/Kconfig
> +++ b/sound/soc/samsung/Kconfig
> @@ -245,3 +245,11 @@ config SND_SOC_ARNDALE_RT5631_ALC5631
> depends on SND_SOC_SAM
Hi,
On 09/01/15 16:23, Jacek Anaszewski wrote:
> This patch adds a description of 'flashes' property
> to the samsung-fimc.txt.
>
> Signed-off-by: Jacek Anaszewski
> Acked-by: Kyungmin Park
> ---
> .../devicetree/bindings/media/samsung-fimc.txt |7 +++
> 1 file changed, 7 insertio
Hi,
On 19/01/15 10:48, Inha Song wrote:
> --- a/arch/arm/boot/dts/exynos4412-trats2.dts
> +++ b/arch/arm/boot/dts/exynos4412-trats2.dts
> + sound {
> + compatible = "samsung,trats2-audio";
> + assigned-clocks = <&pmu_system_controller 0>;
> + assigned-cloc
Hi,
On 21/01/15 06:58, Inha Song wrote:
> Add MAX98090 audio codec, I2S interface and the sound nodes to support
> audio on Odroid-XU3 board.
>
> Signed-off-by: Inha Song
> ---
> arch/arm/boot/dts/exynos5422-odroidxu3.dts | 34
> ++
> 1 file changed, 34 insertions(+
On 15/01/15 02:50, Chanwoo Choi wrote:
> This patch adds the divider clock id for Exynos4 memory bus frequency.
> The clock id is used fo DVFS (Dynamic Voltage/Frequency Scaling)
> feature of exynos memory bus frequency.
>
> Cc: Sylwester Nawrocki
> Cc: Tomasz Figa
> Signed
ing both patches via
arm-soc seems a more sane option in this case.
Acked-by: Sylwester Nawrocki
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Sylwester
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Hi,
On 15/01/15 22:03, Pavel Machek wrote:
>> Perhaps we could use the 'reg' property to describe actual connections,
>> > I'm not sure if it's better than a LED specific property, e.g.
>> >
>> > max77387@52 {
>> > compatible = "nxp,max77387";
>> > #address-cells = <2>;
>> >
On 14/01/15 18:14, Baluta, Teodora wrote:
> On Vi, 2014-12-26 at 11:13 +, Jonathan Cameron wrote:
>> On 18/12/14 16:51, Lars-Peter Clausen wrote:
>>> Adding V4L folks to Cc for more input.
>>
>> Thanks Lars - we definitely would need the v4l guys to agree to a driver like
>> this going in IIO.
On 12/01/15 18:06, Mark Brown wrote:
> On Mon, Jan 12, 2015 at 10:55:29AM -0600, Rob Herring wrote:
>> > On Mon, Jan 12, 2015 at 10:10 AM, Jacek Anaszewski
>>> > > There are however devices that don't fall into this category, i.e. they
>>> > > have many outputs, that can be connected to a single LE
On 23/12/14 15:57, Chanwoo Choi wrote:
> I'll fix it and re-send these patch-set.
There is no need, I already corrected it.
The patches are already queued in this branch:
http://git.linuxtv.org/cgit.cgi/snawrocki/samsung.git/log/?h=for-v3.20/clk/next
--
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Sylwester
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Hi Chanwoo,
On 23/12/14 08:40, Chanwoo Choi wrote:
> This patch-set uses the samsung_cmu_register_one() function to simplify the
> clock driver for Exynos3250/Exynos4415 SoC and change return value of
> samsung_cmu_register_one() because some clock driver may need the instance
> of samsung_clk_pro
Hi Vivek,
On 25/11/14 12:48, Vivek Gautam wrote:
> On Sat, Nov 22, 2014 at 8:42 PM, Kukjin Kim wrote:
>> > On 11/22/14 17:40, Kishon Vijay Abraham I wrote:
>>> >> On Friday 21 November 2014 08:41 PM, Felipe Balbi wrote:
...
>>> I took dwc3 driver patches.
>>> >>
>>> >> I took the phy patches
On 18/12/14 01:58, Rafael J. Wysocki wrote:
What's needed to solve this problem is a generalized way to have runtime
> >> PM dependencies between devices. Runtime PM already automatically
> >> handles parent devices as one type of dependent device (e.g. a parent
> >> device nee
On 11/12/14 12:04, Tomasz Figa wrote:
...
>> > On 11/12/14 09:26, Tomasz Figa wrote:
>>> > > From: Sylwester Nawrocki
>>> > >
>>> > > This patch adds notifiers to the runtime PM/genpd subsystem. It is now
>>> > > possible to r
Hi Tomasz,
On 11/12/14 09:26, Tomasz Figa wrote:
> From: Sylwester Nawrocki
>
> This patch adds notifiers to the runtime PM/genpd subsystem. It is now
> possible to register a notifier, which will be called before and after
> the generic power domain subsystem calls the power do
Hi,
On 04/12/14 17:12, Pavel Machek wrote:
+- maxim,boost-mode :
> >>+ In boost mode the device can produce up to 1.2A of total current
> >>+ on both outputs. The maximum current on each output is reduced
> >>+ to 625mA then. If there are two child led nodes defi
On 10/12/14 11:02, Jacek Anaszewski wrote:
+Optional properties:
>>> +- maxim,fleds : Array of current outputs in order: fled1, fled2.
s/current outputs/LED current regulator outputs used/ ?
>>> +Note: both current outputs can be connected to a single led
s/led/LED ? And there
On 09/12/14 15:41, Lee Jones wrote:
struct max77693_led_platform_data {
> >>+ const char *label[2];
> >> u32 fleds[2];
> >> u32 iout_torch[2];for_each_available_child_of_node
> >> u32 iout_flash[2];
> >
nger
> hold adma clock enabled so whole audss domain will be gated).
>
> This is a non-intrusive workaround for that issue, as wanted by
> Sylwester:
> https://lkml.org/lkml/2014/12/5/223
>
> Any comments on this?
The patch looks OK to me, it would be good though if someone el
d to a mutex so that vb2 helpers
> vb2_ops_wait_prepare/finish() can make use of it.
>
> Signed-off-by: Lad, Prabhakar
> Cc: Sylwester Nawrocki
Acked-by: Sylwester Nawrocki
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On 05/12/14 13:34, Javier Martinez Canillas wrote:
> Hello Sylwester,
>
> On 12/05/2014 12:22 PM, Sylwester Nawrocki wrote:
>>> >> Tested-by: Javier Martinez Canillas
>> >
>> > Can you confirm sound works with this patch on exynos5420 ? Or does
&g
Hi Krzysztof,
On 05/12/14 12:00, Krzysztof Kozlowski wrote:
> Audio subsystem clocks are located in separate block. If clock for this
> block (from main clock domain) 'mau_epll' is gated then any read or
> write to audss registers will block.
>
> This was observed on Exynos 5420 platforms (Arndal
Javier,
On 05/12/14 12:00, Krzysztof Kozlowski wrote:
> Audio subsystem clocks are located in separate block. If clock for this
> block (from main clock domain) 'mau_epll' is gated then any read or
> write to audss registers will block.
>
> This was observed on Exynos 5420 platforms (Arndale Octa
On 04/12/14 11:47, Krzysztof Kozlowski wrote:
> Audio subsystem clocks are located in separate block. If clock for this
> block (from main clock domain) 'mau_epll' is gated then any read or
> write to audss registers will block.
>
> This was observed on Exynos 5420 platforms (Arndale Octa and Peac
On 26/11/14 15:24, Krzysztof Kozlowski wrote:
> Audio subsystem clocks are located in separate block. If clock for this
> block (from main clock domain) 'mau_epll' is gated then any read or
> write to audss registers will block.
>
> This was observed on Exynos 5420 platforms (Arndale Octa and Peac
On 26/11/14 15:24, Krzysztof Kozlowski wrote:
> During driver unbind the syscore ops were not unregistered which lead to
> double add on syscore list:
>
> $ echo "381.audss-clock-controller" >
> /sys/bus/platform/drivers/exynos-audss-clk/unbind
> $ echo "381.audss-clock-controller" >
> /
on
> CONFIG_PM.
>
> The alternative of CONFIG_PM_SLEEP and CONFIG_PM_RUNTIME may be
> replaced with CONFIG_PM too.
>
> Make these changes everywhere under drivers/media/.
>
> Signed-off-by: Rafael J. Wysocki
Acked-by: Sylwester Nawrocki
> ---
>
> Note: This
Hi,
On 27/11/14 12:56, Chanwoo Choi wrote:
> On 11/27/2014 08:41 PM, Arnd Bergmann wrote:
>> > On Thursday 27 November 2014 16:35:08 Chanwoo Choi wrote:
>>> >> + - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
>>> >> +and "samsung,exynos5433-cmu-bus2" - clock controller compati
QVGA_HEIGHT 240
>
> +#define SVGA_WIDTH 800
> +#define SVGA_HEIGHT 680
I think this should be 600. With that fixed, for both patches:
Acked-by: Sylwester Nawrocki
> #define SXGA_WIDTH 1280
> #define SXGA_HEIGHT 1024
>
> #define VGA_WIDTH640
> #define VGA_HE
On 04/11/14 20:52, Paul Bolle wrote:
> On Tue, 2014-11-04 at 11:42 -0800, Greg KH wrote:
>> > As it's something that no one seemed to ever need before (i.e. it's not
>> > a regression fix), but it would be a "new feature", I don't think it's
>> > really a stable fix.
>> >
>> > But feel free to con
On 04/11/14 00:24, Greg KH wrote:
> On Tue, Oct 07, 2014 at 11:12:07AM +0200, Sylwester Nawrocki wrote:
>> > The PLAT_S5P Kconfig symbol was removed in commit d78c16ccde96
>> > ("ARM: SAMSUNG: Remove remaining legacy code"). There are still
>> > some ref
On 28/10/14 05:09, Kukjin Kim wrote:
> Sylwester Nawrocki wrote:
>>
>> On 27/10/14 02:11, Chanwoo Choi wrote:
>>> Chanwoo Choi (2):
>>> clk: samsung: exynos4415: Add clocks using common clock framework
>>> clk: samsung: Document binding for Exynos4415
On 27/10/14 02:11, Chanwoo Choi wrote:
> Chanwoo Choi (2):
> clk: samsung: exynos4415: Add clocks using common clock framework
> clk: samsung: Document binding for Exynos4415 clock controller
Added both to my tree, thanks. In future please put DT binding
documentation first in the series, befo
Hi Chanwoo,
On 24/10/14 16:07, Chanwoo Choi wrote:
[...]
>> How about prefixing the table names below with "exynos4415", rather than
>> "samsung" ?
>
> 'struct samsung_fixed_factor_clock' is common for Exynos SoC.
>
> Do you means that add 'exynos4415' prefix as following:
> - fixed_factor_clks
On 24/10/14 15:18, Daniel Drake wrote:
> On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote:
>> > This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
>> > using common clock framework. The CMU (Clock Management Unit) of Exynos4415
>> > controls PLLs(Phase Locked Loops) and g
n clocks for individual IPs.
>
> Cc: Sylwester Nawrocki
> Cc: Tomasz Figa
> Signed-off-by: Chanwoo Choi
> Signed-off-by: Tomasz Figa
> Signed-off-by: Seung-Woo Kim
> Acked-by: Kyungmin Park
Thanks for the update, there are still couple issues pointed out
by checkpatch.p
n clocks for individual IPs.
>
> Cc: Sylwester Nawrocki
> Cc: Tomasz Figa
> Signed-off-by: Chanwoo Choi
> Signed-off-by: Tomasz Figa
> Signed-off-by: Seung-Woo Kim
> Acked-by: Kyungmin Park
The patch looks good to me, I've applied it to my tree and will
be sending i
inding is not supposed
to depend on any OS. Instead I would just put here something like:
"This patch adds DT binding documentation for Exynos4415 SoC system
clock controllers."
> Cc: Sylwester Nawrocki
> Cc: Tomasz Figa
> Signed-off-by: Chanwoo Choi
> Acked-by: Kyungmi
Paul Bolle
Acked-by: Jingoo Han
Cc: [3.17+]
Signed-off-by: Sylwester Nawrocki
---
Changes since v2:
- updated the commit description.
drivers/usb/host/Kconfig |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
in
The PLAT_S5P Kconfig symbol was removed in commit d78c16ccde96
("ARM: SAMSUNG: Remove remaining legacy code"). There are still
some references left, fix that by replacing them with ARCH_S5PV210.
Reported-by: Paul Bolle
Signed-off-by: Sylwester Nawrocki
---
drivers/usb/host/Kcon
On 06/10/14 14:37, Sergei Shtylyov wrote:
>> diff --git a/drivers/media/platform/exynos4-is/Kconfig
>> b/drivers/media/platform/exynos4-is/Kconfig
>> index 77c951237744..775c3278d0eb 100644
>> --- a/drivers/media/platform/exynos4-is/Kconfig
>> +++ b/drivers/media/platform/exynos4-is/Kconfig
>> @@
On 06/10/14 11:26, Arnd Bergmann wrote:
> On Monday 06 October 2014 11:10:26 Paul Bolle wrote:
>> config VIDEO_SAMSUNG_S5P_TV
>> bool "Samsung TV driver for S5P platform"
>> depends on PM_RUNTIME
>> - depends on PLAT_S5P || ARCH_EXYNOS || COMPILE_TEST
>> + depends on AR
() couldn't simply be used, since
> exynos4_jpeg_sw_reset() is called with a spinlock held.
>
> So, let's use ndelay() instead.
>
> Reported-by: Stephen Rothwell
> Signed-off-by: Mauro Carvalho Chehab
Acked-by: Sylwester Nawrocki
--
Thanks,
Sylwester
--
To unsubscribe from this li
On 09/09/14 16:38, Mauro Carvalho Chehab wrote:
> ERROR: "__bad_ndelay" [drivers/media/platform/s5p-jpeg/s5p-jpeg.ko] undefined!
>
> Yet, it sounds a bad idea to use ndelay to wait for 100 us
> for the device to reset.
>
> Reported-by: Stephen Rothwell
> Signed-off-by: Mauro Carvalho Chehab
>
On 13/08/14 22:34, Mark Brown wrote:
> On Fri, Jul 25, 2014 at 02:42:31PM -0700, Mike Turquette wrote:
>> Quoting Sylwester Nawrocki (2014-07-03 10:25:53)
>
>>> I would appreciate a DT, SPI or the I2C maintainer opinions.
>
>> Yes, Acks from SPI and I2C maintainers
(dropping linux-doc ML and Randy from Cc)
On 31/07/14 13:22, Humberto Silva Naves wrote:
> This implements the fixed rate clocks generated either inside or
> outside the SoC. It also adds a dt-binding constant for the
> sclk_hdmiphy clock, which shall be later used by other drivers,
> such as the
On 11/07/14 14:00, Tushar Behera wrote:
> @@ -103,17 +140,11 @@ static int exynos_audss_clk_probe(struct
> platform_device *pdev)
> return PTR_ERR(reg_base);
> }
>
> - clk_table = devm_kzalloc(&pdev->dev,
> - sizeof(struct clk *) * EXYNOS_AUDSS
roviders
are probed in of_clk_init() is not guaranteed. Since deferred probing
is not supported in of_clk_init() and the AudioSS block is not the core
controller, we can initialize it later as a platform device.
Signed-off-by: Andrew Bresticker
Acked-by: Tomasz Figa
Revie
On 18/06/14 17:29, Sylwester Nawrocki wrote:
> This patch adds helper functions to configure clock parents and rates
> as specified through 'assigned-clock-parents', 'assigned-clock-rates'
> DT properties for a clock provider or clock consumer device.
> The helpers
On 02/07/14 13:49, Peter De Schrijver wrote:
> Or if you use notifiers which use i2c... See also
> http://comments.gmane.org/gmane.linux.kernel/1553699. One workaround is to
> always leave the clock of the i2c controller in a prepared state.
Keeping the clock always prepared might not be that bad,
I busses, before the driver probing and also in the clock core
after registration of a clock provider.
Signed-off-by: Sylwester Nawrocki
Acked-by: Kyungmin Park
---
Changes since v6:
- use a set of separate DT properties to specify the default parent
clocks and rates;
- the clock defaults
for maximum DT property
name length for now.
This series has been tested on ARM, on Exynos4412 Odroid U3 board.
The full git tree can be found at:
git://linuxtv.org/snawrocki/samsung.git v3.16-rc1-odroid-sound-clk
and browsed at
http://git.linuxtv.org/cgit.cgi/snawrocki/samsung.git/log/?h=v
Please ignore this patch, I'll send the correct one in a while.
My apologies for spamming.
On 18/06/14 12:47, Sylwester Nawrocki wrote:
> This patch adds helper functions to configure clock parents and rates
> as specified through 'assigned-clock-parents', 'assigned-cl
I busses, before the driver probing and also in the clock core
after registration of a clock provider.
Signed-off-by: Sylwester Nawrocki
Acked-by: Kyungmin Park
---
Changes since v6:
- use a set of separate DT properties to specify the default parent
clocks and rates;
- the clock defaults
linuxtv.org/snawrocki/samsung.git v3.16-rc1-odroid-sound-clk
and browsed at
http://git.linuxtv.org/cgit.cgi/snawrocki/samsung.git/log/?h=v3.16-rc1-odroid-sound-clk
Sylwester Nawrocki (1):
clk: Support for clock parents and rates assigned from device tree
.../devicetree/bindings
lets us to avoid casting to struct device_node * or caching variables
internally in drivers just to be able to properly drop a reference to the
OF node on clean up paths.
Signed-off-by: Sylwester Nawrocki
---
include/sound/soc.h |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
di
On 27/05/14 12:28, Tushar Behera wrote:
> On 05/19/2014 10:52 PM, Sylwester Nawrocki wrote:
>> This patch adds a helper function to configure clock parents and
>> rates as specified in clock-parents, clock-rates DT properties
>> for a consumer device and a call to it before dr
On 23/05/14 08:37, Tero Kristo wrote:
> On 05/23/2014 04:34 AM, Mike Turquette wrote:
[...]
>> It looks like this idea was dropped for v6. Can we revisit it? Take a
>> look at Tero's example implementation for OMAP using this binding:
>>
>> http://www.spinics.net/lists/linux-omap/msg104705.html
>>
On 23/05/14 03:34, Mike Turquette wrote:
> Quoting Sylwester Nawrocki (2014-04-11 05:25:49)
>>>> +==Assigned clock parents and rates==
>>>> +
>>>> +Some platforms require static initial configuration of parts of the clocks
>>>> +controller. Such a
Hi Sachin,
On 29/05/14 08:30, Sachin Kamat wrote:
> PTR_ERR_OR_ZERO simplifies the code.
>
> Signed-off-by: Sachin Kamat
> Cc: Sylwester Nawrocki
> ---
> drivers/phy/phy-exynos-mipi-video.c |5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> d
&clk_gate_ops, CLK_SET_RATE_PARENT
>>>>> >>>> +| CLK_SET_RATE_NO_REPARENT);
>>>> >>>
>>>> >>> Would you please remove CLK_SET_RATE_NO_REPARENT flag from here? Let me
>>>> &g
ARENT flag from here? Let me
>>> know if you have reservations against this.
>>
>> The problem with clock reparenting is that there are certain parent
>> clocks of CLKOUT, rate of which changes at runtime, e.g. clocks derived
>> from APLL or bus clocks, which can b
On 19/05/14 19:22, Sylwester Nawrocki wrote:
> @@ -2620,7 +2639,10 @@ void __init of_clk_init(const struct of_device_id
> *matches)
> list_for_each_entry_safe(clk_provider, next,
> &clk_provider_list, node) {
>
This patch adds a helper function to configure clock parents and
rates as specified in clock-parents, clock-rates DT properties
for a consumer device and a call to it before driver is bound to
a device.
Signed-off-by: Sylwester Nawrocki
---
Changes since v5:
- updated the DT binding description
This patch adds of_clk_get_by_clkspec() helper function, which does only
a struct clk lookup from the clock providers. It is used in the subsequent
patch where parsing of a clock from device tree and the lookup from
providers needed to be split.
Signed-off-by: Sylwester Nawrocki
---
Changes
nts/clock-rates properties
are not yet available; an alternative would be to let drivers call
of_clk_device_setup() directly,
- dropped the patch adding a macro definition for maximum DT property
name length for now.
This series has been tested on ARM, on Exynos4412 Odroid U3 board.
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