On 11/3/20 6:53 AM, Jim Mattson wrote:
On Sun, Nov 1, 2020 at 10:14 PM Tao Xu wrote:
There are some cases that malicious virtual machines can cause CPU stuck
(event windows don't open up), e.g., infinite loop in microcode when
nested #AC (CVE-2015-5307). No event window obviously mea
On 11/3/20 12:43 AM, Andy Lutomirski wrote:
On Sun, Nov 1, 2020 at 10:14 PM Tao Xu wrote:
There are some cases that malicious virtual machines can cause CPU stuck
(event windows don't open up), e.g., infinite loop in microcode when
nested #AC (CVE-2015-5307). No event window obvi
On 11/3/20 1:32 AM, Sean Christopherson wrote:
On Mon, Nov 02, 2020 at 02:14:45PM +0800, Tao Xu wrote:
There are some cases that malicious virtual machines can cause CPU stuck
(event windows don't open up), e.g., infinite loop in microcode when
nested #AC (CVE-2015-5307). No event w
On 11/3/20 1:31 AM, Sean Christopherson wrote:
On Mon, Nov 02, 2020 at 08:43:30AM -0800, Andy Lutomirski wrote:
On Sun, Nov 1, 2020 at 10:14 PM Tao Xu wrote:
2. Another patch to disable interception of #DB and #AC when notify
VM-Exiting is enabled.
Whoa there.
A VM control that says
, and user can set it to 0 to disable
this feature.
TODO:
1. The appropriate value of notify window.
2. Another patch to disable interception of #DB and #AC when notify
VM-Exiting is enabled.
Co-developed-by: Xiaoyao Li
Signed-off-by: Tao Xu
Signed-off-by: Xiaoyao Li
---
arch/x86/include
On 5/21/2020 2:37 PM, Xiaoyao Li wrote:
On 5/21/2020 1:28 PM, Tao Xu wrote:
On 5/21/2020 12:33 PM, Xiaoyao Li wrote:
On 5/21/2020 5:05 AM, Paolo Bonzini wrote:
On 20/05/20 18:07, Maxim Levitsky wrote:
This msr is only available when the host supports WAITPKG feature.
This breaks a
On 5/21/2020 12:33 PM, Xiaoyao Li wrote:
On 5/21/2020 5:05 AM, Paolo Bonzini wrote:
On 20/05/20 18:07, Maxim Levitsky wrote:
This msr is only available when the host supports WAITPKG feature.
This breaks a nested guest, if the L1 hypervisor is set to ignore
unknown msrs, because the only ot
On 7/20/2019 1:18 AM, Paolo Bonzini wrote:
On 19/07/19 08:31, Tao Xu wrote:
Ping for comments :)
Hi, I'll look at it for 5.4, right after the merge window.
Paolo
Hi paolo,
Linux 5.3 has released, could you review these patches. Thank you very much!
Tao
On 7/16/2019 2:55 PM, Tao Xu
5-145
"Memory Proximity Domain Attributes Structure"
for Flags.
Looks good to me.
Reviewed-by: Tao Xu
Signed-off-by: Daniel Black
---
drivers/acpi/hmat/hmat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/acpi/hmat/hmat.c b/drivers/acpi/hmat/hmat.c
ind
On 7/20/2019 1:18 AM, Paolo Bonzini wrote:
On 19/07/19 08:31, Tao Xu wrote:
Ping for comments :)
Hi, I'll look at it for 5.4, right after the merge window.
Paolo
Thank you Paolo!
On 7/16/2019 2:55 PM, Tao Xu wrote:
UMONITOR, UMWAIT and TPAUSE are a set of user wait instruc
Ping for comments :)
On 7/16/2019 2:55 PM, Tao Xu wrote:
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
UMONITOR arms address monitoring hardware using an address. A store
to an address within the specified address range triggers the
monitoring hardware to wake up the
On 7/17/2019 9:17 AM, Tao Xu wrote:
On 7/17/2019 12:03 AM, Eduardo Habkost wrote:
On Fri, Jul 12, 2019 at 04:29:06PM +0800, Tao Xu wrote:
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
to determines the maximum time in TSC-quanta that the processor can
reside
in
On 7/17/2019 12:03 AM, Eduardo Habkost wrote:
On Fri, Jul 12, 2019 at 04:29:06PM +0800, Tao Xu wrote:
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
to determines the maximum time in TSC-quanta that the processor can reside
in either C0.1 or C0.2.
This patch emulates
variable
mwait_control_cached in arch/x86/kernel/cpu/umwait.c caches the MSR value,
so this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
Changes in v8:
- Add an accessor to expose
ff-by: Tao Xu
---
Changes in v8:
- Introduce a common exit helper handle_unexpected_vmexit (Sean)
---
arch/x86/include/uapi/asm/vmx.h | 6 +-
arch/x86/kvm/vmx/nested.c | 4
arch/x86/kvm/vmx/vmx.c | 28
3 files changed, 21 insertions(+
be found in the
latest Intel 64 and IA-32 Architectures Software Developer's Manual.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
Changes in v8:
- Remove unnecessary comments (Sean)
- Add vmx_waitpkg_supported() helper (Sean)
---
arch/x86/include
wait_control_msr()(Xiaoyao)
Tao Xu (3):
KVM: x86: Add support for user wait instructions
KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
KVM: vmx: Introduce handle_unexpected_vmexit and handle WAITPKG vmexit
arch/x86/include/asm/vmx.h | 1 +
arch/x86/include/uapi/asm/vmx.h | 6 ++-
arch/x86/ker
On 7/12/2019 11:52 PM, Sean Christopherson wrote:
On Fri, Jul 12, 2019 at 04:29:06PM +0800, Tao Xu wrote:
diff --git a/arch/x86/kernel/cpu/umwait.c b/arch/x86/kernel/cpu/umwait.c
index 6a204e7336c1..631152a67c6e 100644
--- a/arch/x86/kernel/cpu/umwait.c
+++ b/arch/x86/kernel/cpu/umwait.c
On 7/12/2019 11:13 PM, Sean Christopherson wrote:
On Fri, Jul 12, 2019 at 04:29:05PM +0800, Tao Xu wrote:
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 46af3a5e9209..a4d5da34b306 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -2048,6 +2048,7
On 7/13/2019 12:03 AM, Sean Christopherson wrote:
On Fri, Jul 12, 2019 at 04:29:07PM +0800, Tao Xu wrote:
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -5213,6 +5213,9 @@ bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32
exit_reason)
case EXIT_REASON_ENCLS
d in the
latest Intel 64 and IA-32 Architectures Software Developer's Manual.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
Changes in v7:
- Add nested support for user wait instructions (Paolo)
---
arch/x86/include/asm/vmx.h | 1 +
arch/x86/kvm/cpuid.c
appen.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
Changes in v7:
- Add nested exit reason for UMWAIT and TPAUSE (Paolo)
---
arch/x86/include/uapi/asm/vmx.h | 6 +-
arch/x86/kvm/vmx/nested.c | 3 +++
arch/x86/kvm/vmx/vmx.c
variable
mwait_control_cached in arch/x86/power/umwait.c caches the MSR value, so
this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
Changes in v7:
- Use the test on vmx->secondary_exec_control
wait_control_msr()(Xiaoyao)
Tao Xu (3):
KVM: x86: add support for user wait instructions
KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
KVM: vmx: handle vm-exit for UMWAIT and TPAUSE
arch/x86/include/asm/vmx.h | 1 +
arch/x86/include/uapi/asm/vmx.h | 6 ++-
arch/x86/kernel/cpu/umwait.c| 3
On 7/11/2019 9:25 PM, Paolo Bonzini wrote:
On 21/06/19 07:57, Tao Xu wrote:
+ if (guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG))
+ atomic_switch_umwait_control_msr(vmx);
+
guest_cpuid_has is slow. Please replace it with a test on
secondary_exec_controls_get(vmx).
Thank you
Ping ;)
On 6/21/2019 1:57 PM, Tao Xu wrote:
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
to determines the maximum time in TSC-quanta that the processor can reside
in either C0.1 or C0.2.
This patch emulates MSR IA32_UMWAIT_CONTROL in guest and differentiate
On 7/3/2019 12:37 AM, Paolo Bonzini wrote:
On 20/06/19 11:46, Xiaoyao Li wrote:
You cannot put the atomic switch here. What if umwait_control_cached is changed
at runtime? Host kernel patch exposed a sysfs interface to let it happen.
Thanks for the review, Xiaoyao. I agree with both of your r
d in the
latest Intel 64 and IA-32 Architectures Software Developer's Manual.
Reviewed-by: Xiaoyao Li
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
No changes in v6
---
arch/x86/include/asm/vmx.h | 1 +
arch/x86/kvm/cpuid.c | 2 +-
arch/x86/kvm/vmx/v
appen.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
No changes in v6
---
arch/x86/include/uapi/asm/vmx.h | 6 +-
arch/x86/kvm/vmx/vmx.c | 16
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/uapi/asm/
variable
mwait_control_cached in arch/x86/power/umwait.c caches the MSR value, so
this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
Changes in v6:
add check msr_info->host_initiated in get/
OL (Paolo and Xiaoyao)
Handle vm-exit for UMWAIT and TPAUSE as "never happen" (Paolo)
v2:
Separated from the series https://lkml.org/lkml/2018/7/10/160
Add provide a capability to enable UMONITOR, UMWAIT and TPAUSE
v1:
Sent out with MOVDIRI/MOVDIR64B instruct
d in the
latest Intel 64 and IA-32 Architectures Software Developer's Manual.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
Changes in v5:
remove vmx_waitpkg_supported() and use
guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG) directly (Xiaoyao)
-
variable
mwait_control_cached in arch/x86/power/umwait.c caches the MSR value, so
this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
Changes in v5:
remove vmx_waitpkg_supported() to fix guest can
appen.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
No changes in v5.
---
arch/x86/include/uapi/asm/vmx.h | 6 +-
arch/x86/kvm/vmx/vmx.c | 16
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/uap
ies https://lkml.org/lkml/2018/7/10/160
Add provide a capability to enable UMONITOR, UMWAIT and TPAUSE
v1:
Sent out with MOVDIRI/MOVDIR64B instructions patches
Tao Xu (3):
KVM: x86: add support for user wait instructions
KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
KVM: vmx: handl
t msr.
Besides, vmx_compute_secondary_exec_control() adjusts
SECONDARY_EXEC_XSAVES bit based on guest cpuid's X86_FEATURE_XSAVE
and X86_FEATURE_XSAVES, it should use updated value to decide whether
set XSS_EXIT_BITMAP.
Co-developed-by: Xiaoyao Li
Signed-off-by: Xiaoyao Li
Signed-off-by: Tao Xu
On 6/19/2019 3:16 PM, Xiaoyao Li wrote:
On 6/19/2019 3:01 PM, Tao Xu wrote:
On 6/19/2019 2:23 PM, Xiaoyao Li wrote:
On 6/19/2019 2:09 PM, Tao Xu wrote:
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
This patch adds support for user wait instructions in KVM. Availability
of
On 6/19/2019 2:23 PM, Xiaoyao Li wrote:
On 6/19/2019 2:09 PM, Tao Xu wrote:
UMONITOR, UMWAIT and TPAUSE are a set of user wait instructions.
This patch adds support for user wait instructions in KVM. Availability
of the user wait instructions is indicated by the presence of the CPUID
feature
pen" (Paolo)
v2:
Separated from the series https://lkml.org/lkml/2018/7/10/160
Add provide a capability to enable UMONITOR, UMWAIT and TPAUSE
v1:
Sent out with MOVDIRI/MOVDIR64B instructions patches
Tao Xu (3):
KVM: x86: add support for user wait instructions
K
d in the
latest Intel 64 and IA-32 Architectures Software Developer's Manual.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
no changes in v4.
---
arch/x86/include/asm/vmx.h | 1 +
arch/x86/kvm/cpuid.c| 2 +-
arch/x86/kvm/vmx/capabilities.h
appen.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
no changes in v4
---
arch/x86/include/uapi/asm/vmx.h | 6 +-
arch/x86/kvm/vmx/vmx.c | 16
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/uapi/asm/
variable
mwait_control_cached in arch/x86/power/umwait.c caches the MSR value, so
this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
Changes in v4:
Set msr of IA32_UMWAIT_CONTROL can be 0 and add the
On 6/17/2019 11:32 AM, Xiaoyao Li wrote:
On 6/16/2019 5:55 PM, Tao Xu wrote:
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
to determines the maximum time in TSC-quanta that the processor can
reside
in either C0.1 or C0.2.
This patch emulates MSR
On 6/17/2019 11:50 PM, Radim Krčmář wrote:
2019-06-17 14:31+0800, Xiaoyao Li:
On 6/17/2019 11:32 AM, Xiaoyao Li wrote:
On 6/16/2019 5:55 PM, Tao Xu wrote:
+ if (vmx->msr_ia32_umwait_control != host_umwait_control)
+ add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONT
nd Xiaoyao)
Handle vm-exit for UMWAIT and TPAUSE as "never happen" (Paolo)
v2:
Separated from the series https://lkml.org/lkml/2018/7/10/160
Add provide a capability to enable UMONITOR, UMWAIT and TPAUSE
v1:
Sent out with MOVDIRI/MOVDIR64B instructions patches
Tao Xu
appen.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
arch/x86/include/uapi/asm/vmx.h | 6 +-
arch/x86/kvm/vmx/vmx.c | 16
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/uapi/asm/vmx.h b/arch/x86/in
d in the
latest Intel 64 and IA-32 Architectures Software Developer's Manual.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
arch/x86/include/asm/vmx.h | 1 +
arch/x86/kvm/cpuid.c| 2 +-
arch/x86/kvm/vmx/capabilities.h | 6 ++
ar
variable
mwait_control_cached in arch/x86/power/umwait.c caches the MSR value, so
this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
arch/x86/kvm/vmx/vmx.c | 36
arch
appen.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
arch/x86/include/uapi/asm/vmx.h | 6 +-
arch/x86/kvm/vmx/vmx.c | 16
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/uapi/asm/vmx.h b/arch/x86/in
variable
mwait_control_cached in arch/x86/power/umwait.c caches the MSR value, so
this patch uses it to avoid frequently rdmsr of IA32_UMWAIT_CONTROL.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
arch/x86/kvm/vmx/vmx.c | 36
arch
ent out with MOVDIRI/MOVDIR64B instructions patches
Tao Xu (3):
KVM: x86: add support for user wait instructions
KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL
KVM: vmx: handle vm-exit for UMWAIT and TPAUSE
arch/x86/include/asm/vmx.h | 1 +
arch/x86/include/uapi/asm/vmx.h | 6 +++-
d in the
latest Intel 64 and IA-32 Architectures Software Developer's Manual.
Co-developed-by: Jingqi Liu
Signed-off-by: Jingqi Liu
Signed-off-by: Tao Xu
---
arch/x86/include/asm/vmx.h | 1 +
arch/x86/kvm/cpuid.c| 2 +-
arch/x86/kvm/vmx/capabilities.h | 6 ++
ar
On 29/05/2019 09:24, Paolo Bonzini wrote:
On 24/05/19 09:56, Tao Xu wrote:
+7.19 KVM_CAP_ENABLE_USR_WAIT_PAUSE
+
+Architectures: x86
+Parameters: args[0] whether feature should be enabled or not
+
+With this capability enabled, a VM can use UMONITOR, UMWAIT and TPAUSE
+instructions. If the
On 2/22/2019 3:24 AM, Yu, Fenghua wrote:
On Wed, Feb 20, 2019 at 10:37:27PM -0800, Andy Lutomirski wrote:
On Wed, Feb 20, 2019 at 7:44 PM Tao Xu wrote:
From: Fenghua Yu
From patchwork Wed Jan 16 21:18:41 2019
Content-Type: text/plain; charset="utf-8"
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