On 24/07/2019 09:47, Tony Lindgren wrote:
* Suman Anna [190723 21:02]:
Hi Tony,
On 7/23/19 6:28 AM, Tony Lindgren wrote:
The ahclkr clkctrl clock bit 28 only exists for mcasp 1 and 2 on dra7.
Otherwise we get the following warning on beagle-x15:
...
@@ -2962,9 +2958,8 @@
Hi,
Mostly some cosmetic comments below, other than that seems fine to me.
On 30/07/2019 12:34, Peter Ujfalusi wrote:
From: Grygorii Strashko
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There
Hi,
Here are a few patches to fix reset handling for ti-sysc bus driver.
Without these, the iommu won't be working properly at least.
-Tero
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
: Tero Kristo
---
drivers/bus/ti-sysc.c | 25 +
1 file changed, 5 insertions(+), 20 deletions(-)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
index ad9c6d3..e08125a 100644
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -95,7 +95,6 @@ struct sysc
Parenting clockdomain for the IP should be enabled during the reset
handling logic, otherwise the reset may not finish properly. Re-order
the clockdomain control logic to avoid this.
Signed-off-by: Tero Kristo
---
drivers/bus/ti-sysc.c | 9 +
1 file changed, 5 insertions(+), 4 deletions
Some devices need to share their reset signals, like DSP MMUs, thus drop
the exclusive notation from reset request. Also, balance the init time
reset count, otherwise the resets will never be applied post boot.
Signed-off-by: Tero Kristo
---
drivers/bus/ti-sysc.c | 12 +---
1 file
On 11/07/2019 08:49, Keerthy wrote:
On 29/06/19 2:07 AM, Nishanth Menon wrote:
On 09:08-20190628, Keerthy wrote:
[..]
+ select GPIO_SYSFS
+ select GPIO_DAVINCI
Could you help explain the logic of doing this? commit message is
basically the diff in English. To me, this does NOT make s
On 22/05/2019 19:19, Nishanth Menon wrote:
Hi,
This series adds support for the latest new SoC, J721E, from Texas Instruments.
The series is an based off v5.2-rc1 and has the following driver
dependencies for a successful boot:
1. https://lore.kernel.org/lkml/20190429131533.25122-1-...@ti.com
On 07/06/2019 23:58, Suman Anna wrote:
Hi Nishanth, Tero,
On 5/22/19 11:19 AM, Nishanth Menon wrote:
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster,
On 22/05/2019 19:19, Nishanth Menon wrote:
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad mark
On 07/06/2019 22:35, Andrew F. Davis wrote:
This patch adds a driver for the Page-based Address Translator (PAT)
present on various TI SoCs. A PAT device performs address translation
using tables stored in an internal SRAM. Each PAT supports a set number
of pages, each occupying a programmable 4K
On 29/05/2019 12:18, Kishon Vijay Abraham I wrote:
Patch series adds PCIe and SERDES DT nodes to k3-am65.dtsi and keeps
them disabled in k3-am654-base-board.dts since there are no PCIe
slots in the base board.
PCIe slots are actually present in add on boards. Once overlay support
is merged, I'll
On 08/06/2019 06:51, keerthy wrote:
On 6/8/2019 4:09 AM, Linus Walleij wrote:
On Thu, Jun 6, 2019 at 11:55 AM Keerthy wrote:
The patch adds k3 am654 compatible, specific properties and
an example.
Signed-off-by: Keerthy
Patch applied with the three others, so now all
GPIO changes are in
On 06/06/2019 12:56, Keerthy wrote:
Add gpio0/1 nodes under main domain. They have 96 and 90 gpios
respectively and all are capable of generating banked interrupts.
Signed-off-by: Keerthy
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 32
1 file changed, 32 insertion
On 05/06/2019 09:14, Keerthy wrote:
Enable GPIO_DAVINCI and related configs for TI K3 AM6 platforms.
Signed-off-by: Keerthy
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d1b72f99e2f4..
On 10/06/2019 20:16, santosh.shilim...@oracle.com wrote:
On 6/10/19 5:19 AM, Tero Kristo wrote:
On 08/06/2019 00:35, santosh.shilim...@oracle.com wrote:
On 6/5/19 3:33 PM, Suman Anna wrote:
Texas Instrument's System Control Interface (TI-SCI) Message Protocol
is used in Texas Instrum
On 10/06/2019 12:41, Lokesh Vutla wrote:
On 10/06/19 2:48 PM, Peter Ujfalusi wrote:
Configuration of NAVSS resource, like rings, UDMAP channels, flows
and PSI-L thread management need to be done via TISCI.
Add the needed structures and functions for NAVSS resource configuration of
the followi
On 28/05/2019 18:55, Andrew F. Davis wrote:
TI-SCI firmware will only respond to messages when the
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED flag is set. Most messages already do
this, set this for the ones that do not.
This will be enforced in future firmware that better match the TI-SCI
specifications,
On 08/06/2019 00:35, santosh.shilim...@oracle.com wrote:
On 6/5/19 3:33 PM, Suman Anna wrote:
Texas Instrument's System Control Interface (TI-SCI) Message Protocol
is used in Texas Instrument's System on Chip (SoC) such as those
in K3 family AM654 SoC to communicate between various compute
proce
Sorry, this has sort of slipped through. I can pick this up and queue
towards 5.2-rc fixes.
-Tero
On 04/06/2019 11:33, Yuehaibing wrote:
Hi all,
Friendly ping:
Who can take this?
On 2019/5/10 11:52, YueHaibing wrote:
Fix Kbuild warning when SOC_TI is not set
WARNING: unmet direct dependen
ns:
Acked-by: Tero Kristo
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
On 12/05/2019 13:03, YueHaibing wrote:
There is no callers in tree, so can be removed.
Looks ok to me, basically legacy code that we forgot to remove while doing:
commit 7558562a70fbd6b3fa746fa33c76c9333aa0bb32
Author: Tony Lindgren
Date: Thu Dec 14 08:32:06 2017 -0800
clk: ti: Drop le
On 12/04/2019 07:24, Lokesh Vutla wrote:
On 11/04/19 8:30 PM, Tony Lindgren wrote:
Hi,
* Lokesh Vutla [190410 04:15]:
+Example:
+
+The following example demonstrates both interrupt router node and the consumer
+node(main gpio) on the AM654 SoC:
+
+main_intr: interrupt-controller0 {
On 28/03/2019 14:31, Rob Herring wrote:
On Tue, Mar 12, 2019 at 02:35:17PM +0530, Vignesh Raghavendra wrote:
Add dt bindings for TI syscon gate clock.
Signed-off-by: Vignesh Raghavendra
---
.../bindings/clock/ti,syscon-gate-clock.txt | 35 +++
1 file changed, 35 insertions
On 09/02/2019 20:53, Andreas Kemnade wrote:
On Mon, 21 Jan 2019 11:58:03 -0800
Tony Lindgren wrote:
* Andreas Kemnade [190116 14:04]:
On the gta04 with a dm3730 omap_hdq does not work properly when the
device enters lower power states. Idling uart1 and 2 is enough
to show up that problem, if
On 05/02/2019 14:45, Roger Quadros wrote:
Hi,
The AM654 SoC supports 2 DWC3 USB controller instances. The
AM654 base board supports the 2nd (USB1) instance in high-speed.
This series enables support for USB1 instance on the AM654-base-board.
The series depends on [1] and [2]. Both are in the -
On 12/02/2019 14:22, Vignesh R wrote:
TI AM654 SoC has two ADC instances in the MCU domain. Add DT nodes for
the same.
Signed-off-by: Vignesh R
---
Tero,
Could you also pick up DT bindings here:
https://patchwork.kernel.org/patch/10751429/
All the Acks are in place.
Queued for 5.1, includin
On 05/02/2019 14:25, Roger Quadros wrote:
Tero,
On 11/01/19 11:44, Roger Quadros wrote:
The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram
node so drivers can use it via genpool API.
Following areas are marked reserved:
- Lower 128KB for ATF
- 64KB@0xf for SYSFW
- Upper 1MB for cache
On 24/01/2019 14:40, Nishanth Menon wrote:
On 13:43-20190124, Faiz Abbas wrote:
Hi,
On 17/01/19 3:14 PM, Faiz Abbas wrote:
The following patches add eMMC support on TI's AM65x-evm.
v3:
1. Fixed patch titles to only include eMMC
2. Added dma-coherent to the sdhci0 node.
v2:
1. The SD ca
On 24/01/2019 14:40, Nishanth Menon wrote:
On 13:43-20190124, Faiz Abbas wrote:
Hi,
On 17/01/19 3:14 PM, Faiz Abbas wrote:
The following patches add eMMC support on TI's AM65x-evm.
v3:
1. Fixed patch titles to only include eMMC
2. Added dma-coherent to the sdhci0 node.
v2:
1. The SD ca
On 18/01/2019 21:45, Tony Lindgren wrote:
* Andreas Kemnade [190118 19:39]:
Hi,
On Fri, 18 Jan 2019 10:36:30 -0800
Tony Lindgren wrote:
[...]
til the next workaround.
That flags also causes the iclk being enabled/disabled
manually.
Yes but SWSUP_IDLE for the interface clock to me curren
On 02/01/2019 14:26, Lokesh Vutla wrote:
Hi Peter,
On 02/01/19 5:19 PM, Peter Ujfalusi wrote:
On 27/12/2018 8.13, Lokesh Vutla wrote:
Texas Instruments' K3 generation SoCs has an IP Interrupt Aggregator
which is an interrupt controller that does the following:
- Converts events to interrupt
On 12/01/2019 00:49, Stephen Boyd wrote:
Quoting Tero Kristo (2019-01-03 23:28:58)
On 04/01/2019 01:39, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-12-31 00:30:21)
On Mon, 31 Dec 2018 09:23:01 +0200
Tero Kristo wrote:
On 28/12/2018 22:02, Tony Lindgren wrote:
* Andreas Kemnade
On 04/01/2019 01:39, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-12-31 00:30:21)
On Mon, 31 Dec 2018 09:23:01 +0200
Tero Kristo wrote:
On 28/12/2018 22:02, Tony Lindgren wrote:
* Andreas Kemnade [181227 20:13]:
Hi,
On Tue, 4 Dec 2018 08:45:57 -0800
Tony Lindgren wrote
On 28/12/2018 22:02, Tony Lindgren wrote:
* Andreas Kemnade [181227 20:13]:
Hi,
On Tue, 4 Dec 2018 08:45:57 -0800
Tony Lindgren wrote:
* Andreas Kemnade [181204 06:17]:
On Mon, 3 Dec 2018 07:39:10 -0800
Tony Lindgren wrote:
The consumer device stays active just fine with PM runtime
call
On 13/12/2018 17:03, Vignesh R wrote:
On 13-Dec-18 8:29 PM, Tero Kristo wrote:
On 09/12/2018 12:22, Vignesh R wrote:
There are 3 instances of McSPI in MCU domain and 4 instances in Main
domain.
Add DT nodes for all McSPI instances present on AM654 SoC.
Signed-off-by: Vignesh R
---
arch
On 09/12/2018 12:22, Vignesh R wrote:
There are 3 instances of McSPI in MCU domain and 4 instances in Main domain.
Add DT nodes for all McSPI instances present on AM654 SoC.
Signed-off-by: Vignesh R
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 52
arch/arm64/boot/d
On 30/11/2018 09:57, Stephen Boyd wrote:
Quoting Tero Kristo (2018-11-29 23:37:35)
On 30/11/2018 02:26, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-10 12:31:12)
On the gta04 with a dm3730 omap_hdq does not work properly when the
device enters lower power states. Idling uart1 and 2 is
On 30/11/2018 09:57, Stephen Boyd wrote:
Quoting Tero Kristo (2018-11-29 23:35:35)
On 30/11/2018 09:20, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-29 22:15:34)
Hi Stephen,
On Thu, 29 Nov 2018 16:25:05 -0800
Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-10 12:31:14)
Code
On 30/11/2018 02:26, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-10 12:31:12)
On the gta04 with a dm3730 omap_hdq does not work properly when the
device enters lower power states. Idling uart1 and 2 is enough
to show up that problem, if there are no other things enabled.
Further researc
On 30/11/2018 09:20, Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-29 22:15:34)
Hi Stephen,
On Thu, 29 Nov 2018 16:25:05 -0800
Stephen Boyd wrote:
Quoting Andreas Kemnade (2018-11-10 12:31:14)
Code might use autoidle api with clocks not being omap2 clocks,
so check if clock type is n
On 20/11/2018 12:44, Vignesh R wrote:
On 20/11/18 4:07 PM, Tero Kristo wrote:
On 20/11/2018 12:09, Vignesh R wrote:
On 19/11/18 12:49 PM, Tero Kristo wrote:
On 17/11/2018 18:05, Nishanth Menon wrote:
On 11:31-20181113, Vignesh R wrote:
The dt-bindings header for TI K3 AM6 SoCs define a set
On 23/11/2018 10:20, Arnd Bergmann wrote:
On Thu, Nov 22, 2018 at 12:41 PM Roger Quadros wrote:
+
+ if (IS_ERR_OR_NULL(rproc))
+ return ERR_PTR(-EINVAL);
Any usage of IS_ERR_OR_NULL() tends to be an indication of a badly
designed API. Please change this to allow only on
On 20/11/2018 12:09, Vignesh R wrote:
On 19/11/18 12:49 PM, Tero Kristo wrote:
On 17/11/2018 18:05, Nishanth Menon wrote:
On 11:31-20181113, Vignesh R wrote:
The dt-bindings header for TI K3 AM6 SoCs define a set of macros for
[...]
Thanks for reducing the combinations down to the
On 17/11/2018 18:05, Nishanth Menon wrote:
On 11:31-20181113, Vignesh R wrote:
The dt-bindings header for TI K3 AM6 SoCs define a set of macros for
defining pinmux configs in human readable form, instead of raw-coded
hex values.
Signed-off-by: Vignesh R
---
MAINTAINERS |
On 07/11/2018 23:00, Nishanth Menon wrote:
On 10:10-20181005, Vutla, Lokesh wrote:
On Thursday 27 September 2018 10:31 AM, Vignesh R wrote:
cbass_wakeup interconnect which is the parent of wakeup_uart node
defines address-cells=1 and size-cells=1, therefore fix up reg property
of wakeup_uart
On 08/11/2018 13:08, Andreas Kemnade wrote:
Hi,
On Thu, 8 Nov 2018 12:26:08 +0200
Tero Kristo wrote:
On 04/10/2018 23:38, Andreas Kemnade wrote:
Deny autoidle for hwmods with the OCPIF_SWSUP_IDLE flag,
that makes hwmods working properly which cannot handle
autoidle properly in lower power
On 04/10/2018 23:38, Andreas Kemnade wrote:
We have the scenario that first autoidle is disabled for all clocks,
then it is disabled for selected ones and then enabled for all. So
we should have some counting here, also according to the
comment in _setup_iclk_autoidle()
Signed-off-by: Andreas K
On 04/10/2018 23:38, Andreas Kemnade wrote:
Deny autoidle for hwmods with the OCPIF_SWSUP_IDLE flag,
that makes hwmods working properly which cannot handle
autoidle properly in lower power states.
Affected is e. g. the omap_hdq.
Since an ick might have mulitple users, autoidle is disabled
when an
On 04/10/18 18:07, Tony Lindgren wrote:
* Tero Kristo [181004 14:47]:
On 04/10/18 17:25, Tony Lindgren wrote:
It seems we should just provide a generic interface for
clk_allow_autoidle() and clk_deny_autoidle()? Otherwise we'll
be forever stuck with pdata callbacks it seems.
The TI
On 04/10/18 17:25, Tony Lindgren wrote:
* Andreas Kemnade [181004 05:56]:
On the gta04 with a dm3730 omap_hdq does not work properly when the
device enters lower power states. Idling uart1 and 2 is enough
to show up that problem, if there are no other things enabled.
Further research reveals th
On 04/10/18 08:51, Andreas Kemnade wrote:
We have the scenario that first autoidle is disabled for all clocks,
then it is disabled for selected ones and then enabled for all. So
we should have some counting here, also according to the
comment in _setup_iclk_autoidle()
Signed-off-by: Andreas Kem
On 28/09/18 18:57, Stephen Boyd wrote:
Quoting Tero Kristo (2018-09-20 00:11:08)
On 31/08/18 00:46, Stephen Boyd wrote:
Quoting Johan Hovold (2018-08-22 02:03:19)
Fix child-node lookup which by using the wrong OF helper was searching
the whole tree depth-first, something which could end up
On 31/08/18 00:46, Stephen Boyd wrote:
Quoting Johan Hovold (2018-08-22 02:03:19)
Fix child-node lookup which by using the wrong OF helper was searching
the whole tree depth-first, something which could end up matching an
unrelated node.
Also fix the related node-reference leaks.
Fixes: 5b385a
On 05/09/18 16:40, Nishanth Menon wrote:
On 11:17-20180905, Kishon Vijay Abraham I wrote:
AM65 has two PCIe controllers and each PCIe controller has '2' address
spaces one within the 4GB address space of the SoC and the other above
the 4GB address space of the SoC (cbass_main) in addition to the
On 05/09/18 23:33, Tony Lindgren wrote:
* Nishanth Menon [180905 16:24]:
Nishanth Menon (3):
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: k3-am6: Add Device Management Security Controller
support
All look
I fixed up most of these last year, but this
one managed to sneak in since then.
clk-next should be fine.
The patch looks fine to me also, just had to test this out with my
latest development branch as it conflicts with that one a bit.
Acked-by: Tero Kristo
--
Texas Instruments Finland Oy
On 10/07/18 08:56, Tony Lindgren wrote:
* Keerthy [180621 01:18]:
Deep enough power saving mode can result into losing context of the clock
registers also, and they need to be restored once coming back from the power
saving mode. Hence add functions to save/restore clock context.
Patches 1 to
On 19/06/18 07:28, Keerthy wrote:
The default restore context function enables or disables
the clock based on the enable_count. This is done in cases
where the clock context is lost and based on the enable_count
the clock either needs to be enabled/disabled. This particularly
helps restore the st
On 31/05/18 13:14, Faiz Abbas wrote:
Hi,
On Thursday 31 May 2018 09:33 AM, Rob Herring wrote:
On Wed, May 30, 2018 at 07:41:30PM +0530, Faiz Abbas wrote:
Add clkctrl data for the m_can clocks and register it within the
...
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings
On 30/05/18 18:54, Tony Lindgren wrote:
* Tero Kristo [180530 15:44]:
On 30/05/18 18:28, Tony Lindgren wrote:
* Tero Kristo [180530 15:18]:
For the OCP if part, I think that is still needed until we switch over to
full sysc driver. clkctrl_offs you probably also need because that is used
On 30/05/18 18:28, Tony Lindgren wrote:
* Tero Kristo [180530 15:18]:
For the OCP if part, I think that is still needed until we switch over to
full sysc driver. clkctrl_offs you probably also need because that is used
for mapping the omap_hwmod against a specific clkctrl clock. Those can be
On 30/05/18 17:50, Tony Lindgren wrote:
* Faiz Abbas [180530 14:12]:
From: Lokesh Vutla
Add MCAN hwmod data and register it for dra762 silicons.
Signed-off-by: Lokesh Vutla
Signed-off-by: Faiz Abbas
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 32 +++
1 file chang
et if usb_otg_ss instances 3 and 4 are affected by this
issue or not so don't add this flag for those instances.
Cc: Tero Kristo
Signed-off-by: Roger Quadros
Signed-off-by: Tony Lindgren
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
This fails to build for me on arm32 wi
On 19/03/18 05:44, Dan Rue wrote:
On Fri, Mar 16, 2018 at 04:23:25PM +0100, Greg Kroah-Hartman wrote:
4.14-stable review patch. If anyone has any objections, please let me know.
--
From: Tero Kristo
[ Upstream commit 729e13bf58e643b9accd2a14c55b555958702fb0 ]
In case the
e.
Remove the indentation to fix Smatch warning:
drivers/crypto/omap-sham.c:1761 omap_sham_done_task() warn: inconsistent
indenting
Signed-off-by: Krzysztof Kozlowski
Acked-by: Tero Kristo
---
drivers/crypto/omap-sham.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
re_request() warn: variable
dereferenced before check 'req' (see line 805)
Signed-off-by: Krzysztof Kozlowski
Acked-by: Tero Kristo
---
drivers/crypto/omap-sham.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.
messages during boot, basically one extra for each device that exists on
the SoC; on K2G this is approx 80.
Signed-off-by: Tero Kristo
---
drivers/clk/keystone/sci-clk.c | 380 ++---
1 file changed, 90 insertions(+), 290 deletions(-)
diff --git a/drivers/clk
On 16/01/18 03:11, Tony Lindgren wrote:
We can support the RSTCTRL reset registers on many TI SoCs with
reset-simple.
Cc: Dave Gerlach
Cc: Mark Rutland
Cc: Nishant Menon
Cc: Philipp Zabel
Cc: Rob Herring
Cc: Suman Anna
Cc: Tero Kristo
Signed-off-by: Tony Lindgren
---
That's all
On 14/11/17 21:44, Tony Lindgren wrote:
* Tero Kristo [171114 19:34]:
I guess you could just use rx51_secure_dispatcher and ditch the
save_secure_ram_context call completely (and most of the other related
code)? That one would handle the cache also in a clean manner.
Something like
On 14/11/17 19:37, Tony Lindgren wrote:
* Joonsoo Kim [171114 06:34]:
On Fri, Nov 10, 2017 at 07:36:20AM -0800, Tony Lindgren wrote:
* Joonsoo Kim [171110 06:34]:
On Thu, Nov 09, 2017 at 07:26:10PM -0800, Tony Lindgren wrote:
+#define OMAP34XX_SRAM_PHYS 0x4020
+#define OMAP34XX_SRAM
Thank you.
Thanks!
Rafael
The latest patches (#1 v3 and #2 v4) seem to work fine in my sanity
tests also.
Tested-by: Tero Kristo
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
PM / QoS: Fix device resume latency PM QoS")
Signed-off-by: Tero Kristo
Cc: Rafael J. Wysocki
Applied.
And pushed to Linus.
I'm afraid it is not sufficient.
Commit 0cc2b4e5a020fc7f ("PM / QoS: Fix device resume latency PM QoS")
introduced two issues on Renesas platform
On 31/10/17 10:40, Rafael J. Wysocki wrote:
On Tue, Oct 31, 2017 at 8:13 AM, Tero Kristo wrote:
On 31/10/17 01:27, Rafael J. Wysocki wrote:
On Monday, October 30, 2017 11:19:08 AM CET Rafael J. Wysocki wrote:
On Mon, Oct 30, 2017 at 8:10 AM, Tero Kristo wrote:
The recent change to the
On 31/10/17 01:27, Rafael J. Wysocki wrote:
On Monday, October 30, 2017 11:19:08 AM CET Rafael J. Wysocki wrote:
On Mon, Oct 30, 2017 at 8:10 AM, Tero Kristo wrote:
The recent change to the PM QoS framework to introduce a proper
no constraint value overlooked to handle the devices which don&#
econd level issues like
probe failures and increased power consumption among other things.
Fix this by adding a proper return value for devices that don't
implement PM QoS implicitly.
Fixes: 0cc2b4e5a020 ("PM / QoS: Fix device resume latency PM QoS")
Signed-off-by: Tero Kristo
C
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
On 09/10/17 17:20, Mark Brown wrote:
On Wed, Sep 27, 2017 at 05:55:40PM +0530, Keerthy wrote:
The reset value of the EN_PIN_CTRL bit fields of LDOs and BUCKs
need no
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
On 06/09/17 13:36, Keerthy wrote:
Reset the mcasp3_ahclkx_mux to abe_24m_fclk. This is needed
in case of kexec where the reset values might be wiped off.
Signed-off-
Looks fine.
Acked-by: Tero Kristo
---
drivers/clk/ti/adpll.c | 2 +-
drivers/clk/ti/apll.c | 2 +-
drivers/clk/ti/fapll.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/ti/adpll.c b/drivers/clk/ti/adpll.c
index 255cafb..d5c6db4 100644
--- a/drivers/clk
f (postfix && strlen(postfix) > 1) {
if (strlen(postfix) > ADPLL_MAX_CON_ID)
dev_warn(d->dev, "clock %s con_id lookup may fail\n",
name);
Looks fine to me.
Acked-by: Tero Kristo
("clk: keystone: Add sci-clk driver support")
Signed-off-by: Arnd Bergmann
Looks ok to me. Tero?
Yeah, looks okay to me also, been traveling so sorry about the latency.
Acked-by: Tero Kristo
On 13/06/17 23:32, Santosh Shilimkar wrote:
On 6/13/2017 1:16 PM, Dave Gerlach wrote:
Santosh,
On 05/31/2017 11:28 AM, Rob Herring wrote:
On Mon, May 22, 2017 at 01:37:37PM -0500, Dave Gerlach wrote:
[...]
[1] https://www.spinics.net/lists/arm-kernel/msg577079.html
.../devicetree/bindings
On 13/06/17 17:24, Sebastian Reichel wrote:
Hi,
On Tue, Jun 13, 2017 at 04:49:18PM +0300, Tero Kristo wrote:
On 13/06/17 12:28, Sebastian Reichel wrote:
This adds crypto support for OMAP4, which was missing for some reason.
This fixes error about missing hwmod on Droid 4. IP-Cores for AES and
sham accelerator also. The dts data
should be applied first if you want to avoid any issues with hwmod core
complaining about missing DT data, so the sequencing of this series and
mine need to be done carefully.
The patches themselves in this series look fine now, so:
Acked-by: Tero Kristo
On 10/06/17 02:12, Sebastian Reichel wrote:
This fixes the following error during kernel boot:
platform 4b501000.aes: Cannot lookup hwmod 'aes'
Unfortunately the AES module is only documented partly
in the OMAP4430 TRM. I found an old patch from Joel,
which I took over and updated for currently
On 10/06/17 02:12, Sebastian Reichel wrote:
This fixes the following error during kernel boot:
platform 480a5000.des: Cannot lookup hwmod 'des'
Unfortunately the DES module is only documented partly
in the OMAP4430 TRM. I found an old patch from Joel,
which I took over and updated for currently
On 10/06/17 02:12, Sebastian Reichel wrote:
Add missing functional clock for DES3DES IP core. This is
documented in the TRM as CM_L4SEC_DES3DES_CLKCTRL.
Signed-off-by: Sebastian Reichel
---
arch/arm/boot/dts/omap44xx-clocks.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arc
On 03/05/17 21:52, Russell King - ARM Linux wrote:
On Tue, Apr 18, 2017 at 10:42:49AM +0530, Keerthy wrote:
From: Russ Dill
The clock/dpll registers are in the WKUP power domain. Under both RTC-only
suspend and hibernation, these registers are lost. Hence save/restore
them accordingly.
This
On 04/05/17 10:51, Peter De Schrijver wrote:
On Tue, Apr 18, 2017 at 10:42:49AM +0530, Keerthy wrote:
From: Russ Dill
The clock/dpll registers are in the WKUP power domain. Under both RTC-only
suspend and hibernation, these registers are lost. Hence save/restore
them accordingly.
This won't
the address from div->reg.ptr
instead.
Actually, I believe the code you are fixing works before this commit:
commit 6c0afb503937a12a8d20a805fcf263e31afa9871
Author: Tero Kristo
Date: Thu Feb 9 11:24:37 2017 +0200
clk: ti: convert to use proper register definition for all accesses
..
f-by: Arnd Bergmann
This one is clear... I think I should start running the single SoC build
testing script again before posting stuff, this is an area where I seem
to fail repeatedly... sorry about that.
Acked-by: Tero Kristo
---
drivers/clk/ti/clk.c | 12 ++--
1 file change
On 20/04/17 18:06, Arnd Bergmann wrote:
On Thu, Apr 20, 2017 at 4:57 PM, Tero Kristo wrote:
On 20/04/17 00:43, Arnd Bergmann wrote:
When none of the OMAP4-generation SoCs are enabled, we run into a link
error for am43xx/am43xx:
drivers/clk/ti/dpll.o: In function `of_ti_am3_dpll_x2_setup
e is masked in the testing I did
locally so far.
Fixes: 0565fb168d63 ("clk: ti: dpll: move omap3 DPLL functionality to clock
driver")
However, I believe the fixes tag should point to this one in linux-next:
commit 473adbf4e02857a6b78dfb3d9fcf752638bbadb9
Author: Tero Kristo
Dat
On 18/04/17 08:12, Keerthy wrote:
From: Russ Dill
The clock/dpll registers are in the WKUP power domain. Under both RTC-only
suspend and hibernation, these registers are lost. Hence save/restore
them accordingly.
Signed-off-by: Russ Dill
Signed-off-by: Keerthy
I think the core support shou
On 12/04/17 20:24, Eduardo Valentin wrote:
On Wed, Apr 12, 2017 at 10:41:00PM +0530, Keerthy wrote:
On Wednesday 12 April 2017 10:38 PM, Grygorii Strashko wrote:
On 04/12/2017 11:44 AM, Keerthy wrote:
On Wednesday 12 April 2017 10:01 PM, Grygorii Strashko wrote:
On 04/12/2017 10:44 AM
On 02/02/17 00:12, Andrew Morton wrote:
On Wed, 1 Feb 2017 19:35:40 +0530 Lokesh Vutla wrote:
commit 4a9d4b024a31 ("switch fput to task_work_add") implements a
schedule_work() for completing fput(), but did not guarantee calling
__fput() after unpacking initramfs. Because of this, there is a
p
. Let me know if this needs to be rebased.
- Keerthy
Signed-off-by: Keerthy
Reported-by: Richard Woodruff
Acked-by: Tero Kristo
Stephen / Michael, can you pick this up?
-Tero
---
drivers/clk/ti/divider.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion
On 17/01/17 13:14, Lokesh Vutla wrote:
commit 4a9d4b024a31 ("switch fput to task_work_add") implements a
schedule_work() for completing fput(), but did not guarantee calling
__fput() after unpacking initramfs. Because of this, there is a
possibility that during boot a driver can see ETXTBSY when
On 17/01/17 00:12, Dave Gerlach wrote:
On 01/13/2017 08:40 PM, Rob Herring wrote:
On Fri, Jan 13, 2017 at 2:28 PM, Dave Gerlach wrote:
On 01/13/2017 01:25 PM, Rob Herring wrote:
On Thu, Jan 12, 2017 at 9:27 AM, Dave Gerlach wrote:
Rob,
On 01/11/2017 03:34 PM, Rob Herring wrote:
On Mon
On 26/10/16 22:56, Santosh Shilimkar wrote:
On 10/25/2016 10:34 AM, Tero Kristo wrote:
On 19/10/16 02:08, Nishanth Menon wrote:
Version 4 of the series is basically a rebase to v4.9-rc1, no functional
changes.
Hi,
Any final comments on this series, or shall I send a pull-req forward?
Very
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