Qualcomm crypto engine does not handle the following scenarios and
will issue an abort. In such cases, pass on the transformation to
a fallback algorithm.
- DES3 algorithms with all three keys same.
- AES192 algorithms.
- 0 length messages.
Signed-off-by: Thara Gopinath
---
v1->
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto engine.
Signed-off-by: Thara Gopinath
---
v2->v3:
- Made qce_be32_to_cpu_array truly be32 to cpu endian by using
be32_to_cpup
instead of cpu_to_be32p. Also remove the (u32 *) typcast
Remove various redundant checks in qce_auth_cfg. Also allow qce_auth_cfg
to take auth_size as a parameter which is a required setting for ccm(aes)
algorithms
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 21 +
1 file changed, 9 insertions(+), 12 deletions
that in this patch, the enabled algorithms always choose
RESULTS_DUMP to be enabled. But later with the introduction of ccm
algorithms, this changes.
Reviewed-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions
-by: Thara Gopinath
---
v1->v2:
- Removed spurious totallen from qce_aead_async_req_handle since
it was unused as pointed out by Hubert.
- Updated qce_dma_prep_sgs to use #nents returned by dma_map_sg rather
than
using precomputed #nents.
drivers/crypto/Kcon
rf4309 is the specification that uses aes ccm algorithms with IPsec
security packets. Add a submode to identify rfc4309 ccm(aes) algorithm
in the crypto driver.
Reviewed-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
v1->v2:
- Moved up the QCE_ENCRYPT AND QCE_DECRYPT
infrastructure needed to enable and run the AEAD transformations on
Qualcomm CE. Patch 7 adds support to queue fallback algorithms in case of
unsupported special inputs.
This patch series has been tested with in kernel crypto testing module
tcrypt.ko with fuzz tests enabled as well.
Thara Gopinath (7
MAC_FAILED gets set in the status register if authenthication fails
for ccm algorithms(during decryption). Add support to catch and flag
this error.
Reviewed-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
v1->v2:
- Split the error checking for -ENXIO and -EBADMSG into if-e
On 4/13/21 7:09 PM, Bjorn Andersson wrote:
On Tue 13 Apr 17:44 CDT 2021, Thara Gopinath wrote:
[..]
Yes, given that you just typecast things as you do it should just work
to move the typecast to the qce_cpu_to_be32p_array().
But as I said, this would indicate that what is cpu_to_be32
Remove various redundant checks in qce_auth_cfg. Also allow qce_auth_cfg
to take auth_size as a parameter which is a required setting for ccm(aes)
algorithms
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 21 +
1 file changed, 9 insertions(+), 12 deletions
Qualcomm crypto engine does not handle the following scenarios and
will issue an abort. In such cases, pass on the transformation to
a fallback algorithm.
- DES3 algorithms with all three keys same.
- AES192 algorithms.
- 0 length messages.
Signed-off-by: Thara Gopinath
---
v1->
-by: Thara Gopinath
---
v1->v2:
- Removed spurious totallen from qce_aead_async_req_handle since
it was unused as pointed out by Hubert.
- Updated qce_dma_prep_sgs to use #nents returned by dma_map_sg rather
than
using precomputed #nents.
drivers/crypto/Kcon
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto engine.
Signed-off-by: Thara Gopinath
---
v1->v2:
- Minor fixes like removing not needed initializing of variables
and using bool values in lieu of 0 and 1 as pointed out by Bj
rf4309 is the specification that uses aes ccm algorithms with IPsec
security packets. Add a submode to identify rfc4309 ccm(aes) algorithm
in the crypto driver.
Signed-off-by: Thara Gopinath
---
v1->v2:
- Moved up the QCE_ENCRYPT AND QCE_DECRYPT bit positions so that
addit
that in this patch, the enabled algorithms always choose
RESULTS_DUMP to be enabled. But later with the introduction of ccm
algorithms, this changes.
Reviewed-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions
MAC_FAILED gets set in the status register if authenthication fails
for ccm algorithms(during decryption). Add support to catch and flag
this error.
Signed-off-by: Thara Gopinath
---
v1->v2:
- Split the error checking for -ENXIO and -EBADMSG into if-else clause
infrastructure needed to enable and run the AEAD transformations on
Qualcomm CE. Patch 7 adds support to queue fallback algorithms in case of
unsupported special inputs.
This patch series has been tested with in kernel crypto testing module
tcrypt.ko with fuzz tests enabled as well.
Thara Gopinath (7
On 4/13/21 6:33 PM, Bjorn Andersson wrote:
On Tue 13 Apr 17:27 CDT 2021, Thara Gopinath wrote:
On 4/5/21 6:18 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto engine
On 4/13/21 6:20 PM, Bjorn Andersson wrote:
On Tue 13 Apr 16:31 CDT 2021, Thara Gopinath wrote:
Hi Bjorn,
On 4/5/21 6:18 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto
On 4/5/21 6:18 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto engine.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 155
Hi Bjorn,
On 4/5/21 6:18 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto engine.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 155
On 4/5/21 6:32 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
rf4309 is the specification that uses aes ccm algorithms with IPsec
security packets. Add a submode to identify rfc4309 ccm(aes) algorithm
in the crypto driver.
Signed-off-by: Thara Gopinath
Hi Bjorn,
Thanks for the reviews.
I realized that I had these replies in my draft for a while and forgot
to send them!
On 4/5/21 1:36 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
MAC_FAILED gets set in the status register if authenthication fails
for ccm
On 3/19/21 6:08 PM, Konrad Dybcio wrote:
MDM9607 TSENS IP is very similar to the one of MSM8916, with
minor adjustments to various tuning values.
Signed-off-by: Konrad Dybcio
Acked-by: Thara Gopinath
Warm Regards
Thara
---
v4: Remove unneeded braces and newline
drivers/thermal/qcom
On 3/19/21 2:15 PM, Ansuel Smith wrote:
Device based on tsens VER_0 contains a hardware bug that results in some
problem with sensor enablement. Sensor id 6-11 can't be enabled
selectively and all of them must be enabled in one step.
Signed-off-by: Ansuel Smith
Acked-by: Thara Gopinath
Add myself as the maintainer for Qualcomm tsens drivers so that I
can help Daniel by taking care of/reviewing changes to these drivers.
Signed-off-by: Thara Gopinath
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aa84121c5611..ab66ab9a628e
On 3/19/21 9:28 AM, Ansuel Smith wrote:
On Fri, Mar 19, 2021 at 09:11:38AM -0400, Thara Gopinath wrote:
On 3/18/21 8:52 PM, Ansuel Smith wrote:
VER_0 is used to describe device based on tsens version before v0.1.
These device are devices based on msm8960 for example apq8064 or
ipq806x
On 3/18/21 8:52 PM, Ansuel Smith wrote:
Drop unused define for msm8960 replaced by generic api and reg_field.
Signed-off-by: Ansuel Smith
Thanks for the clean up!
Reviewed-by: Thara Gopinath
Warm Regards
Thara
---
drivers/thermal/qcom/tsens-8960.c | 24 +---
1
On 3/18/21 8:52 PM, Ansuel Smith wrote:
Rework calibrate function to use common function. Derive the offset from
a missing hardcoded slope table and the data from the nvmem calib
efuses.
Drop custom get_temp function and use generic api.
Signed-off-by: Ansuel Smith
Acked-by: Thara Gopinath
Hi!
On 3/18/21 8:52 PM, Ansuel Smith wrote:
Device based on tsens VER_0 contains a hardware bug that results in some
problem with sensor enablement. Sensor id 6-11 can't be enabled
selectively and all of them must be enabled in one step.
Thanks for rewording!
Signed-off-by: Ansuel Smith
and fix them. Once that is done, you can add
Reviewed-by: Thara Gopinath
Warm Regards
Thara
Signed-off-by: Ansuel Smith
---
drivers/thermal/qcom/tsens.c | 141 ---
drivers/thermal/qcom/tsens.h | 4 +-
2 files changed, 116 insertions(+), 29 deletions(-)
diff
add it to commit description as
well.I will also consider changing the subject header to something more
generic like
"drivers: thermal: tsens: Replace custom 8960 apis with generic apis"
or anything better.
Otherwise,
Acked-by: Thara Gopinath
Warm Regards
Thara
Signed-off-
On 2/17/21 2:40 PM, Ansuel Smith wrote:
It's present a hardware bug in tsens VER_0 where if sensors upper to id
6 are enabled selectively, underfined results are expected. Fix this by
enabling all the remaining sensor in one step.
It took me a while to understand this. It is most likely
SLP_CLK_ENA_8660 and SLP_CLK_ENA. Everything else can
be removed and the s/w can use priv->rf[_field_] for access.
Otherwise for this patch
Acked-by: Thara Gopinath
Warm Regards
Thara
Signed-off-by: Ansuel Smith
---
drivers/thermal/qcom/tsens-8960.c | 80 ++-
1 f
On 2/17/21 2:40 PM, Ansuel Smith wrote:
Use init_common and drop custom init for msm8960.
Signed-off-by: Ansuel Smith
Reviewed-by: Thara Gopinath
Warm Regards
Thara
--- > drivers/thermal/qcom/tsens-8960.c | 52 +--
1 file changed, 1 insertion(+),
-by: Thara Gopinath
Warm Regards
Thara
---
drivers/thermal/qcom/tsens.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
index f9126909892b..842f518fdf84 100644
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers
Hi Ansuel!
Apologies for delay in the review..
This particular patch throws checkpatch check warnings. Please
run checkpatch.pl --strict and fix them. Rest of the comments below
On 2/17/21 2:40 PM, Ansuel Smith wrote:
VER_0 is used to describe device based on tsens version before v0.1.
These
On 2/17/21 2:40 PM, Ansuel Smith wrote:
Add support for tsens present in ipq806x SoCs based on generic msm8960
tsens driver.
Signed-off-by: Ansuel Smith
Reviewed-by: Thara Gopinath
Warm Regards
Thara
---
drivers/thermal/qcom/tsens.c | 3 +++
1 file changed, 3 insertions(+)
diff
On 2/9/21 2:25 PM, Konrad Dybcio wrote:
MDM9607 TSENS IP is very similar to the one of MSM8916, with
minor adjustments to various tuning values.
Signed-off-by: Konrad Dybcio
Acked-by: Rob Herring
---
Changes since v2:
- Address Bjorn's comments (remove redundant variable and kfree)
On 2/25/21 4:31 PM, Konrad Dybcio wrote:
The sensor *is* in fact used and does report temperature.
I can't find any info that says otherwise. So,
Acked-by: Thara Gopinath
Warm Regards
Thara
Signed-off-by: Konrad Dybcio
---
drivers/thermal/qcom/tsens-v1.c | 4 ++--
1 file changed
o it makes more sense to use
the IP version for the compatible string, rather than using the soc
name as the compatible string.
[1].
https://lore.kernel.org/linux-arm-msm/20201119155233.3974286-7-thara.gopin...@linaro.org/
Cc: Thara Gopinath
Cc: Bjorn Andersson
Cc: Rob Herring
Cc: Andy Gross
Cc:
On 3/12/21 8:01 AM, Herbert Xu wrote:
On Thu, Feb 25, 2021 at 01:27:13PM -0500, Thara Gopinath wrote:
+static int
+qce_aead_async_req_handle(struct crypto_async_request *async_req)
+{
+ struct aead_request *req = aead_request_cast(async_req);
+ struct qce_aead_reqctx *rctx
On 3/12/21 8:02 AM, Herbert Xu wrote:
On Thu, Mar 04, 2021 at 01:41:15PM -0500, Thara Gopinath wrote:
Yes it did. The last patch adds fallback for unsupported cases and
this will make it pass the fuzz tests.
Please include this information in the next round.
I will. Thanks!
Thanks
On 3/10/21 7:19 AM, Daniel Lezcano wrote:
Hi Ansuel,
On 17/02/2021 20:40, Ansuel Smith wrote:
This patchset convert msm8960 to reg_filed, use int_common instead
of a custom function and fix wrong tsens get_temp function for msm8960.
Ipq8064 SoCs tsens driver is based on 8960 tsens driver.
On Thu, 4 Mar 2021 at 00:30, Herbert Xu wrote:
>
> On Thu, Feb 25, 2021 at 01:27:09PM -0500, Thara Gopinath wrote:
> > Enable support for AEAD algorithms in Qualcomm CE driver. The first three
> > patches in this series are cleanups and add a few missing pieces required
Qualcomm crypto engine does not handle the following scenarios and
will issue an abort. In such cases, pass on the transformation to
a fallback algorithm.
- DES3 algorithms with all three keys same.
- AES192 algorithms.
- 0 length messages.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto engine.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 155 +++-
1 file changed, 153 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/qce/common.c b
Remove various redundant checks in qce_auth_cfg. Also allow qce_auth_cfg
to take auth_size as a parameter which is a required setting for ccm(aes)
algorithms
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 21 +
1 file changed, 9 insertions(+), 12 deletions
-by: Thara Gopinath
---
drivers/crypto/Kconfig | 15 +
drivers/crypto/qce/Makefile | 1 +
drivers/crypto/qce/aead.c | 779
drivers/crypto/qce/aead.h | 53 +++
drivers/crypto/qce/common.h | 2 +
drivers/crypto/qce/core.c | 4 +
6 files changed, 854
that in this patch, the enabled algorithms always choose
RESULTS_DUMP to be enabled. But later with the introduction of ccm
algorithms, this changes.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/qce
MAC_FAILED gets set in the status register if authenthication fails
for ccm algorithms(during decryption). Add support to catch and flag
this error.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git
rf4309 is the specification that uses aes ccm algorithms with IPsec
security packets. Add a submode to identify rfc4309 ccm(aes) algorithm
in the crypto driver.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
infrastructure needed to enable and run the AEAD transformations on
Qualcomm CE. Patch 7 adds support to queue fallback algorithms in case of
unsupported special inputs.
This series is dependant on https://lkml.org/lkml/2021/2/11/1052.
Thara Gopinath (7):
crypto: qce: common: Add MAC failed error
On 2/11/21 3:01 PM, Thara Gopinath wrote:
This patch series is a result of running kernel crypto fuzz tests (by
enabling CONFIG_CRYPTO_MANAGER_EXTRA_TESTS) on the transformations
currently supported via the Qualcomm crypto engine on sdm845. The first
nine patches are fixes for various
On 2/18/21 3:48 AM, Viresh Kumar wrote:
On 17-02-21, 10:32, Thara Gopinath wrote:
First of all, I am still unable to find this setting in the sysfs space.
The driver needs to call cpufreq_enable_boost_support() for that.
Ok. that makes sense.
Irrespective the ideal behavior here
845 that I had reported. So,
Tested-by: Thara Gopinath
drivers/thermal/cpufreq_cooling.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/cpufreq_cooling.c
b/drivers/thermal/cpufreq_cooling.c
index f5af2571f9b7..10af3341e5ea 100644
--- a/drive
On 2/17/21 12:50 AM, Viresh Kumar wrote:
Hi Thara,
On 16-02-21, 19:00, Thara Gopinath wrote:
This is a fix for a regression observed on db845 platforms with 5.7-rc11
kernel. On these platforms running stress tests with 5.11-rc7 kernel
causes big cpus to overheat and ultimately shutdown
of the cpu in cpufreq driver.
cpufreq_frequency_table_cpuinfo that calculates the maximum frequency of a
cpu for cpufreq driver already has such a check in place.
Signed-off-by: Thara Gopinath
---
include/linux/cpufreq.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include
parameters in qce_start.
Reviewed-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 17 +++--
drivers/crypto/qce/common.h | 3 +--
drivers/crypto/qce/sha.c | 2 +-
drivers/crypto/qce/skcipher.c | 2 +-
4 files changed, 10 insertions(+), 14
src_table is unused and hence remove it from struct qce_cipher_reqctx
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/cipher.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/crypto/qce/cipher.h b/drivers/crypto/qce/cipher.h
index cffa9fc628ff..850f257d00f3 100644
--- a/drivers
ECB/CBC encryption/decryption requires the data to be blocksize aligned.
Crypto engine hangs on non-block sized operations for these algorithms.
Return invalid data if data size is not blocksize aligned for these
algorithms.
Signed-off-by: Thara Gopinath
---
v5->v6:
- Remove the wr
Set the register REG_ENCR_XTS_DU_SIZE to cryptlen for AES XTS
transformation. Anything else causes the engine to return back
wrong results.
Acked-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 8
1 file changed, 4 insertions(+), 4 deletions
Crypto engine BAM dma does not support 0 length data. Return unsupported
if zero length messages are passed for transformation.
Signed-off-by: Thara Gopinath
---
v5->v6:
- Return 0 for zero length messages instead of -EOPNOTSUPP in the
cipher algorithms as pointed out by E
Crypto engine does not support key1 = key2 for AES XTS algorithm; the
operation hangs the engines. Return -EINVAL in case key1 and key2 are the
same.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff
Return unsupported if any three keys are same for DES3 algorithms
since CE does not support this and the operation causes the engine to
hang.
Signed-off-by: Thara Gopinath
---
v6->v7:
- Fixed sparse warning in patch 4 as pointed out by Herbert Xu.
This means the check
len > QCE_SECTOR_SIZE and is not a multiple
of it
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
index 11a2a3
ter this
behavior and allowed to proceed if rctx->buflen is 0 because the crypto
engine BAM does not allow for zero length transfers.
Reviewed-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/sha.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/
if buffer length is 0.
To fix these issues, save and restore the partial transformation state
using the newly introduced qce_sha_saved_state struct. This ensures that
all the pieces required to properly restart the transformation is captured
and restored back
Signed-off-by: Thara Gopinath
---
v4
ECB transformations do not have an IV and hence set the ivsize to 0 for
ecb(aes).
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
index c2f0469ffb22
m struct qce_sha_saved_state to store and restore
partial sha transformation.
- Rebased to 5.11-rc3.
Thara Gopinath (11):
crypto: qce: sha: Restore/save ahash state with custom struct in
export/import
crypto: qce: sha: Hold back a block of data to be transferred as part
of f
parameters in qce_start.
Reviewed-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 17 +++--
drivers/crypto/qce/common.h | 3 +--
drivers/crypto/qce/sha.c | 2 +-
drivers/crypto/qce/skcipher.c | 2 +-
4 files changed, 10 insertions(+), 14
Set the register REG_ENCR_XTS_DU_SIZE to cryptlen for AES XTS
transformation. Anything else causes the engine to return back
wrong results.
Acked-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 8
1 file changed, 4 insertions(+), 4 deletions
src_table is unused and hence remove it from struct qce_cipher_reqctx
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/cipher.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/crypto/qce/cipher.h b/drivers/crypto/qce/cipher.h
index cffa9fc628ff..850f257d00f3 100644
--- a/drivers
ECB/CBC encryption/decryption requires the data to be blocksize aligned.
Crypto engine hangs on non-block sized operations for these algorithms.
Return invalid data if data size is not blocksize aligned for these
algorithms.
Signed-off-by: Thara Gopinath
---
v5->v6:
- Remove the wr
len > QCE_SECTOR_SIZE and is not a multiple
of it
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
index 64f661
ECB transformations do not have an IV and hence set the ivsize to 0 for
ecb(aes).
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
index d24d96ed5be9
Crypto engine BAM dma does not support 0 length data. Return unsupported
if zero length messages are passed for transformation.
Signed-off-by: Thara Gopinath
---
v5->v6:
- Return 0 for zero length messages instead of -EOPNOTSUPP in the
cipher algorithms as pointed out by E
Return unsupported if any three keys are same for DES3 algorithms
since CE does not support this and the operation causes the engine to
hang.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/crypto/qce
Crypto engine does not support key1 = key2 for AES XTS algorithm; the
operation hangs the engines. Return -EINVAL in case key1 and key2 are the
same.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff
if buffer length is 0.
To fix these issues, save and restore the partial transformation state
using the newly introduced qce_sha_saved_state struct. This ensures that
all the pieces required to properly restart the transformation is captured
and restored back
Signed-off-by: Thara Gopinath
ter this
behavior and allowed to proceed if rctx->buflen is 0 because the crypto
engine BAM does not allow for zero length transfers.
Reviewed-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/sha.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/
Introduced custom struct qce_sha_saved_state to store and restore
partial sha transformation.
- Rebased to 5.11-rc3.
Thara Gopinath (11):
crypto: qce: sha: Restore/save ahash state with custom struct in
export/import
crypto: qce: sha: Hold back a block of data to be transferred as part
On 2/4/21 7:26 PM, Eric Biggers wrote:
On Thu, Feb 04, 2021 at 07:09:53PM -0500, Thara Gopinath wrote:
@@ -260,6 +261,10 @@ static int qce_skcipher_crypt(struct skcipher_request
*req, int encrypt)
rctx->flags |= encrypt ? QCE_ENCRYPT : QCE_DECRYPT;
keylen = IS_XTS(r
On 2/4/21 5:50 PM, Eric Biggers wrote:
On Thu, Feb 04, 2021 at 04:43:54PM -0500, Thara Gopinath wrote:
+ /*
+* ECB and CBC algorithms require message lengths to be
+* multiples of block size.
+* TODO: The spec says AES CBC mode for certain versions
Hi Eric,
On 2/4/21 5:48 PM, Eric Biggers wrote:
On Thu, Feb 04, 2021 at 04:43:53PM -0500, Thara Gopinath wrote:
Crypto engine BAM dma does not support 0 length data. Return unsupported
if zero length messages are passed for transformation.
Signed-off-by: Thara Gopinath
---
drivers/crypto
Return unsupported if any three keys are same for DES3 algorithms
since CE does not support this and the operation causes the engine to
hang.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/crypto/qce
On 2/3/21 9:42 PM, Herbert Xu wrote:
On Thu, Feb 04, 2021 at 04:56:17AM +0800, kernel test robot wrote:
Thank you for the patch! Yet something to improve:
Please fix this before you resubmit again.
Hi Herbert.
Sorry about that. I have send the fix.
Thanks,
--
Warm Regards
Thara
len > QCE_SECTOR_SIZE and is not a multiple
of it
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
index 10e85b
ECB/CBC encryption/decryption requires the data to be blocksize aligned.
Crypto engine hangs on non-block sized operations for these algorithms.
Return invalid data if data size is not blocksize aligned for these
algorithms.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 12
parameters in qce_start.
Reviewed-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 17 +++--
drivers/crypto/qce/common.h | 3 +--
drivers/crypto/qce/sha.c | 2 +-
drivers/crypto/qce/skcipher.c | 2 +-
4 files changed, 10 insertions(+), 14
src_table is unused and hence remove it from struct qce_cipher_reqctx
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/cipher.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/crypto/qce/cipher.h b/drivers/crypto/qce/cipher.h
index cffa9fc628ff..850f257d00f3 100644
--- a/drivers
Set the register REG_ENCR_XTS_DU_SIZE to cryptlen for AES XTS
transformation. Anything else causes the engine to return back
wrong results.
Acked-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 8
1 file changed, 4 insertions(+), 4 deletions
e to store and restore
partial sha transformation.
- Rebased to 5.11-rc3.
Thara Gopinath (11):
crypto: qce: sha: Restore/save ahash state with custom struct in
export/import
crypto: qce: sha: Hold back a block of data to be transferred as part
of final
crypto: qce: skciph
ECB transformations do not have an IV and hence set the ivsize to 0 for
ecb(aes).
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
index 28bea9584c33
Crypto engine BAM dma does not support 0 length data. Return unsupported
if zero length messages are passed for transformation.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto
Crypto engine does not support key1 = key2 for AES XTS algorithm; the
operation hangs the engines. Return -EINVAL in case key1 and key2 are the
same.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff
if buffer length is 0.
To fix these issues, save and restore the partial transformation state
using the newly introduced qce_sha_saved_state struct. This ensures that
all the pieces required to properly restart the transformation is captured
and restored back
Signed-off-by: Thara Gopinath
---
v4
ter this
behavior and allowed to proceed if rctx->buflen is 0 because the crypto
engine BAM does not allow for zero length transfers.
Reviewed-by: Bjorn Andersson
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/sha.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/
Crypto engine BAM dma does not support 0 length data. Return unsupported
if zero length messages are passed for transformation.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/skcipher.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto
src_table is unused and hence remove it from struct qce_cipher_reqctx
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/cipher.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/crypto/qce/cipher.h b/drivers/crypto/qce/cipher.h
index cffa9fc628ff..850f257d00f3 100644
--- a/drivers
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