a.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Thierry Reding
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On Tue, May 19, 2020 at 05:05:27PM +0300, Dmitry Osipenko wrote:
> 19.05.2020 10:28, Ulf Hansson пишет:
> > On Sat, 16 May 2020 at 17:44, Dmitry Osipenko wrote:
> >>
> >> Several people asked me about the MMC warnings in the KMSG log and
> >> I had to tell to ignore them because these warning are
On Mon, May 11, 2020 at 08:51:14AM +1000, Stephen Rothwell wrote:
> Hi all,
>
> After merging the tegra tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> ERROR: modpost: "host1x_driver_register_full"
> [drivers/staging/media/tegra-video/tegra-video.ko] undefined!
>
On Mon, May 11, 2020 at 07:20:15PM +0800, Samuel Zou wrote:
> Fix the following sparse warning:
>
> drivers/staging/media/tegra-video/tegra210.c:589:33: warning: symbol
> 'tegra210_video_formats' was not declared.
>
> The tegra210_video_formats has only call site within tegra210.c
> It should
On Fri, Apr 17, 2020 at 07:09:13PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> The MAX77620 doesn't support bulk writes, so make sure the regmap code
> breaks bulk writes into multiple single-byte writes.
>
> Note that this is mostly cosmetic because currentl
On Fri, May 01, 2020 at 03:53:09PM +0200, Alexandre Belloni wrote:
> On 01/05/2020 08:00:11-0500, Rob Herring wrote:
> > > I don't think this is true because in the case of a discrete RTC, its
> > > interrupt pin can be connected directly to a PMIC to power up a board
> > > instead of being
On Sun, Apr 26, 2020 at 09:16:30PM +0200, Christophe JAILLET wrote:
> 'host1x_debug_init()' must be reverted in an error handling path.
>
> This is already fixed in the remove function since commit 44156eee91ba
> ("gpu: host1x: Clean up debugfs on removal")
>
> Signed-off-by: Christophe JAILLET
On Wed, May 06, 2020 at 02:32:34PM +0200, Geert Uytterhoeven wrote:
> Hi all,
>
> The Tegra EMC scaling support code is not a clock provider, but merely a
> clock consumer, and thus does not need to include
> .
>
> However, drivers/memory/tegra/tegra210-emc-table.c relies on
>
gt; ---
> include/linux/of_reserved_mem.h | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Thierry Reding
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On Wed, May 06, 2020 at 02:32:36PM +0200, Geert Uytterhoeven wrote:
> The Tegra EMC scaling support code is not a clock provider, but merely a
> clock consumer, and thus does not need to include
> .
>
> Fixes: ec37a9a17afbfad5 ("memory: tegra: Add EMC scaling support code for
> Tegra210")
>
On Wed, Apr 08, 2020 at 09:00:30PM +0200, Arnd Bergmann wrote:
> The suspend/resume functions have no callers depending on
> configuration, so they must be marked __maybe_unused to
> avoid these harmless warnings:
>
> drivers/memory/tegra/tegra186.c:1578:12: error: 'tegra186_mc_resume' defined
>
On Wed, May 06, 2020 at 10:09:07PM +0200, Christophe JAILLET wrote:
> The call to 'tegra_bpmp_get()' must be balanced by a call to
> 'tegra_bpmp_put()' in case of error, as already done in the remove
> function.
>
> Add an error handling path and corresponding goto.
>
> Fixes: 52d15dd23f0b
On Fri, Apr 17, 2020 at 07:05:37PM +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> When the XUDC device is idle (i.e. powergated), care must be taken not
> to access any registers because that would lead to a crash.
>
> Move the call to tegra_xudc_device_mode_o
On Thu, Mar 19, 2020 at 10:02:17PM +0300, Dmitry Osipenko wrote:
> Hello,
>
> This series moves intermediate-clk handling from tegra20-cpufreq into
> tegra-clk driver. This allows us to switch to generic cpufreq-dt driver
> which brings voltage scaling, per-hardware OPPs and Tegra30 support out
>
On Mon, Apr 27, 2020 at 09:18:00AM +0200, Thierry Reding wrote:
> On Tue, Apr 07, 2020 at 12:05:20PM +0200, Thierry Reding wrote:
> > On Wed, Dec 04, 2019 at 03:21:38PM +0530, Viresh Kumar wrote:
> > > On 04-12-19, 10:33, Thierry Reding wrote:
> > > > Yeah, the c
On Wed, Mar 25, 2020 at 01:43:34AM +0300, Dmitry Osipenko wrote:
> ASUS TF300T device may not work properly if firmware is asked to fully
> re-initialize L2 cache after resume from LP2 suspend. The downstream
> kernel of TF300T uses different opcode to enable cache after resuming
> from LP2, this
On Wed, Mar 25, 2020 at 01:43:33AM +0300, Dmitry Osipenko wrote:
> Downstream kernel of ASUS TF300T sets r0 to #3. There is no explanation in
> downstream code whether this is really needed and some of T30 downstream
> kernels have and explicit comment telling that all arguments are ignored
> by
On Wed, Mar 25, 2020 at 01:43:35AM +0300, Dmitry Osipenko wrote:
> The new Tegra CPU Idle driver now has a unified code path for the coupled
> CC6 (LP2) state, this allows to enable the deepest idling state on Tegra30
> SoC where the whole CPU cluster is power-gated.
>
> Tested-by: Michał
On Mon, May 04, 2020 at 02:32:51PM +0530, Nagarjuna Kristam wrote:
> >On 28-04-2020 16:25, Thierry Reding wrote:
> > > On Wed, Apr 15, 2020 at 01:55:06PM +0530, Nagarjuna Kristam wrote:
[...]
> > > diff --git a/drivers/phy/tegra/xusb-tegra-cd.c
> > > b/
On Sat, May 02, 2020 at 05:40:35PM +0300, Dmitry Osipenko wrote:
> 27.04.2020 18:31, Wolfram Sang пишет:
> >
> >> Yes, that bug should be fixed anyway. But that doesn't justify breaking
> >> suspend/resume completely, which *is* a regression.
> >>
> >> Look, I'm not saying that we should drop
On Wed, Apr 29, 2020 at 03:35:26PM +0300, Dmitry Osipenko wrote:
> 29.04.2020 11:55, Thierry Reding пишет:
> ...
> >>> It's not "papering over an issue". The bug can't be fixed properly
> >>> without introducing I2C atomic transfers support for a late su
On Wed, Apr 29, 2020 at 05:46:46PM +0300, Dmitry Osipenko wrote:
> 29.04.2020 16:57, Jon Hunter пишет:
> >
> > On 29/04/2020 13:35, Dmitry Osipenko wrote:
> >> 29.04.2020 11:55, Thierry Reding пишет:
> >> ...
> >>>>> It's not "
On Wed, Apr 29, 2020 at 10:14:48AM +0200, Thierry Reding wrote:
> On Mon, Apr 27, 2020 at 06:18:34PM +0300, Dmitry Osipenko wrote:
> > 27.04.2020 18:12, Thierry Reding пишет:
> > > On Mon, Apr 27, 2020 at 05:21:30PM +0300, Dmitry Osipenko wrote:
> > >> 27.04.20
On Mon, Apr 27, 2020 at 06:18:34PM +0300, Dmitry Osipenko wrote:
> 27.04.2020 18:12, Thierry Reding пишет:
> > On Mon, Apr 27, 2020 at 05:21:30PM +0300, Dmitry Osipenko wrote:
> >> 27.04.2020 14:00, Thierry Reding пишет:
> >>> On Mon, Apr 27, 2020 at 12:52:10P
adctl_soc);
>
Same comments as for patch 7/8, with those addressed:
Acked-by: Thierry Reding
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pdate for the change I suggested in patch 6/8,
but with that and the typo above addressed, this is:
Acked-by: Thierry Reding
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On Wed, Apr 15, 2020 at 01:55:06PM +0530, Nagarjuna Kristam wrote:
> Perform charger-detect operation if corresponding dt property is enabled.
> Update usb-phy with the detected charger state and max current values.
> Register charger-detect API's of usb-phy to provide needed functionalities.
>
>
tam
> ---
> V2:
> - Patch re-based.
> ---
> drivers/phy/tegra/xusb-tegra210.c | 190
> ++
> 1 file changed, 133 insertions(+), 57 deletions(-)
Ignore that previous comment, I was making wrong assumptions:
Acked-by: Thierry Reding
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nd my prior comments, for some reason I thought this was adding a
custom API for driver interoperability, but I see now that this is just
a means of splitting out SoC-specific code, so:
Acked-by: Thierry Reding
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On Wed, Apr 15, 2020 at 01:55:05PM +0530, Nagarjuna Kristam wrote:
> When USB charger is enabled, UTMI PAD needs to be protected according
> to the direction and current level. Add support for the same on Tegra210
> and Tegra186.
>
> Signed-off-by: Nagarjuna Kristam
> ---
> V2:
> - Commit
On Wed, Apr 15, 2020 at 01:55:04PM +0530, Nagarjuna Kristam wrote:
> Add USB2 pad power on and off API's for TEgra210 and provide its control
"Tegra210"
> via soc ops. It can be used by operations like charger detect to power on
> and off USB2 pad if needed.
>
> Signed-off-by: Nagarjuna Kristam
On Wed, Apr 15, 2020 at 01:55:03PM +0530, Nagarjuna Kristam wrote:
> Add support for UTMI pad power on and off API's via soc ops. These API
> can be used by operations like charger detect to power on and off UTMI
> pad if needed. Update powered_on flag in the pad power control API's.
>
>
On Wed, Apr 15, 2020 at 01:55:02PM +0530, Nagarjuna Kristam wrote:
> Register vbus_draw to gadget ops and update corresponding vbus
> draw current to usb_phy.
>
> Signed-off-by: Nagarjuna Kristam
> ---
> V2:
> - Patch re-based.
> ---
> drivers/usb/gadget/udc/tegra-xudc.c | 16
ristam
> Acked-by: Rob Herring
> ---
> V2:
> - Added Acked-by updates to commit message.
> ---
> Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt | 4
>
> 1 file changed, 4 insertions(+)
Acked-by: Thierry Reding
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On Mon, Oct 21, 2019 at 11:42:05AM +0200, Enric Balletbo i Serra wrote:
> Hi Thierry,
> On 17/10/19 13:35, Thierry Reding wrote:
> > On Wed, Oct 09, 2019 at 03:47:43PM +0200, Enric Balletbo i Serra wrote:
>
> [snip]
>
> >
> > --- >8 ---
> > From 15245e
tegra/pinctrl-tegra.c | 3 +--
> 2 files changed, 2 insertions(+), 5 deletions(-)
Acked-by: Thierry Reding
> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
> b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
> index f2fa1f7..6f7b376 100644
> --- a/drivers/pinctrl/tegra/
rSpeed 20 Gbit/s) (a.k.a. USB 3.2 Gen 2 x 2)
...
Or those could just be sequentially enumerated, like in the above
example.
Rob, any thoughts?
Thierry
> 3. In individual phy driver, to add SOC/PHY specific programming accordingly.
>
> Thanks,
> JC
>
> On 10/14/19 9:40 P
aps it can
be repurposed for PHY_MODE_USB_HOST_SS?
Thierry
>
> Thanks,
> JC
>
> On 10/14/19 9:40 PM, Rob Herring wrote:
> > On Mon, Oct 14, 2019 at 8:17 AM Thierry Reding
> > wrote:
> >>
> >> On Wed, Oct 09, 2019 at 06:39:00PM -0500, Rob Her
gt; 2. .enabled is false
> >>> 3. the PWM is not already enabled
> >>>
> >>> (#3 included to avoid too many false positives when disabling a PWM)
> >>
> >> I think I created a patch for that in the past, don't remember the
> >> details.
> >
On Wed, Oct 16, 2019 at 11:02:47PM -0700, Guru Das Srinagesh wrote:
> On Wed, Oct 16, 2019 at 12:15:39PM +0200, Thierry Reding wrote:
> > On Tue, Oct 15, 2019 at 07:11:39PM -0700, Guru Das Srinagesh wrote:
> > > Because period and duty cycle are defined as ints with units of
On Sat, Oct 05, 2019 at 10:12:12PM +0530, Vidya Sagar wrote:
> Although Tegra194 has support for CLKREQ sideband signal and P2972
> has routing of the same till the slot, it is the case most of the time
> that the connected device doesn't have CLKREQ support. Hence, it makes
> sense to assume that
E_EN;
> + val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
> appl_writel(pcie, val, APPL_PINMUX);
> }
If we do support CLKREQ, do we have to explicitly set the OVERRIDE bit?
Or clear the OVERRIDE_EN bit? Is it always guaranteed that the defaults
(OVERRIDE_EN = 0) is applied
On Wed, Oct 16, 2019 at 04:16:27PM +0300, Dmitry Osipenko wrote:
> 16.10.2019 08:27, Viresh Kumar пишет:
> > On 16-10-19, 00:16, Dmitry Osipenko wrote:
> >> Hello,
> >>
> >> This series moves intermediate-clk handling from tegra20-cpufreq into
> >> tegra-clk driver, this allows us to switch to
On Tue, Oct 15, 2019 at 07:11:39PM -0700, Guru Das Srinagesh wrote:
> Because period and duty cycle are defined as ints with units of
> nanoseconds, the maximum time duration that can be set is limited to
> ~2.147 seconds. Change their definitions to u64 so that higher durations
> may be set.
>
>
On Tue, Oct 15, 2019 at 07:11:39PM -0700, Guru Das Srinagesh wrote:
> Because period and duty cycle are defined as ints with units of
> nanoseconds, the maximum time duration that can be set is limited to
> ~2.147 seconds. Change their definitions to u64 so that higher durations
> may be set.
>
>
On Mon, Oct 14, 2019 at 03:53:03PM +0200, meg...@megous.com wrote:
> From: Ondrej Jirman
>
> Since 5.4-rc1, pwm_apply_state calls ->get_state after ->apply
> if available, and this revealed an issue with integer precision
> when calculating duty_cycle and period for the currently set
> state in
On Fri, Oct 04, 2019 at 02:53:53PM +0200, Fabrice Gasnier wrote:
> Add suspend/resume PM sleep ops. When going to low power, enforce the PWM
> channel isn't active. Let the PWM consumers disable it during their own
> suspend sequence, see [1]. So, perform a check here, and handle the
> pinctrl
On Fri, Oct 04, 2019 at 02:53:52PM +0200, Fabrice Gasnier wrote:
> Split breakinput routine that configures STM32 timers 'break' safety
> feature upon probe, into two routines:
> - stm32_pwm_apply_breakinputs() sets all the break inputs into registers.
> - stm32_pwm_probe_breakinputs() probes the
On Fri, Oct 04, 2019 at 02:53:51PM +0200, Fabrice Gasnier wrote:
> Add documentation for pinctrl sleep state that can be used by
> STM32 timers PWM.
>
> Signed-off-by: Fabrice Gasnier
> ---
> Documentation/devicetree/bindings/pwm/pwm-stm32.txt | 8 +---
> 1 file changed, 5 insertions(+), 3
restart mechanism.
Acked-by: Arnd Bergmann
Reviewed-by: Wolfram Sang
Signed-off-by: Guenter Roeck
Signed-off-by: Thierry Reding
---
arch/arm/kernel/setup.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
From: Guenter Roeck
All users of arm_pm_restart() have been converted to use the kernel
restart handler.
Acked-by: Arnd Bergmann
Reviewed-by: Wolfram Sang
Tested-by: Wolfram Sang
Acked-by: Catalin Marinas
Signed-off-by: Guenter Roeck
Signed-off-by: Thierry Reding
---
arch/arm64/include
From: Guenter Roeck
All users of arm_pm_restart() have been converted to use the kernel
restart handler.
Acked-by: Arnd Bergmann
Reviewed-by: Wolfram Sang
Signed-off-by: Guenter Roeck
Signed-off-by: Thierry Reding
---
arch/arm/include/asm/system_misc.h | 1 -
arch/arm/kernel/reboot.c
the
default arm restart handler.
Acked-by: Arnd Bergmann
Reviewed-by: Wolfram Sang
Signed-off-by: Guenter Roeck
Signed-off-by: Thierry Reding
---
arch/arm/mach-prima2/rstc.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach
, but
keep it as low as possible since PSCI reset is known to fail on some
boards.
Acked-by: Arnd Bergmann
Reviewed-by: Wolfram Sang
Tested-by: Wolfram Sang
Signed-off-by: Guenter Roeck
Acked-by: Lorenzo Pieralisi
Signed-off-by: Thierry Reding
---
drivers/firmware/psci/psci.c | 12 ++--
1
From: Thierry Reding
Hi Russell, ARM SoC maintainers,
here's the full set of patches that remove arm_pm_restart as discussed
earlier. There's some background on the series in this thread:
https://lore.kernel.org/linux-arm-kernel/20170130110512.6943-1-thierry.red...@gmail.com/
I also
-off-by: Guenter Roeck
Signed-off-by: Thierry Reding
---
arch/arm/xen/enlighten.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 1e57692552d9..eb0a0edb9909 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch
; config PWM_SAMSUNG
> tristate "Samsung PWM support"
> - depends on PLAT_SAMSUNG || ARCH_EXYNOS
> + depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS
> help
> Generic PWM framework driver for Samsung.
>
Acked-by: Thierry Reding
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aps Greg should pick up this patch because he's carrying the patch
that adds the platform_get_irq_byname_optional() patch for v5.5.
Greg, would you prefer a copy of this in your mailbox, or does the
following patchwork link suffice:
http://patchwork.ozlabs.org/patch/1175012/
Either way, this patch:
Acked-by: Thierry Reding
Thierry
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On Wed, Oct 09, 2019 at 06:39:00PM -0500, Rob Herring wrote:
> On Wed, Oct 09, 2019 at 10:43:41AM +0800, JC Kuo wrote:
> > Extend the bindings to cover the set of features found in Tegra194.
> > Note that, technically, there are four more supplies connected to the
> > XUSB pad controller
a soc supports USB 3.1 Gen 2 speed
>
> drivers/phy/tegra/Makefile| 1 +
> drivers/phy/tegra/xusb-tegra186.c | 74 +++
> drivers/phy/tegra/xusb.c | 7 +++
> drivers/phy/tegra/xusb.h | 6 +++
> 4 files changed, 88 insertions(+)
Acked-by: Thierry Reding
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e sufficient.
>
> Signed-off-by: JC Kuo
> ---
> Changes in v4: none
> Changes in v3: none
> Changes in v2:
> - new patch to protect Tegra186 soc data with config
>
> drivers/phy/tegra/xusb-tegra186.c | 70 ---
> 1 file changed, 36 insertions(+),
On Mon, Oct 14, 2019 at 02:48:03PM +0200, Miquel Raynal wrote:
> The MAX7313 chip is fully compatible with the PCA9535 on its basic
> functions but can also manage the intensity on each of its ports with
> PWM. Each output is independent and may be tuned with 16 values (4
> bits per output). The
On Mon, Sep 23, 2019 at 01:55:44PM +0530, Nagarjuna Kristam wrote:
> Patches 1-3 are phy driver changes to add support for device
> mode.
> Patches 4-7 are changes related to XUSB device mode
> controller driver.
> Patch 8 is to enable drivers for XUDC support in defconfig
>
> Test Steps(USB
cker
>
> Signed-off-by: Nagarjuna Kristam
> Acked-by: Thierry Reding
> ---
> drivers/usb/gadget/udc/Kconfig | 11 +
> drivers/usb/gadget/udc/Makefile |1 +
> drivers/usb/gadget/udc/tegra-xudc.c | 3787
> +++
> 3 files changed, 3799
On Mon, Oct 07, 2019 at 01:03:11PM +0200, Greg KH wrote:
> On Sat, Oct 05, 2019 at 12:28:59AM +0800, JC Kuo wrote:
> > Hi,
> >
> > This series introduces support for Tegra194 XUSB host and pad
> > controller. Tegra194 XUSB host and pad controller are highly
> > similar to the controllers found on
From: Thierry Reding
The stmmac driver will try to acquire its private mutex during suspend
via phylink_resolve() -> stmmac_mac_link_down() -> stmmac_eee_init().
However, the phylink configuration is updated with the private mutex
held already, which causes a deadlock during suspend
From: Thierry Reding
regmap_add_irq_chip() will try to allocate all of the IRQ descriptors
upfront if passed a non-zero irq_base parameter. However, the intention
is to allocate IRQ descriptors on an as-needed basis if possible. Pass 0
instead of -1 to fix that use-case.
Signed-off-by: Thierry
From: Thierry Reding
The gpiod_set_debounce() function takes the debounce time in
microseconds. Adjust the switch/case values in the MAX77620 GPIO to use
the correct unit.
Signed-off-by: Thierry Reding
---
drivers/gpio/gpio-max77620.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions
-off-by: Timo Alho
Signed-off-by: Thierry Reding
---
drivers/gpio/gpio-max77620.c | 231 ++-
1 file changed, 117 insertions(+), 114 deletions(-)
diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
index c58b56e5291e..c5b64a4ac172 100644
From: Thierry Reding
regmap_add_irq_chip() will try to allocate all of the IRQ descriptors
upfront if passed a non-zero irq_base parameter. However, the intention
is to allocate IRQ descriptors on an as-needed basis if possible. Pass 0
instead of -1 to fix that use-case.
Signed-off-by: Thierry
sertions(+), 2 deletions(-)
Acked-by: Thierry Reding
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), 3 deletions(-)
Acked-by: Thierry Reding
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), 3 deletions(-)
Acked-by: Thierry Reding
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On Tue, Oct 01, 2019 at 04:47:17PM +0300, Andy Shevchenko wrote:
> Use %ptT instead of open coded variant to print content of
> time64_t type in human readable format.
>
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Signed-off-by: Andy Shevchenko
> ---
> drivers/u
On Wed, Oct 02, 2019 at 11:08:44AM +0100, Colin King wrote:
> From: Colin Ian King
>
> Variable pval is being assigned a value that is never read. The
> assignment is redundant and hence can be removed.
>
> Addresses-Coverity: ("Unused value")
> Signed-off-by: Colin Ian King
> ---
>
On Wed, Oct 02, 2019 at 04:00:51PM +0800, JC Kuo wrote:
> This commit enables XUSB host and pad controller in Tegra194
> P2972- board.
>
> Signed-off-by: JC Kuo
> ---
> .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 31 +-
> .../boot/dts/nvidia/tegra194-p2972-.dts | 59
On Wed, Oct 02, 2019 at 04:00:50PM +0800, JC Kuo wrote:
> Adds the XUSB pad and XUSB controllers on Tegra194.
>
> Signed-off-by: JC Kuo
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 130 +++
> 1 file changed, 130 insertions(+)
>
> diff --git
On Wed, Oct 02, 2019 at 04:00:50PM +0800, JC Kuo wrote:
> Adds the XUSB pad and XUSB controllers on Tegra194.
>
> Signed-off-by: JC Kuo
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 130 +++
> 1 file changed, 130 insertions(+)
>
> diff --git
On Wed, Oct 02, 2019 at 04:00:48PM +0800, JC Kuo wrote:
> Add support for the XUSB pad controller found on Tegra194 SoCs. It is
> mostly similar to the same IP found on Tegra186, but the number of
> pads exposed differs, as do the programming sequences. Because most of
> the Tegra194 XUSB PADCTL
b3: usb3-0, usb3-1, usb3-2, usb3-3
> + - functions: "xusb"
>
> Port nodes:
> ===
> @@ -221,6 +231,9 @@ Optional properties:
>is internal. In the absence of this property the port is considered to be
>external.
>
> +- nvidia,disable-gen2: A boolean property whose presence determines that a
> port
> + should be limited to USB 3.1 Gen 1. This properlty is only for Tegra194.
s/properlty/property/
With that:
Acked-by: Thierry Reding
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t; 3. mailbox registers address changes
>
> Signed-off-by: JC Kuo
> ---
> drivers/usb/host/xhci-tegra.c | 30 ++
> 1 file changed, 30 insertions(+)
Acked-by: Thierry Reding
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> ---
> drivers/usb/host/xhci-tegra.c | 58 +--
> 1 file changed, 42 insertions(+), 16 deletions(-)
Acked-by: Thierry Reding
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Description: PGP signature
On Tue, Sep 03, 2019 at 04:26:52PM +0530, Nagarjuna Kristam wrote:
> tegra_fuse_readl() can be called from drivers at any time. If this API is
> called before tegra_fuse_probe(), we end up enabling clock before it is
> registered. Add check for fuse clock in tegra_fuse_readl() and return
>
On Wed, Aug 14, 2019 at 10:53:38AM +, Philippe Schenker wrote:
> Add the stmpe-adc DT node as found on Toradex T30 modules
>
> Signed-off-by: Philippe Schenker
>
> ---
>
> arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi | 22 ++
> arch/arm/boot/dts/tegra30-apalis.dtsi
On Tue, Oct 01, 2019 at 03:23:30PM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> The regulator_bulk_set_supply_names() helper was merged upstream. Use it
> in a couple tegra drivers.
>
> Bartosz Golaszewski (3):
> ahci: tegra: use regulator_bulk_set_supply_names()
> phy:
On Fri, Jan 04, 2019 at 09:30:09PM +0200, Andy Shevchenko wrote:
> Use %ptT instead of open coded variant to print content of
> time64_t type in human readable format.
>
> Cc: Mathias Nyman
> Cc: Thierry Reding
> Cc: Jonathan Hunter
> Signed-off-by: Andy Shevchenko
>
On Mon, Sep 30, 2019 at 11:54:59AM +, Philippe Schenker wrote:
> On Wed, 2019-08-14 at 10:53 +, Philippe Schenker wrote:
> > Add the stmpe-adc DT node as found on Toradex T30 modules
> >
> > Signed-off-by: Philippe Schenker
>
> Hi Thierry, could you please pull this patch for 5.4? Or
On Mon, Sep 30, 2019 at 10:55:15AM +0100, Robin Murphy wrote:
> On 2019-09-30 9:56 am, Thierry Reding wrote:
> > On Mon, Sep 30, 2019 at 01:20:55AM -0700, Christoph Hellwig wrote:
> > > On Sun, Sep 29, 2019 at 01:16:20PM +0200, Arnd Bergmann wrote:
> > > > On a se
On Mon, Sep 30, 2019 at 04:51:08PM +0800, Sam Shih wrote:
> Hi,
>
> On Fri, 2019-09-27 at 13:28 +0200, Thierry Reding wrote:
> > On Wed, Sep 25, 2019 at 10:32:33PM +0800, Sam Shih wrote:
> > > This adds pwm support for MT7629, and separate mt7629 compatible
On Mon, Sep 30, 2019 at 01:20:55AM -0700, Christoph Hellwig wrote:
> On Sun, Sep 29, 2019 at 01:16:20PM +0200, Arnd Bergmann wrote:
> > On a semi-related note, Thierry asked about one aspect of the dma-ranges
> > property recently, which is the behavior of dma_set_mask() and related
> > functions
On Sun, Sep 29, 2019 at 08:59:38PM +0300, Dmitry Osipenko wrote:
> Hello,
>
> This series does the following:
>
> 1. Unifies Tegra20/30/114 drivers into a single driver and moves it out
> into common drivers/cpuidle/ directory.
>
> 2. Enables CPU cluster power-down idling state on
On Sun, Sep 29, 2019 at 08:59:46PM +0300, Dmitry Osipenko wrote:
> The outer_disable() of Tegra's suspend code is open-coded now since
> that helper produces spurious warning message about secondary CPUs being
> online. The secondaries are actually halted by the cpuidle driver on
> entering into
() usage after platform_get_irq()
Thierry Reding (2):
pwm: atmel: Remove unneeded check for match data
pwm: atmel: Consolidate driver data initialization
Uwe Kleine-König (12):
pwm: jz4740: Document known limitations
pwm: imx: Document known limitations
pwm: rockchip: Set
On Wed, Sep 25, 2019 at 10:32:33PM +0800, Sam Shih wrote:
> This adds pwm support for MT7629, and separate mt7629 compatible string
> from mt7622
>
> Signed-off-by: Sam Shih
> ---
> drivers/pwm/pwm-mediatek.c | 6 ++
> 1 file changed, 6 insertions(+)
I picked this patch up and made some
On Mon, Sep 23, 2019 at 01:55:44PM +0530, Nagarjuna Kristam wrote:
> Patches 1-3 are phy driver changes to add support for device
> mode.
> Patches 4-7 are changes related to XUSB device mode
> controller driver.
> Patch 8 is to enable drivers for XUDC support in defconfig
>
> Test Steps(USB
On Wed, Sep 25, 2019 at 10:32:32PM +0800, Sam Shih wrote:
> From: Ryder Lee
>
> This adds a property "num-pwms" in example so that we could
> specify the number of PWM channels via device tree.
>
> Signed-off-by: Ryder Lee
> Signed-off-by: Sam Shih
> Reviewed-by: Matthias Brugger
> Acked-by:
On Wed, Sep 25, 2019 at 08:30:03AM +0200, Uwe Kleine-König wrote:
> On Fri, Sep 20, 2019 at 06:49:03AM +0800, Sam Shih wrote:
> > We can use fixed-clock to repair mt7628 pwm during configure from
> > userspace. The SoC is legacy MIPS and has no complex clock tree.
> > Due to we can get clock
On Tue, Sep 24, 2019 at 05:42:48PM +0800, Anson Huang wrote:
> Use the new helper devm_platform_ioremap_resource() which wraps the
> platform_get_resource() and devm_ioremap_resource() together, to
> simplify the code.
>
> Signed-off-by: Anson Huang
> ---
> - This is a resend version of
On Tue, Sep 24, 2019 at 05:42:49PM +0800, Anson Huang wrote:
> Add helper variable dev = >dev to simply the code.
>
> Signed-off-by: Anson Huang
> ---
> drivers/pwm/pwm-mxs.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deletions(-)
Again, lots of churn, no gain.
Thierry
On Tue, Sep 24, 2019 at 05:01:07PM +0800, Anson Huang wrote:
> Add helper variable dev = >dev to simply the code.
>
> Signed-off-by: Anson Huang
> ---
> drivers/pwm/pwm-imx-tpm.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deletions(-)
Again, positive diffstat and doesn't gain
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