Hi Krzysztof,
Good idea, just a couple of nits inline. Other than that:
Acked-by: Tomasz Figa
2015-11-16 10:36 GMT+09:00 Krzysztof Kozlowski :
> Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS
> so it is built also on ARMv7. This does not bring any kind of b
uffers might be still in processing.
Signed-off-by: John Sheu
Reviewed-by: Pawel Osciak
Reviewed-by: Tomasz Figa
Signed-off-by: Tomasz Figa
---
drivers/media/v4l2-core/videobuf2-core.c | 22 --
1 file changed, 22 deletions(-)
diff --git a/drivers/media/v4l2-core/videobuf2-co
On Tue, Sep 29, 2015 at 6:43 PM, Thierry Reding
wrote:
> On Tue, Sep 29, 2015 at 02:25:25PM +0900, Tomasz Figa wrote:
>> From: Vince Hsu
>>
>> This patch adds SMMU line size to Tegra SoC data struct to enable SMMU
>> driver to use this knowledge in code added by fur
On Tue, Sep 29, 2015 at 6:32 PM, Thierry Reding
wrote:
> On Tue, Sep 29, 2015 at 02:25:24PM +0900, Tomasz Figa wrote:
>> This patch adds a new "flush" callback to iommu_ops, which is supposed
>> to perform any necessary flushes within given IOMMU domain to make any
>&g
On Tue, Sep 29, 2015 at 6:27 PM, Thierry Reding
wrote:
>
> On Tue, Sep 29, 2015 at 02:25:23PM +0900, Tomasz Figa wrote:
> > Currently the IOMMU subsystem provides 3 basic operations: iommu_map(),
> > iommu_map_sg() and iommu_unmap(). iommu_map() can be used to map memory
> &g
This patch modifies the tegra-smmu driver to perform PTC and TLB flushes
inside iommu_ops .flush() callback instead of map and unmap operations,
so that performance of large maps and unmaps is heavily optimized due to
elimination of page-by-page flushing.
Signed-off-by: Tomasz Figa
Signed-off-by
lushes and
replace it with one flush of full address range on devices which support
it.
Signed-off-by: Tomasz Figa
---
drivers/iommu/iommu.c | 33 ++---
include/linux/iommu.h | 2 ++
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/iommu.c
: Tomasz Figa
---
drivers/memory/tegra/tegra114.c | 1 +
drivers/memory/tegra/tegra124.c | 3 +++
drivers/memory/tegra/tegra210.c | 1 +
drivers/memory/tegra/tegra30.c | 1 +
include/soc/tegra/mc.h | 1 +
5 files changed, 7 insertions(+)
diff --git a/drivers/memory/tegra/tegra114.c b
every buffer size. ~18M means around 17-19M due do the variance
in requested buffer sizes.
Tomasz Figa (2):
iommu: Add support for out of band flushing
iommu/tegra-smmu: Make the driver use out of band flushing
Vince Hsu (1):
memory: tegra: add TLB cache line size
drivers/iommu/io
; ---
> drivers/clk/samsung/clk-s5pv210.c | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Tomasz Figa
Best regards,
Tomasz
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I missed it originally, but if it's not too late yet...
On Fri, Jun 26, 2015 at 7:07 PM, Mark Yao wrote:
> Window 1 support scale and yuv format, it's waste use it for a
> cursor, use window 3 is enough.
>
> Signed-off-by: Mark Yao
> ---
> Changes in v2: None
>
> drivers/gpu/drm/rockchip/rockch
-
> 1 file changed, 11 deletions(-)
Reviewed-by: Tomasz Figa
Best regards,
Tomasz
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Please read the FAQ at http://www.tux.org/lkml/
On Fri, Jul 3, 2015 at 7:08 PM, Mark yao wrote:
> On 2015年07月03日 17:24, Tomasz Figa wrote:
>>
>> On Fri, Jul 3, 2015 at 5:19 PM, Mark yao wrote:
>>>
>>> On 2015年07月03日 16:02, Tomasz Figa wrote:
>>>>
>>>> Hi Mark,
>>>>
>>
set_irq_flags calls. Some
> users also set IRQ_NOPROBE and this has been maintained although it is not
> clear that is really needed. There appears to be a great deal of blind
> copy and paste of this code.
>
> Signed-off-by: Rob Herring
> Acked-by: Linus Walleij
> Cc: Stephen War
read raw data for
>>> exynos4x12")
>>> Link: https://lkml.org/lkml/2015/6/11/85
>>>
>>> ---
>>>
>>> Changes since v1:
>>> 1. After discussion on LKML this solution was chosen because it smaller,
>>>simpler, self-containe
On Fri, Jul 3, 2015 at 7:22 PM, Mark yao wrote:
> On 2015年07月03日 17:58, Tomasz Figa wrote:
>>>>
>>>> >>Aren't the scl_modes for CbCr planes always the same as for Y plane?
>>>
>>> >
>>> >
>>> >No, such as sr
On Fri, Jul 3, 2015 at 6:17 PM, Mark yao wrote:
>>> +static void _vop_cal_scl_fac(struct vop *vop, const struct vop_win_data
>>> *win,
>>> +uint32_t src_w, uint32_t src_h, uint32_t
>>> dst_w,
>>> +uint32_t dst_h, uint32_t pixel_format)
>>> +{
On Fri, Jul 3, 2015 at 5:19 PM, Mark yao wrote:
> On 2015年07月03日 16:02, Tomasz Figa wrote:
>>
>> Hi Mark,
>>
>> Please see my comments inline.
>>
>> On Fri, Jun 26, 2015 at 7:10 PM, Mark Yao wrote:
>>>
>>> Win2/3 support 4 area display,
Hi Mark,
Please see my comments inline.
On Fri, Jun 26, 2015 at 7:10 PM, Mark Yao wrote:
> Win2/3 support 4 area display, but now havn't found a suitable
> way to use it, and it enable by win gate and area gate,
> so default enable area0 gate, so that its behaviour just like a
> win.
So I assum
---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
Reviewed-by: Tomasz Figa
Best regards,
Tomasz
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Hi Mark,
Please see my comments inline.
On Fri, Jun 26, 2015 at 7:07 PM, Mark Yao wrote:
> Win_full support 1/8 to 8 scale down/up engine, support
> all format scale.
[snip]
> @@ -351,6 +412,15 @@ static inline void vop_mask_write_relaxed(struct vop
> *vop, uint32_t offset,
> }
> }
>
On Thu, Jul 2, 2015 at 3:53 PM, Mark yao wrote:
> Hi Tomasz
> Thanks for your review, I will fix it soon.
>
> On 2015年07月02日 14:00, Tomasz Figa wrote:
>>
>> Hi Mark,
>>
>> Please see my comments inline.
>>
>> On Fri, Jun 26, 2015 at 7:07 PM, Ma
Hi Mark,
Please see my comments inline.
On Fri, Jun 26, 2015 at 7:07 PM, Mark Yao wrote:
> vop support yuv with NV12, NV16 and NV24, only 2 plane yuv.
>
> Signed-off-by: Mark Yao
>
> Changes in v2:
> - Uv buffer not support odd offset, align it.
> - Fix error display when move yuv image.
>
> --
On Fri, Jun 26, 2015 at 7:07 PM, Mark Yao wrote:
> vir_stride need number words of the virtual width, and fb->pitches
> save bytes_per_pixel, so just div 4 switch to stride.
>
> Signed-off-by: Mark Yao
> ---
> Changes in v2: None
>
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c |2 +-
> 1 fil
2015-06-16 0:00 GMT+09:00 Javier Martinez Canillas
:
> Hello Sudeep,
>
> On 06/15/2015 11:01 AM, Sudeep Holla wrote:
>>
>>
>> On 15/06/15 08:46, Javier Martinez Canillas wrote:
>> [...]
>>
>>>
>>> Sudeep, so we may need something like $subject after all from Doug's
>>> explanations since the combin
2015-06-11 21:40 GMT+09:00 Krzysztof Kozlowski :
> W dniu 11.06.2015 o 21:15, Javier Martinez Canillas pisze:
>> Hello Krzysztof,
>>
>> On Thu, Jun 11, 2015 at 12:43 PM, Krzysztof Kozlowski
>> wrote:
>>> W dniu 11.06.2015 o 17:26, Krzysztof Kozlowski pisze:
Add proper gate clock for the Analo
rivers/pinctrl/qcom/pinctrl-msm.c|2 +-
> drivers/pinctrl/samsung/pinctrl-exynos.c |8
> drivers/pinctrl/samsung/pinctrl-s3c24xx.c | 18 +-
> drivers/pinctrl/samsung/pinctrl-s3c64xx.c | 22 ++
For Samsun
On Mon, May 11, 2015 at 7:55 PM, Tomasz Figa wrote:
> VOP can support BGR formats in all windows thanks to red/blue swap option
> provided in WINx_CTRL0 registers. This patch enables support for
> ABGR, XBGR, BGR888 and BGR565 formats by using this feature.
>
> Signed-off-
Hi,
Please see my comments inline.
On Fri, May 15, 2015 at 6:43 PM, Yong Wu wrote:
[snip]
> +
> +struct mtk_iommu_info {
> + void __iomem*base;
> + int irq;
> + struct device *dev;
> + struct device *larbdev[MTK_IOMMU_LA
Hi,
Please see my comments inline.
On Fri, May 15, 2015 at 6:43 PM, Yong Wu wrote:
> This patch add smi binding document.
>
> Signed-off-by: Yong Wu
> ---
> .../bindings/soc/mediatek/mediatek,smi-larb.txt| 24
> ++
> .../bindings/soc/mediatek/mediatek,smi.txt |
Hi,
Please see my comments inline.
On Fri, May 15, 2015 at 6:43 PM, Yong Wu wrote:
> This patch add mediatek iommu dts binding document.
>
> Signed-off-by: Yong Wu
> ---
> .../devicetree/bindings/iommu/mediatek,iommu.txt | 51 ++
> include/dt-bindings/iommu/mt8173-iommu-port.h
VOP can support BGR formats in all windows thanks to red/blue swap option
provided in WINx_CTRL0 registers. This patch enables support for
ABGR, XBGR, BGR888 and BGR565 formats by using this feature.
Signed-off-by: Tomasz Figa
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 33
Hi Mark,
Thanks for review.
On Fri, May 8, 2015 at 5:40 PM, Mark yao wrote:
>> @@ -233,6 +243,7 @@ static const struct vop_win_phy win23_data = {
>> .nformats = ARRAY_SIZE(formats_234),
>> .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
>> .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
>>
VOP can support BGR formats in all windows thanks to red/blue swap option
provided in WINx_CTRL0 registers. This patch enables support for
ABGR, XBGR, BGR888 and BGR565 formats by using this feature.
Signed-off-by: Tomasz Figa
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 33
On Wed, Apr 15, 2015 at 4:06 PM, Yong Wu wrote:
> On Wed, 2015-04-15 at 11:20 +0900, Tomasz Figa wrote:
>> On Tue, Apr 14, 2015 at 3:31 PM, Yong Wu wrote:
>> >> >>
>> >> >> > +
>> >> >> > + piommu->p
On Tue, Apr 14, 2015 at 3:31 PM, Yong Wu wrote:
>> >>
>> >> > +
>> >> > + piommu->protect_va = devm_kmalloc(piommu->dev,
>> >> > MTK_PROTECT_PA_ALIGN*2,
>> >>
>> >> style: Operators like * should have space on both sides.
>> >>
>> >> > + GFP_KERNEL);
2015-04-07 16:11 GMT+02:00 Javier Martinez Canillas
:
> From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
> From: Javier Martinez Canillas
> Date: Tue, 7 Apr 2015 15:53:27 +0200
> Subject: [RFC PATCH] clk: exynos5420: Restore GATE_BUS_TOP on suspend
>
> Commit ae43b3289186 ("A
2015-04-07 13:56 GMT+02:00 Javier Martinez Canillas
:
> So I disabled the sss clock before trying a S2R:
>
> # devmem 0x10018800 32 0xFFFB
> (CLK_SSS in CLK_GATE_IP_G2D is gated)
>
> and S2R worked anyways but I see that CLK_GATE_IP_G2D is reset to
> its default value on S2R so maybe that is wh
Hi Eddie,
Please see my response inline.
On Tue, Mar 31, 2015 at 6:44 PM, Eddie Huang wrote:
[snip]
>> > + ret = mtk_rtc_read(rtc, RTC_BBPU, &data);
>> > + if (ret < 0)
>> > + goto exit;
>> > +
>> > + while (data & RTC_BBPU_CBUSY) {
>> > + cpu_rela
Hi Javier,
Please see my comments inline.
2015-03-31 0:53 GMT+09:00 Javier Martinez Canillas
:
[snip]
> diff --git a/drivers/clk/samsung/clk-exynos5420.c
> b/drivers/clk/samsung/clk-exynos5420.c
> index 07d666cc6a29..2d39b629144a 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/driver
Hi Javier,
2015-03-31 0:53 GMT+09:00 Javier Martinez Canillas
:
> The Samsung helpers functions to register clocks, add the clock instance
> returned by the common clock framework to a lookup table that is used by
> OF to lookup the clocks.
>
> But this table could also be useful to clock drivers
Hi Eddie,
Please see my comments inline.
On Wed, Mar 18, 2015 at 2:45 PM, Eddie Huang wrote:
> From: Tianping Fang
>
> Add Mediatek MT6397 RTC driver
[snip]
> +#define RTC_BBPU 0x
> +#define RTC_WRTGR 0x003c
> +#define RTC_IRQ_EN 0x0004
> +#define RT
Hi Yong Wu,
Sorry for long delay, I had to figure out some time to look at this again.
On Wed, Mar 18, 2015 at 8:22 PM, Yong Wu wrote:
>>
>> > + imudev = piommu->dev;
>> > +
>> > + spin_lock_irqsave(&priv->portlock, flags);
>>
>> What is protected by this spinlock?
>
| 1 +
> drivers/pinctrl/samsung/pinctrl-exynos.c | 103
> +
> drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
> drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
> 4 files changed, 107 insertions(+)
>
Acked-by: Tomas
Sorry, I had to dig my way out through my backlog.
On Tue, Mar 3, 2015 at 10:36 PM, Joerg Roedel wrote:
> On Mon, Feb 09, 2015 at 08:19:21PM +0900, Tomasz Figa wrote:
>> Even though the code uses the dt_lock spin lock to serialize mapping
>> operation from different threads, it d
__GFP_NORETRY, which bypasses OOM invocation, for orders higher than
zero and, only if that fails, fall back to normal order 0 allocation
which might invoke OOM killer.
Signed-off-by: Tomasz Figa
---
arch/arm/mm/dma-mapping.c | 27 +--
1 file changed, 21 insertions(+), 6 deletions
Hi David,
On Tue, Mar 17, 2015 at 8:32 AM, David Rientjes wrote:
> On Mon, 16 Mar 2015, Tomasz Figa wrote:
>
>> diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
>> index 83cd5ac..f081e9e 100644
>> --- a/arch/arm/mm/dma-mapping.c
>> +++ b/arch/arm/m
__GFP_NORETRY, which bypasses OOM invocation, for positive orders and
only if that fails doing OOMable order 0 allocation as a fall back.
Signed-off-by: Tomasz Figa
---
arch/arm/mm/dma-mapping.c | 29 +
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mm
Hi,
Please find next part of my comments inline.
On Fri, Mar 6, 2015 at 7:48 PM, wrote:
[snip]
> +/*
> + * pimudev is a global var for dma_alloc_coherent.
> + * It is not accepatable, we will delete it if "domain_alloc" is enabled
It looks like we indeed need to use dma_alloc_coherent() and
On Tue, Mar 10, 2015 at 12:41 PM, Yingjoe Chen
wrote:
> On Tue, 2015-03-10 at 02:00 +0900, Tomasz Figa wrote:
>> On Mon, Mar 9, 2015 at 11:46 PM, Yingjoe Chen
>> wrote:
>> > On Mon, 2015-03-09 at 20:11 +0900, Tomasz Figa wrote:
>> > <...>
>> >
On Mon, Mar 9, 2015 at 11:46 PM, Yingjoe Chen wrote:
> On Mon, 2015-03-09 at 20:11 +0900, Tomasz Figa wrote:
> <...>
>> > +/*
>> > + * pimudev is a global var for dma_alloc_coherent.
>> > + * It is not accepatable, we will delete it if "domain_all
Hi,
You can find part 2 of my comments inline.
On Fri, Mar 6, 2015 at 7:48 PM, wrote:
[snip]
> +static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
> +{
> + struct iommu_domain *domain = dev_id;
> + struct mtk_iommu_domain *mtkdomain = domain->priv;
> + struct mtk_iommu_
le, when "cache-size" or "cache-sets"
> properties haven't been filled in l2c dt node.
Just s/prefect/prefetch/ and s/of tree/device tree/ in patch
description (not sure if this could be fixed while applying or needs
respin). Otherwise:
Reviewed-by: Tomasz Figa
Best regar
Hi Yong Wu,
Thanks for this series. Please see my comments inline.
On Fri, Mar 6, 2015 at 7:48 PM, wrote:
> From: Yong Wu
>
> This patch adds support for mediatek m4u (MultiMedia Memory Management Unit).
> Currently this only supports m4u gen 2 with 2 levels of page table on mt8173.
[snip]
>
2015-02-25 19:13 GMT+09:00 Inha Song :
> Hi, Tomasz,
>
> Thanks for you comment :)
>
> On Wed, 25 Feb 2015 09:54:02 +0900
> Tomasz Figa wrote:
>
>> Hi Inha,
>>
>> Thanks for the patch. Please see my comments inline.
>>
>> 2015-02-24 18:22 GMT+
Hi Inha,
Thanks for the patch. Please see my comments inline.
2015-02-24 18:22 GMT+09:00 Inha Song :
> This patch add CLKOUT driver support for Exynos3250 SoC.
Could you please add a little more information? I know that it might
be pretty obvious to people familiar with this driver and/or hardwa
Hi Sascha,
On Fri, Feb 13, 2015 at 9:06 PM, Sascha Hauer wrote:
>
> Hi Tomasz,
>
>> > +static void mtk_cg_disable(struct clk_hw *hw)
>> > +{
>> > + mtk_cg_set_bit(hw);
>> > +}
>> > +
>> > +static int mtk_cg_enable_inv(struct clk_hw *hw)
>> > +{
>> > + mtk_cg_set_bit(hw);
>> > +
>> > +
Please find my comments inline.
On Mon, Feb 9, 2015 at 7:47 PM, Sascha Hauer wrote:
> From: James Liao
>
> This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs,
> INFRA and PERI clocks.
>
> Signed-off-by: James Liao
> Signed-off-by: Henry Chen
> Signed-off-by: Sascha Hauer
> ---
Hi,
Let me add some suggestions inline.
On Mon, Feb 9, 2015 at 7:47 PM, Sascha Hauer wrote:
> From: James Liao
>
> This patch adds common clock support for Mediatek SoCs, including plls,
> muxes and clock gates.
[snip]
> +static int mtk_cg_enable(struct clk_hw *hw)
> +{
> + mtk_cg_clr_b
On Mon, Feb 9, 2015 at 8:19 PM, Tomasz Figa wrote:
> Even though the code uses the dt_lock spin lock to serialize mapping
> operation from different threads, it does not protect from IOMMU
> accesses that might be already taking place and thus altering state
> of the IOTLB. Thi
his patch changes the mapping code to always zap the page table
after it is updated, which avoids the aforementioned race and also
zap the last page of the mapping to make sure that stale data is
not cached from an already existing mapping.
Signed-off-by: Tomasz Figa
Reviewed-by: Daniel Ku
gt; general
>> port groups and 2 memory port groups.
>>
>> Cc: Tomasz Figa
>> Cc: Thomas Abraham
>> Cc: Linus Walleij
>> Signed-off-by: Chanwoo Choi
>> Acked-by: Inki Dae
>> ---
>> Changes from v2:
>> - Rebase it on v3.19-rc5
>
2015-01-23 1:47 GMT+09:00 Sylwester Nawrocki :
> Hi Chanwoo,
>
> On 21/01/15 07:26, Chanwoo Choi wrote:
>> This patch adds the support for CMU (Clock Management Units) of Exynos5433
>> which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
>> (PLL/MMC/UART/MCT/I2C/SPI) for kern
Hi,
[CCing more people]
2015-01-16 23:39 GMT+09:00 Paul Osmialowski :
> This enhancement of i2c API is designed to address following problem
> caused by circular lock dependency:
>
> -> #1 (prepare_lock){+.+.+.}:
> [2.730502][] __lock_acquire+0x3c0/0x8a4
> [2.735970][] loc
2015-01-06 5:25 GMT+09:00 Arnd Bergmann :
> On Monday 05 January 2015 13:19:00 Marek Szyprowski wrote:
>> DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
>> + .l2c_aux_val= OMAP_L2C_AUX_CTRL,
>> + .l2c_aux_mask = 0xcf9f,
>> + .l2c_write_sec = omap4_
2015-01-04 1:45 GMT+09:00 Nishanth Menon :
> On 01/03/2015 10:16 AM, Tomasz Figa wrote:
>>
>> 2015-01-04 0:34 GMT+09:00 Nishanth Menon :
>>>
>>> On 15:40-20150103, Tomasz Figa wrote:
>>>>
>>>> Hi Nishanth,
>>>>
>>>
2015-01-04 0:34 GMT+09:00 Nishanth Menon :
> On 15:40-20150103, Tomasz Figa wrote:
>> Hi Nishanth,
>>
>> 2015-01-03 2:43 GMT+09:00 Nishanth Menon :
>> > AM437x generation of processors support programming the PL310 L2Cache
>> > controller's address f
Hi Tony,
2015-01-03 9:23 GMT+09:00 Tony Lindgren :
> * Nishanth Menon [150102 11:50]:
>> On 01/02/2015 12:46 PM, santosh.shilim...@oracle.com wrote:
>> > On 1/2/15 9:43 AM, Nishanth Menon wrote:
>> >> Hi,
>> >> OMAP4 and AM437x ROM code provides services to program PL310's latency
>> >> registers
Hi Nishanth,
2015-01-03 2:43 GMT+09:00 Nishanth Menon :
> AM437x generation of processors support programming the PL310 L2Cache
> controller's address filter start and end registers using a secure
> montior service.
typo: s/montior/monitor/
[snip]
> + base = omap4_get_l2cache_base
On 02.01.2015 18:13, Tomasz Figa wrote:
On 30.12.2014 23:51, Nishanth Menon wrote:
Looks like the following also need addressing:
data->save is called twice (once more after l2cof_init)
l2c310_init_fns also needs l2c310_configure
will be nice to use l2x0_data only after we kmemdup data
On 30.12.2014 23:51, Nishanth Menon wrote:
Looks like the following also need addressing:
data->save is called twice (once more after l2cof_init)
l2c310_init_fns also needs l2c310_configure
will be nice to use l2x0_data only after we kmemdup data in __l2c_init
I'll check this.
Thanks.
Appar
On 30.12.2014 03:23, Nishanth Menon wrote:
On 12/23/2014 04:48 AM, Marek Szyprowski wrote:
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
{
- void __iomem *base = l2x0_base;
+ unsigned revision;
- if (!(readl_relaxed(base + L2X0_CTRL) & L
Thanks a lot for investigating this, even before I could look into
splitting this.
2014-12-30 3:23 GMT+09:00 Nishanth Menon :
> On 12/23/2014 04:48 AM, Marek Szyprowski wrote:
>
>> -static void l2c310_resume(void)
>> +static void l2c310_configure(void __iomem *base)
>> {
>> - void __iomem *ba
Nishanth, Tony,
On 24.12.2014 02:13, Nishanth Menon wrote:
On 12/23/2014 11:06 AM, Tony Lindgren wrote:
* Marek Szyprowski [141223 02:51]:
From: Tomasz Figa
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to
On 10.12.2014 17:39, Vivek Gautam wrote:
USB and Power regulator on Exynos7 require gpios available
in BUS1 pin controller block.
So adding the BUS1 pinctrl support.
Signed-off-by: Naveen Krishna Ch
Signed-off-by: Vivek Gautam
Cc: Tomasz Figa
Cc: Linus Walleij
---
Changes since V2
Hi Chanwoo,
On 27.11.2014 16:34, Chanwoo Choi wrote:
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa
Cc: Thomas Abraham
Cc
Hi Andreas,
On 23.11.2014 07:26, Andreas Färber wrote:
From: Hakjoo Kim
Add Samsung EXYNOS5410 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5410.
Signed-off-by: Hakjoo Kim
[AF: Rebased onto Exynos5260 and irq_chip consolidation]
Signed-off-by: Andreas Färber
On Tue, Dec 16, 2014 at 4:53 AM, Laurent Pinchart
wrote:
> Hi Tomasz,
>
> On Monday 15 December 2014 11:39:01 Tomasz Figa wrote:
>> On Sat, Dec 13, 2014 at 5:47 AM, Laurent Pinchart wrote:
>> > On Friday 12 December 2014 13:15:51 Tomasz Figa wrote:
>> >> On Fr
On Sat, Dec 13, 2014 at 5:04 AM, Kevin Hilman wrote:
> Tomasz Figa writes:
>
> [...]
>
>> We have a power domain, which contains an IOMMU and an IP block, which
>> can do bus transactions through that IOMMU. Of course the IP block is
>> not aware of the IOMMU, becau
On Sat, Dec 13, 2014 at 5:47 AM, Laurent Pinchart
wrote:
> Hello,
>
> On Friday 12 December 2014 13:15:51 Tomasz Figa wrote:
>> On Fri, Dec 12, 2014 at 5:48 AM, Rafael J. Wysocki wrote:
>> > On Thursday, December 11, 2014 04:51:37 PM Ulf Hansson wrote:
>> >>
Hi Rafael,
On Fri, Dec 12, 2014 at 5:48 AM, Rafael J. Wysocki wrote:
> On Thursday, December 11, 2014 04:51:37 PM Ulf Hansson wrote:
>> On 11 December 2014 at 16:31, Kevin Hilman wrote:
>> > [+ Laurent Pinchart]
>> >
>> > Tomasz Figa writes:
>> &g
Hi Ulf,
On Thu, Dec 11, 2014 at 8:58 PM, Ulf Hansson wrote:
> On 11 December 2014 at 09:26, Tomasz Figa wrote:
>> This patch modifies the rockchip-iommu driver to consider state of
>> the power domain the IOMMU is located in. When the power domain
>> is powered off, the IOM
Hi Sylwester,
On Thu, Dec 11, 2014 at 7:36 PM, Sylwester Nawrocki
wrote:
>
> Hi Tomasz,
>
> On 11/12/14 09:26, Tomasz Figa wrote:
> > From: Sylwester Nawrocki
> >
> > This patch adds notifiers to the runtime PM/genpd subsystem. It is now
> > possible to regis
uses power domain notifications
to perform necessary IOMMU initialization. Race with runtime PM core
is avoided by protecting code accessing the hardware, including startup
and shutdown functions, with a spinlock with a check for power state
inside.
Signed-off-by: Tomasz Figa
---
drivers/iommu
rocki
[tf...@chromium.org: rebased]
Signed-off-by: Tomasz Figa
---
Documentation/power/notifiers.txt | 14 +++
drivers/base/power/domain.c | 50 +++
include/linux/pm_domain.h | 20
3 files changed, 84 insertions(+)
diff --
Add PM domain notifications
Tomasz Figa (1):
iommu: rockchip: Handle system-wide and runtime PM
Documentation/power/notifiers.txt | 14 +++
drivers/base/power/domain.c | 50 +
drivers/iommu/rockchip-iommu.c| 208 +++---
include/linux/pm_domain.h
Hi Vivek,
Please see my comments below.
2014-11-24 22:02 GMT+09:00 Vivek Gautam :
> USB and Power regulator on Exynos7 require gpios available
> in BUS1 pin controller block.
> So adding the BUS1 pinctrl support.
>
> Signed-off-by: Naveen Krishna Ch
> Signed-off-by: Vivek Gautam
> Cc: Linus Wal
On Fri, Nov 28, 2014 at 6:57 PM, Heiko Stübner wrote:
>
> Am Montag, 17. November 2014, 17:50:38 schrieb Caesar Wang:
> > Add power domain drivers based on generic power domain for
> > Rockchip platform, and support RK3288.
> >
> > https://chromium-review.googlesource.com/#/c/220253/9
2014-12-01 17:37 GMT+09:00 Krzysztof Kozlowski :
>
> On nie, 2014-11-30 at 21:19 +0900, Tomasz Figa wrote:
>> Hi Krzysztof,
>>
>> 2014-11-28 23:08 GMT+09:00 Krzysztof Kozlowski :
>> > On pią, 2014-11-28 at 15:04 +0100, Linus Walleij wrote:
>> >> On Wed,
Hi Krzysztof,
2014-11-28 23:08 GMT+09:00 Krzysztof Kozlowski :
> On pią, 2014-11-28 at 15:04 +0100, Linus Walleij wrote:
>> On Wed, Nov 26, 2014 at 3:24 PM, Krzysztof Kozlowski
>> wrote:
>>
>> > The audio subsystem on Exynos 5420 has separate clocks and GPIO. To
>> > operate properly on GPIOs the
Hi Andreas,
2014-11-28 21:07 GMT+09:00 Andreas Färber :
> Am 28.11.2014 um 12:59 schrieb Linus Walleij:
>> On Sat, Nov 22, 2014 at 11:26 PM, Andreas Färber wrote:
>>
>>> From: Hakjoo Kim
>>>
>>> Add Samsung EXYNOS5410 SoC specific data to enable pinctrl
>>> support for all platforms based on EXY
2014-11-27 20:45 GMT+09:00 Arnd Bergmann :
> On Thursday 27 November 2014 16:34:58 Chanwoo Choi wrote:
>> +
>> +/*
>> + * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
>> + * four gpio/pin-mux/pinconfig controllers.
>> + */
>> +struct samsung_pin_ctrl exynos5433_pin_ctrl[]
Hi Krzysztof,
Please see my comments inline.
2014-11-25 0:18 GMT+09:00 Krzysztof Kozlowski :
> +static int audss_clk_gate_enable(struct clk_hw *hw)
> +{
> + int ret;
> +
> + if (!IS_ERR(pll_in))
> + clk_prepare_enable(pll_in);
Calling clk_prepare_enable() from enable()
Hi Chanwoo,
2014-11-07 15:23 GMT+09:00 Chanwoo Choi :
> Dear Linus,
>
> Could you please review this patch?
I'll take care of this during this weekend.
Sorry for all the delays, but I was in the middle of relocation to
another country and I just didn't have enough time yet to collect all
the pat
On 24.10.2014 15:23, Daniel Drake wrote:
> On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote:
>> This patch adds new exynos4415.dtsi to support Exynos4415 SoC
>> based on Cortex-A9 quad cores and includes following dt nodes:
>
> There's a lot in common between your new exynos4415.dtsi and the
>
On 24.10.2014 15:18, Daniel Drake wrote:
> On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi wrote:
>> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
>> using common clock framework. The CMU (Clock Management Unit) of Exynos4415
>> controls PLLs(Phase Locked Loops) and gener
Hi Chanwoo,
On 24.10.2014 13:39, Chanwoo Choi wrote:
> This patch add sleep mode pin configuration using pinctrl subsystem
> to reduce leakage power-consumption of gpio pin in sleep state.
>
> Signed-off-by: Chanwoo Choi
> Acked-by: Kyungmin Park
I suspect a typo in this email address. Kukjin,
Hi Chanwoo,
On 20.10.2014 05:32, Chanwoo Choi wrote:
> This patch add Exynos4415's SoC ID. Exynos4415 is based on the 32-bit RISC
> processor for Smartphone. Exynos4415 uses Cortex A9 quad-cores and has a
> target
> speed of 1.6GHz and provides 8.5GB/s memory bandwidth.
>
> Cc: Kukjin Kim
> Sig
Hi Anton,
On 13.10.2014 06:54, Anton Tikhomirov wrote:
> Hi Vivek,
>
>> Exynos7 also has a separate special gate clock going to the IP
>> apart from the usual AHB clock. So add support for the same.
>
> As we discussed before, Exynos7 SoCs have 7 clocks to be controlled
> by the driver. Adding o
On 08.10.2014 12:23, Linus Walleij wrote:
> On Thu, Oct 2, 2014 at 8:52 PM, Tomasz Figa wrote:
>
>> This series intends to clean up data structures used by pinctrl-samsung
>> driver.
>> More specifically, it separates initial compile time constants from data used
>&g
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