not affected by the change.
>
Thanks for testing!
> On 2019/06/25 16:57, Vignesh Raghavendra wrote:
>> HyperFlash devices are compliant with CFI AMD/Fujitsu Extended Command
>> Set (0x0002) for flash operations, therefore
>> drivers/mtd/chips/cfi_cmdset_0002.c can be used as
probe.
>>
>> HyperRAM is not supported at the moment.
>>
>> HyperBus specification can be found at[1]
>> HyperFlash datasheet can be found at[2]
>>
>> [1] https://www.cypress.com/file/213356/download
>> [2] https://www.cypress.com/file/213346/download
Add binding documentation for TI's HyperBus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh Raghavendra
---
v8:
Fix white space issues
.../devicetree/bindings/mtd/ti,am654-hbmc.txt | 51 +++
MAINTAINERS | 1 +
2 files changed
Add driver for HyperBus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.
Add basic support for the IP without DMA. Second chipSelect is not
supported for now.
Signed-off-by: Vignesh Raghavendra
---
v8
ile/213346/download
[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Signed-off-by: Vignesh Raghavendra
---
v8:
Fix documentation comments on core APIs
MAINTAINERS | 7 ++
drivers/mtd/Kconfig | 2 +
driv
supported.
Print error messages on erase/program failure by looking at related
Status Register bits.
[1] https://www.cypress.com/file/213346/download
Signed-off-by: Vignesh Raghavendra
---
v8:
Fix up status register polling to support banked flashes in patch 1/5.
drivers/mtd/chips/cfi_cmdset_00
Add DT binding documentation for HyperFlash devices.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Rob Herring
---
v8:
No changes
.../devicetree/bindings/mtd/cypress,hyperflash.txt | 13 +
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings
datasheet can be found at[2]
TI's HBMC controller details at[3]
[1] https://www.cypress.com/file/213356/download
[2] https://www.cypress.com/file/213346/download
[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Vignesh Raghavendra (5):
mtd: cfi_cmd
Hi,
On 24/06/19 10:16 PM, Tokunori Ikegami wrote:
>
[...]
>> +/*
>> + * Use status register to poll for Erase/write completion when DQ is not
>> + * supported. This is indicated by Bit[1:0] of SoftwareFeatures field in
>> + * CFI Primary Vendor-Specific Extended Query table 1.5
>> + */
>>
On 22/06/19 1:22 AM, Sergei Shtylyov wrote:
> Hello!
>
> On 06/20/2019 08:22 PM, Vignesh Raghavendra wrote:
>
>> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate
>> Bus interface between a host system master and one or more slave
>>
On 24/06/19 6:10 PM, Sagar Kadam wrote:
> Hello Vignesh,
>
> On Mon, Jun 24, 2019 at 3:04 PM Vignesh Raghavendra wrote:
>>
>> Hi,
>>
>> On 21/06/19 3:58 PM, Sagar Kadam wrote:
>>> Hello Vignesh,
>>>
>>> On Fri, Jun 21, 20
ess.
>> So we should fix it.
>
> It's better to be imperative. Substitute "So we should fix it" with something
> like "Use a post bfpt fixup hook to overwrite the address width advertised by
> the BFPT".
>
>>
>
> We'll need a fixes tag here.> S
Hi,
On 21/06/19 3:58 PM, Sagar Kadam wrote:
> Hello Vignesh,
>
> On Fri, Jun 21, 2019 at 11:33 AM Vignesh Raghavendra wrote:
>>
>> Hi,
>>
>> On 17/06/19 8:48 PM, Sagar Kadam wrote:
>>> Hello Vignesh,
>>>
>>> Thanks for your revi
Hi,
On 17/06/19 8:48 PM, Sagar Kadam wrote:
> Hello Vignesh,
>
> Thanks for your review comments.
>
> On Sun, Jun 16, 2019 at 6:14 PM Vignesh Raghavendra wrote:
>>
>> Hi,
>>
>> On 12-Jun-19 4:17 PM, Sagar Shrikant Kadam wrote:
>> [...]
>>
Add DT binding documentation for HyperFlash devices.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Rob Herring
---
v7: No change
.../devicetree/bindings/mtd/cypress,hyperflash.txt | 13 +
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd
Add driver for HyperBus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.
Add basic support for the IP without DMA. Second chipSelect is not
supported for now.
Signed-off-by: Vignesh Raghavendra
---
v7
Add binding documentation for TI's HyperBus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh Raghavendra
---
v7: Fix example to move HyperBus node out of syscon
v6: Use generic names for bindings
.../devicetree/bindings/mtd/ti,am654-hbmc.txt | 52 +++
MAINTAINERS
oad
[2] https://www.cypress.com/file/213346/download
[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Vignesh Raghavendra (5):
mtd: cfi_cmdset_0002: Add support for polling status register
dt-bindings: mtd: Add binding documentation for HyperFla
346/download
[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Signed-off-by: Vignesh Raghavendra
---
v7: No change
v6:
Clarify read16()/write16() APIs
Move calibration code out into TI specific driver
MAINTAINERS | 7 ++
driv
supported.
Print error messages on erase/program failure by looking at related
Status Register bits.
[1] https://www.cypress.com/file/213346/download
Signed-off-by: Vignesh Raghavendra
---
v7: No change
drivers/mtd/chips/cfi_cmdset_0002.c | 90 +
include/linux
Add binding documentation for TI's HyperBus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh Raghavendra
---
v6:
Use generic names for bindings
.../devicetree/bindings/mtd/ti,am654-hbmc.txt | 51 +++
MAINTAINERS | 1 +
2 files
Add DT binding documentation for HyperFlash devices.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Rob Herring
---
v6: No change
.../devicetree/bindings/mtd/cypress,hyperflash.txt | 13 +
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings
Add driver for HyperBus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.
Add basic support for the IP without DMA. Second chipSelect is not
supported for now.
Signed-off-by: Vignesh Raghavendra
---
v6: Move
supported.
Print error messages on erase/program failure by looking at related
Status Register bits.
[1] https://www.cypress.com/file/213346/download
Signed-off-by: Vignesh Raghavendra
---
v6: no change
drivers/mtd/chips/cfi_cmdset_0002.c | 90 +
include/linux
Table 12-5741. HyperFlash Access Sequence
Vignesh Raghavendra (5):
mtd: cfi_cmdset_0002: Add support for polling status register
dt-bindings: mtd: Add binding documentation for HyperFlash
mtd: Add support for HyperBus memory devices
dt-bindings: mtd: Add bindings for TI's AM654 HyperBus memory
ttp://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Signed-off-by: Vignesh Raghavendra
---
v6:
Clarify read16()/write16() APIs
Move calibration code out into TI specific driver
MAINTAINERS | 7 ++
drivers/mtd/Kcon
On 18/06/19 1:15 AM, Sergei Shtylyov wrote:
> Hello!
>
> On 06/11/2019 02:57 PM, Vignesh Raghavendra wrote:
>
>>>> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate
>>>> Bus interface between a host system master and one or more sla
+Uwe who had interest in 4bit block protection support
On 12-Jun-19 4:17 PM, Sagar Shrikant Kadam wrote:
> Implement a locking scheme for ISSI devices based on stm_lock mechanism.
> The is25x devices have 4 bits for selecting the range of blocks to
> be locked/protected from erase/write
On 11/06/19 5:27 PM, Vignesh Raghavendra wrote:
>
>
> On 10/06/19 11:27 PM, Sergei Shtylyov wrote:
>> On 06/09/2019 01:32 PM, Vignesh Raghavendra wrote:
>>
>>> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate
>>> Bus interfa
Hi,
On 10/06/19 9:55 PM, Sergei Shtylyov wrote:
> Hello!
>
> On 06/09/2019 01:32 PM, Vignesh Raghavendra wrote:
>
>> Add binding documentation for TI's HyperBus memory controller present on
>> AM654 SoC.
>>
>> Signed-off-by: Vignesh Raghavendra
>> --
On 12-Jun-19 4:17 PM, Sagar Shrikant Kadam wrote:
> Nor device (is25wp256 mounted on HiFive unleashed Rev A00 board) from ISSI
> have memory blocks guarded by block protection bits BP[0,1,2,3].
>
> Clearing block protection bits,unlocks the flash memory regions
> The unlock scheme is
Hi,
On 12-Jun-19 4:17 PM, Sagar Shrikant Kadam wrote:
[...]
> @@ -4129,7 +4137,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
> if (ret)
> return ret;
>
> - if (nor->addr_width) {
> + if (nor->addr_width && JEDEC_MFR(info) != SNOR_MFR_ISSI) {
>
arger chips.
>>
>> Tested with Spansion S29GL01GS11TFI flash device.
>>
>> Signed-off-by: Chris Packham
Acked-by: Vignesh Raghavendra
Regards
Vignesh
>> ---
>> drivers/mtd/chips/cfi_cmdset_0002.c | 13 -
>> 1 file changed, 8 insertions(+), 5
set
> in the bootloader. When this bit is set, only the Write Register
> WRR command format with 16 data bits may be used, WRR with 8 bits
> is not recognized and hence the error when trying to clear the block
> protection bits.
>
I see above text in s25fl512s datasheet[1] as wel
On 10/06/19 11:27 PM, Sergei Shtylyov wrote:
> On 06/09/2019 01:32 PM, Vignesh Raghavendra wrote:
>
>> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate
>> Bus interface between a host system master and one or more slave
>> interfaces. Hyp
Add binding documentation for TI's HyperBus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh Raghavendra
---
v5:
Update binding example to show MMIO mux
Fix reg property for flash slave.
.../devicetree/bindings/mtd/ti,am654-hbmc.txt | 51 +++
MAINTAINERS
346/download
[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Signed-off-by: Vignesh Raghavendra
---
v5: No change
MAINTAINERS | 7 +
drivers/mtd/Kconfig | 2 +
drivers/mtd/Makefile |
Add DT binding documentation for HyperFlash devices.
Signed-off-by: Vignesh Raghavendra
Reviewed-by: Rob Herring
---
v5: No change
.../devicetree/bindings/mtd/cypress,hyperflash.txt | 13 +
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd
ler and slave devices
* Rename all files and func names to have hyperbus_ prefix
* Provide default calibration routine for use by controller drivers
* Fix up errors with patch spliting
* Address comments by Sergei Shtylyov
Vignesh Raghavendra (5):
mtd: cfi_cmdset_0002: Add support for polling st
supported.
Print error messages on erase/program failure by looking at related
Status Register bits.
[1] https://www.cypress.com/file/213346/download
Signed-off-by: Vignesh Raghavendra
---
v5: No change
drivers/mtd/chips/cfi_cmdset_0002.c | 90 +
include/linux
Add driver for HyperBus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.
Add basic support for the IP without DMA. Second chipSelect is not
supported for now.
Signed-off-by: Vignesh Raghavendra
---
v5:
Drop
From: Peter Ujfalusi
J721E SoCs have same I2C IP as OMAP SoCs. Add new compatible to
handle J721E SoCs.
Signed-off-by: Peter Ujfalusi
Signed-off-by: Vignesh Raghavendra
---
Initial support for J721E Platform is proposed here:
https://lore.kernel.org/patchwork/cover/1077382/
Documentation
On 15/05/19 6:28 AM, Grygorii Strashko wrote:
> Hi Greg,
>
> On 15.05.19 13:55, Greg Kroah-Hartman wrote:
>> [ Upstream commit 5b277402deac0691226a947df71c581686bd4020 ]
>>
>> Allow I2C_OMAP to be built for K3 platforms.
>>
>> Signed-off-by: Vignesh R
>> Reviewed-by: Grygorii Strashko
>>
On 27/04/19 1:50 AM, Rob Herring wrote:
> On Tue, Apr 23, 2019 at 04:18:13PM +0530, Vignesh Raghavendra wrote:
>> Add binding documentation for TI's HyperBus memory controller present on
>> AM654 SoC.
>>
>> Signed-off-by: Vignesh Raghavendra
>> ---
>>
supported.
Print error messages on erase/program failure by looking at related
Status Register bits.
[1] https://www.cypress.com/file/213346/download
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/chips/cfi_cmdset_0002.c | 90 +
include/linux/mtd/cfi.h
Add DT binding documentation for HyperFlash devices.
Signed-off-by: Vignesh Raghavendra
---
.../devicetree/bindings/mtd/cypress,hyperflash.txt | 13 +
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt
diff --git
346/download
[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Signed-off-by: Vignesh Raghavendra
---
MAINTAINERS | 7 +
drivers/mtd/Kconfig | 2 +
drivers/mtd/Makefile | 1 +
drivers/
Add driver for HyperBus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.
Add basic support for the IP without DMA. Second chipSelect is not
supported for now.
Signed-off-by: Vignesh Raghavendra
---
drivers
erbus_ prefix
* Provide default calibration routine for use by controller drivers
* Fix up errors with patch spliting
* Address comments by Sergei Shtylyov
Vignesh Raghavendra (5):
mtd: cfi_cmdset_0002: Add support for polling status register
dt-bindings: mtd: Add binding documentation for Hyp
Add binding documentation for TI's HyperBus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh Raghavendra
---
.../devicetree/bindings/mtd/ti,am654-hbmc.txt | 32 +++
MAINTAINERS | 1 +
2 files changed, 33 insertions(+)
create mode
On 23/04/19 11:36 AM, Vignesh Raghavendra wrote:
>
>
> Vignesh Raghavendra (5):
> mtd: cfi_cmdset_0002: Add support for polling status register
> dt-bindings: mtd: Add binding documentation for HyperFlash
> mtd: Add support for HyperBus memory devices
> dt-bindin
346/download
[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Signed-off-by: Vignesh Raghavendra
---
MAINTAINERS | 7 +
drivers/mtd/Kconfig | 2 +
drivers/mtd/Makefile | 1 +
drivers/
Add DT binding documentation for HyperFlash devices.
Signed-off-by: Vignesh Raghavendra
---
.../devicetree/bindings/mtd/cypress,hyperflash.txt | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt
diff --git
supported.
Print error messages on erase/program failure by looking at related
Status Register bits.
[1] https://www.cypress.com/file/213346/download
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/chips/cfi_cmdset_0002.c | 90 +
include/linux/mtd/cfi.h
Add binding documentation for TI's HyperBus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh Raghavendra
---
.../devicetree/bindings/mtd/ti,am654-hbmc.txt | 31 +++
MAINTAINERS | 1 +
2 files changed, 32 insertions(+)
create mode
Add driver for HyperBus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.
Add basic support for the IP without DMA. Second chipSelect is not
supported for now.
Signed-off-by: Vignesh Raghavendra
---
drivers
rs with patch spliting
* Address comments by Sergei Shtylyov
Vignesh Raghavendra (5):
mtd: cfi_cmdset_0002: Add support for polling status register
dt-bindings: mtd: Add binding documentation for HyperFlash
mtd: Add support for HyperBus memory devices
dt-bindings: mtd: Add bindings for TI's A
Hi Sergei,
On 12/04/19 2:59 PM, Vignesh Raghavendra wrote:
Vignesh Raghavendra (5):
mtd: cfi_cmdset_0002: Add support for polling status register
dt-bindings: mtd: Add binding documentation for HyperFlash
mtd: Add support for HyperBus memory devices
dt-bindings: mtd: Add bindings
Hi,
On 14/04/19 11:21 PM, Sergei Shtylyov wrote:
> Hello!
>
> On 04/12/2019 12:29 PM, Vignesh Raghavendra wrote:
>
>> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate
>> Bus interface between a host system master and one or more slave
>>
On 14/04/19 11:25 PM, Sergei Shtylyov wrote:
> On 04/12/2019 12:29 PM, Vignesh Raghavendra wrote:
>
>> Add binding documentation for TI's HyperBus memory controller present on
>> AM654 SoC.
>>
>> Signed-off-by: Vignesh Raghavendra
>> ---
>> .../devi
Hi Tudor,
On 15/04/19 1:43 PM, tudor.amba...@microchip.com wrote:
> Hi,
>
> The general approach looks good, few comments below.
>
> On 04/09/2019 07:26 PM, Vignesh Raghavendra wrote:
>> External E-Mail
>>
>>
>> From: Boris Brezillon
>>
>> The
Add driver for HyperBus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.
Add basic support for the IP without DMA. Second chipSelect is not
supported for now.
Signed-off-by: Vignesh Raghavendra
---
drivers
346/download
[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Signed-off-by: Vignesh Raghavendra
---
MAINTAINERS | 7 +
drivers/mtd/Kconfig | 2 +
drivers/mtd/Makefile | 1 +
drivers/
Add binding documentation for TI's HyperBus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh Raghavendra
---
.../devicetree/bindings/mtd/ti,am654-hbmc.txt | 31 +++
MAINTAINERS | 1 +
2 files changed, 32 insertions(+)
create mode
supported.
Print error messages on erase/program failure by looking at related
Status Register bits.
[1] https://www.cypress.com/file/213346/download
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/chips/cfi_cmdset_0002.c | 90 +
include/linux/mtd/cfi.h
Add DT binding documentation for HyperFlash devices.
Signed-off-by: Vignesh Raghavendra
---
.../devicetree/bindings/mtd/cypress,hyperflash.txt | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt
diff --git
rs with patch spliting
* Address comments by Sergei Shtylyov
Vignesh Raghavendra (5):
mtd: cfi_cmdset_0002: Add support for polling status register
dt-bindings: mtd: Add binding documentation for HyperFlash
mtd: Add support for HyperBus memory devices
dt-bindings: mtd: Add bindings for TI's A
by the MTD layer.
Signed-off-by: Boris Brezillon
[vigne...@ti.com: use devm_kmalloc() for bounce buffer allocation]
Signed-off-by: Vignesh Raghavendra
---
Changes from RFC:
* Use devm_kmalloc() for bounce buffer allocation as it supports cache
line aligned buffers now
* Rebase onto latest next
* Fix
On 08/04/19 8:09 PM, Yue Haibing wrote:
> From: YueHaibing
>
> When building with CONFIG_SPI_MEM is not set
> gc warns this:
>
> drivers/spi/spi-zynq-qspi.o: In function `zynq_qspi_supports_op':
> spi-zynq-qspi.c:(.text+0x1da): undefined reference to
> `spi_mem_default_supports_op'
>
> Fixes:
spi_mem_supports_op() when
nor->spimem != NULL.
Signed-off-by: Boris Brezillon
Signed-off-by: Vignesh Raghavendra
---
Chagnes wrt RFC:
Fix checkpatch issues
Rebase onto latest
drivers/mtd/spi-nor/spi-nor.c | 164 ++
include/linux/mtd/spi-nor.h | 14 +++
2 fi
This is repost of patch 6 and 7 split from from Boris Brezillon's X-X-X
mode support series[1]
Background from cover letter for RFC[1]:
m25p80 is just a simple SPI NOR controller driver (a wrapper around the
SPI mem API). Not only it shouldn't be named after a specific SPI NOR
chip, but it also
On 08/04/19 10:20 PM, Dinh Nguyen wrote:
> Get the reset control for the QSPI controller and bring it out of reset.
>
> Suggested-by: Tien-Fong Chee
> Signed-off-by: Dinh Nguyen
> ---
> drivers/mtd/spi-nor/cadence-quadspi.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git
Hi Rob,
On 28/03/19 6:01 PM, Rob Herring wrote:
> On Tue, Mar 12, 2019 at 02:35:17PM +0530, Vignesh Raghavendra wrote:
>> Add dt bindings for TI syscon gate clock.
>>
>> Signed-off-by: Vignesh Raghavendra
>> ---
>> .../bindings/clock/ti,syscon-gate-clock.txt
On 05/04/19 10:55 AM, Naga Sureshkumar Relli wrote:
> Hi Vignesh,
>
> Thanks for the review.
>
>> -Original Message-
>> From: Vignesh Raghavendra
>> Sent: Friday, April 5, 2019 10:14 AM
>> To: Naga Sureshkumar Relli ; broo...@kernel.org;
&
On 01/04/19 1:29 PM, Naga Sureshkumar Relli wrote:
> +/**
> + * zynq_qspi_config_op - Configure QSPI controller for specified transfer
> + * @xqspi: Pointer to the zynq_qspi structure
> + * @qspi:Pointer to the spi_device structure
> + *
> + * Sets the operational mode of QSPI controller
On 25/03/19 10:54 PM, Joakim Tjernlund wrote:
> On Mon, 2019-03-25 at 22:36 +0530, Vignesh Raghavendra wrote:
>>
>> On 25/03/19 7:21 PM, Joakim Tjernlund wrote:
>>> On Mon, 2019-03-25 at 18:27 +0530, Vignesh Raghavendra wrote:
>>>> CAUTION: This email origina
Hi,
On 01/04/19 10:19 AM, Andrey Smirnov wrote:
> Spi_nor_read() already has an appropriate loop around .read() callback
> to handle the case when not all of the data requested was written in a
> signle ->read() call. Drop extra code doing the same thing in
> m25p80_read().
>
Thanks for the
On 29/03/19 2:23 PM, Boris Brezillon wrote:
> On Fri, 29 Mar 2019 13:50:26 +0530
> Vignesh Raghavendra wrote:
>
>> Hi Boris,
>>
>> On 29/03/19 1:25 AM, Boris Brezillon wrote:
>>> On Thu, 28 Mar 2019 16:46:24 +0530
>>> Naga Sureshkumar Relli wrote:
n
> dual, quad or octal mode).
> Just call spi_mem_default_supports_op() from your driver
> ->supports_op() hook if needed.
>
Could you rework to follow Boris's suggestion here?
>>
>> Suggested-by: Vignesh Raghavendra
>> Signed-off-by: Naga Sureshkumar Relli
>> ---
>> Deta
ts_op()
in the case you mentioned. Or did I miss something? Maybe something SPI
NAND specific?
Regards
Vignesh
> Just call spi_mem_default_supports_op() from your driver
> ->supports_op() hook if needed.
>
>>
>> Suggested-by: Vignesh Raghavendra
>> Signed-off-by: Naga S
On 26/03/19 8:50 PM, Liu Xiang wrote:
> At 2019-03-19 13:22:15, "Vignesh Raghavendra" wrote:
>> Hi,
>>
>> On 13/03/19 7:15 PM, Liu Xiang wrote:
>>> In some is25lp256, the DWORD1 of JEDEC Basic Flash Parameter Header
>>> is 0xfff920e5. So the DWO
On 25/03/19 7:21 PM, Joakim Tjernlund wrote:
> On Mon, 2019-03-25 at 18:27 +0530, Vignesh Raghavendra wrote:
>> CAUTION: This email originated from outside of the organization. Do not
>> click links or open attachments unless you recognize the sender and know the
>
Hi,
On 24/03/19 9:48 PM, Sergei Shtylyov wrote:
> Hello!
>
> On 03/21/2019 08:45 PM, Vignesh Raghavendra wrote:
>
>> Add DT binding documentation for Hyperbus memory devices. Only
>> Hyperflash is supported at the moment.
>>
>> Signed-off-by: Vignesh R
Hi,
On 21/03/19 11:41 PM, Joakim Tjernlund wrote:
> On Thu, 2019-03-21 at 23:15 +0530, Vignesh Raghavendra wrote:
>>
>> HyperFlash devices are compliant with CFI AMD/Fujitsu Extended Command
>> Set(0x0002) for flash operations, therefore
>> drivers/mtd/chips/cfi_
Add driver for Hyperbus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.
Add basic support for the IP without DMA. Second ChipSelect is not
supported for now.
Signed-off-by: Vignesh Raghavendra
---
drivers
346/download
[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Signed-off-by: Vignesh Raghavendra
---
MAINTAINERS | 7 +
drivers/mtd/Kconfig | 2 +
drivers/mtd/Makefile | 1 +
drivers/
Add binding documentation for TI's Hyperbus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh Raghavendra
---
.../devicetree/bindings/mtd/ti,am654-hbmc.txt | 27 +++
MAINTAINERS | 1 +
2 files changed, 28 insertions(+)
create mode
Add DT binding documentation for Hyperbus memory devices. Only
Hyperflash is supported at the moment.
Signed-off-by: Vignesh Raghavendra
---
Documentation/devicetree/bindings/mtd/cypress,hyperbus.txt | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 Documentation/devicetree
orted.
[1] https://www.cypress.com/file/213346/download
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/chips/cfi_cmdset_0002.c | 50 +
include/linux/mtd/cfi.h | 5 +++
2 files changed, 55 insertions(+)
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c
tch spliting
* Address comments by Sergei Shtylyov
Vignesh Raghavendra (5):
mtd: cfi_cmdset_0002: Add support for polling status register
dt-bindings: mtd: Add binding documentation for Hyperbus memory
devices
mtd: Add support for Hyperbus memory devices
dt-bindings: mtd: Add bindi
Hi,
Few more comments that I missed last time around.
On 28/02/19 12:32 PM, Naga Sureshkumar Relli wrote:
> Add support for QSPI controller driver used by Xilinx Zynq SOC.
>
> Signed-off-by: Naga Sureshkumar Relli
> ---
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile|
Hi,
On 12/03/19 3:00 PM, Uwe Kleine-König wrote:
> On Tue, Mar 12, 2019 at 02:46:29PM +0530, Vignesh Raghavendra wrote:
>> K3 devices have the same EHRPWM IP as OMAP SoCs. Enable driver to be built
>> for K3 devices. Also, drop reference to AM33xx in help text, as IP is
>>
Hi,
On 13/03/19 7:15 PM, Liu Xiang wrote:
> In some is25lp256, the DWORD1 of JEDEC Basic Flash Parameter Header
> is 0xfff920e5. So the DWORD1[18:17] Address Bytes bits are 0b00,
> means that 3-Byte only addressing. But the device size is larger
> than 16MB, nor->addr_width must be 4 to access
Hi,
On 11/03/19 10:02 AM, Naga Sureshkumar Relli wrote:
> Hi Vignesh,
>
>> -Original Message-
>> From: linux-spi-ow...@vger.kernel.org On
>> Behalf Of
>> Vignesh Raghavendra
>> Sent: Friday, March 8, 2019 10:20 AM
>> To: Naga Sureshku
Add a new compatible string "ti,am654-ehrpwm" to support EHRPWM IP on
TI AM654 SoC.
Signed-off-by: Vignesh Raghavendra
---
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehr
K3 devices have the same EHRPWM IP as OMAP SoCs. Enable driver to be built
for K3 devices. Also, drop reference to AM33xx in help text, as IP is
found on multiple TI SoCs.
Signed-off-by: Vignesh Raghavendra
---
drivers/pwm/Kconfig | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff
This series adds support for EHRPWM IP on TI AM654 SoC
Vignesh Raghavendra (2):
dt-bindings: pwm: tiehrpwm: Add TI AM654 SoC specific compatible
pwm: Kconfig: Enable ehrpwm driver to be compiled for ARCH_K3
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt | 1 +
drivers/pwm/Kconfig
as desired.
Fixes: 38dabd91ff0b ("pwm: tiehrpwm: Fix disabling of output of PWMs")
Signed-off-by: Christoph Vogtländer
[vigne...@ti.com: Improve commit message]
Signed-off-by: Vignesh Raghavendra
---
drivers/pwm/pwm-tiehrpwm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drive
. Each clock node will be child of the
syscon node.
Signed-off-by: Vignesh Raghavendra
---
drivers/clk/keystone/Kconfig | 8 ++
drivers/clk/keystone/Makefile | 1 +
drivers/clk/keystone/syscon-clk.c | 143 ++
3 files changed, 152 insertions(+)
create mode
Add dt bindings for TI syscon gate clock.
Signed-off-by: Vignesh Raghavendra
---
.../bindings/clock/ti,syscon-gate-clock.txt | 35 +++
1 file changed, 35 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt
diff --git
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