[PATCH] input: i8042: add quirk to implement i8042 detect for AMD

Detecting platform supports i8042 or not, AMD resorted to BIOS's FADT i8042 flag. Signed-off-by: Vincent Wan --- drivers/input/serio/i8042-x86ia64io.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h index

[PATCH] input: i8042: add quirk to implement i8042 detect for AMD

Detecting platform supports i8042 or not, AMD resorted to BIOS's FADT i8042 flag. Signed-off-by: Vincent Wan <vincent@amd.com> --- drivers/input/serio/i8042-x86ia64io.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input

[PATCH v3 2/3] mmc:sdhci-pci: enable the clear transfer mode register quirk for AMD sdhci

This patch is to enable the quirk for AMD sdhci requiring transfer mode register need to be cleared for commands without data Signed-off-by: Vincent Wan Signed-off-by: Wan Zongshun --- drivers/mmc/host/sdhci-pci.c | 27 ++- 1 file changed, 26 insertions(+), 1 deletion

[PATCH v3 3/3] mmc:sdhci-pci: enable sdhci doesn't support hs200 quirk for AMD sdhci

AMD SD controller supports the SDR104 mode, but caps2 can not be promoted to support hs200 for eMMC. Signed-off-by: Vincent Wan Signed-off-by: Wan Zongshun --- drivers/mmc/host/sdhci-pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci.c b

[PATCH v3 1/3] mmc:sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms Signed-off-by: Vincent Wan Signed-off-by: Wan Zongshun Signed-off-by: Arindam Nath Tested-by: Vikram B Tested

[PATCH] mmc: Add a quirk for AMD SD controller doesn't support HS200

AMD SD controller support the SDR104 mode, but caps2 can not be promoted to support hs200 for eMMC. Signed-off-by: Vincent Wan --- drivers/mmc/host/sdhci-pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c

Re: [PATCH] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

On 2014年11月04日 15:51, Ulf Hansson wrote: On 30 October 2014 05:06, Vincent Wan wrote: SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms. Signed-off-by: Vincent

[PATCH v2] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms. Signed-off-by: Vincent Wan Signed-off-by: Arindam Nath Cc: Huang Rui Tested-by: Vikram B Tested

[PATCH v2] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms. Signed-off-by: Vincent Wan vincent@amd.com Signed-off-by: Arindam Nath arindam.n...@amd.com Cc: Huang Rui

Re: [PATCH] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

On 2014年11月04日 15:51, Ulf Hansson wrote: On 30 October 2014 05:06, Vincent Wan vincent@amd.com wrote: SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms

[PATCH] mmc: Add a quirk for AMD SD controller doesn't support HS200

AMD SD controller support the SDR104 mode, but caps2 can not be promoted to support hs200 for eMMC. Signed-off-by: Vincent Wan vincent@amd.com --- drivers/mmc/host/sdhci-pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc

[PATCH v3 1/3] mmc:sdhci: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms Signed-off-by: Vincent Wan vincent@amd.com Signed-off-by: Wan Zongshun mcuos@gmail.com Signed-off

[PATCH v3 3/3] mmc:sdhci-pci: enable sdhci doesn't support hs200 quirk for AMD sdhci

AMD SD controller supports the SDR104 mode, but caps2 can not be promoted to support hs200 for eMMC. Signed-off-by: Vincent Wan vincent@amd.com Signed-off-by: Wan Zongshun mcuos@gmail.com --- drivers/mmc/host/sdhci-pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff

[PATCH v3 2/3] mmc:sdhci-pci: enable the clear transfer mode register quirk for AMD sdhci

This patch is to enable the quirk for AMD sdhci requiring transfer mode register need to be cleared for commands without data Signed-off-by: Vincent Wan vincent@amd.com Signed-off-by: Wan Zongshun mcuos@gmail.com --- drivers/mmc/host/sdhci-pci.c | 27 ++- 1 file

[PATCH] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms. Signed-off-by: Vincent Wan Signed-off-by: Arindam Nath Tested-by: Vikram B Tested-by: Raghavendra Swamy

[PATCH] mmc: Add a quirk for AMD SDHC transfer mode register need to be cleared for cmd without data

SDHC controller in AMD chipsets require SDHC transfer mode register to be cleared for commands without data. The issue was uncovered during testing eMMC cards on KB/ML based platforms. Signed-off-by: Vincent Wan vincent@amd.com Signed-off-by: Arindam Nath arindam.n...@amd.com Tested