RE: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Nicolas, > -Original Message- > From: Nicolas Dufresne > Sent: Wednesday, August 26, 2020 7:40 PM > To: Laurent Pinchart ; Vishal Sagar > ; Hans Verkuil > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; lin

RE: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Hyun, Thanks for the review. Please see my comments. > -Original Message- > From: Hyun Kwon > Sent: Thursday, July 16, 2020 4:13 AM > To: Vishal Sagar > Cc: laurent.pinch...@ideasonboard.com; hverk...@xs4all.nl; > mche...@kernel.org; robh...@kernel.org; mark.rutl.

RE: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Hans, Thanks for the review. Please see my comments below. > -Original Message- > From: Hans Verkuil > Sent: Thursday, June 25, 2020 3:13 PM > To: Vishal Sagar ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org; mark.rutl.

RE: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Laurent, Thanks for the review! Please see my comments below. > -Original Message- > From: Laurent Pinchart > Sent: Thursday, July 16, 2020 3:03 AM > To: Vishal Sagar > Cc: Hans Verkuil ; Hyun Kwon ; > mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.c

RE: [PATCH v3 2/3] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem

Hi Laurent and Rob, Thanks for reviewing this patch. > -Original Message- > From: Laurent Pinchart > Sent: Wednesday, July 15, 2020 9:59 PM > To: Vishal Sagar > Cc: Rob Herring ; Hyun Kwon ; > hverk...@xs4all.nl; mche...@kernel.org; mark.rutl...@arm.com; Michal

[PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

parameters based on the ST352 packet embedded in the stream. In case the ST352 packet isn't present in the stream, the core's detected properties are used to set stream properties. The driver currently supports only the AXI4-Stream IP configuration. Signed-off-by: Vishal Sagar --- v3 - fixed

[PATCH v3 0/3] Add support for Xilinx UHD-SDI Receiver subsystem

masking and shifting as per Joe Perches comments - Updated to latest as per Xilinx github repo driver like adding new DV timings not in mainline yet uptill 03/21/20 Vishal Sagar (3): v4l2-dv-timings: Add timings for 1920x1080P48 and 4KP48 media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI R

[PATCH v3 2/3] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem

. Signed-off-by: Vishal Sagar --- v3 - bpc instead of bpp - removed bpc as required property (default to 10 bpc) - add dt-bindings/media/xilinx-sdi.h - made line-rate as u32 instead of string - fixed reg - fixed s/upto/up to/ v2 - Removed references to xlnx,video* - Fixed as per Sakari Ailus and Rob

[PATCH v3 1/3] v4l2-dv-timings: Add timings for 1920x1080P48 and 4KP48

Add the timing entry for 1920x1080p48, 3840x2160p48 and 4096x2160p48 from CTA-861-G. 1920x1080p48 is VIC 111. 3840x2160P48 is VIC 114. 4096x2160P48 is VIC 115. Signed-off-by: Vishal Sagar --- v3 - Added for first time include/uapi/linux/v4l2-dv-timings.h | 31 +++- 1

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Hyun, Thanks for the review. > -Original Message- > From: Hyun Kwon > Sent: Thursday, May 7, 2020 12:13 AM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Laurent Thanks for the review. > -Original Message- > From: Laurent Pinchart > Sent: Wednesday, May 6, 2020 8:42 PM > To: Vishal Sagar > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; linux-me...@vger.

RE: [PATCH v14 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Laurent, > -Original Message- > From: Laurent Pinchart > Sent: Sunday, June 7, 2020 7:10 AM > To: Vishal Sagar > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; linux-me...@vger.kernel.org; > devicet...@vg

RE: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem

Hi Laurent, Thanks for the review. > -Original Message- > From: Laurent Pinchart > Sent: Wednesday, May 6, 2020 6:32 PM > To: Vishal Sagar > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; linux-me...@vger.

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Hans, Thanks for reviewing! > -Original Message- > From: Hans Verkuil > Sent: Wednesday, May 6, 2020 3:25 PM > To: Vishal Sagar ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Please ignore this email .. > -Original Message- > From: Vishal Sagar > Sent: Monday, June 1, 2020 8:12 PM > To: Hans Verkuil ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; linux-

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Hans, Thanks for reviewing! > -Original Message- > From: Hans Verkuil > Sent: Wednesday, May 6, 2020 3:25 PM > To: Vishal Sagar ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal

RE: [PATCH v14 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Laurent, > -Original Message- > From: Laurent Pinchart > Sent: Wednesday, May 27, 2020 9:42 PM > To: Vishal Sagar > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; linux-me...@vger.kernel.org; > devicet...@vg

RE: [PATCH v13 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Laurent, > -Original Message- > From: Laurent Pinchart > Sent: Wednesday, May 27, 2020 6:54 PM > To: Vishal Sagar > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; linux-me...@vger.kernel.org; > devicet...@vg

[PATCH v14 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

10bpc, RAW16, RAW20 are supported when the CSI v2.0 feature is enabled in design. When the VCX feature is enabled, the maximum number of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon Reviewed-by: Laurent Pinchart Reviewed-by: Luca Ceresoli --- v14

[PATCH v14 0/2] Add support for Xilinx CSI2 Receiver Subsystem

te DPHY PHY driver. - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra virtual channels - Fixed the ports as sink and source - Now use the v4l2fwnode API to get number of data-lanes - Added clock framework support - Removed the close() function - updated the set for

[PATCH v14 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem. The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a D-PHY in Rx mode and a Video Format Bridge. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon Reviewed-by: Rob Herring Reviewed-by: Luca Ceresoli Reviewed

RE: [PATCH v13 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Laurent, Thanks for reviewing this patch. > -Original Message- > From: Laurent Pinchart > Sent: Sunday, May 24, 2020 7:57 AM > To: Vishal Sagar > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; linux-me...@vger.

RE: [PATCH v13 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Laurent, Thanks for reviewing this series. > -Original Message- > From: Laurent Pinchart > Sent: Sunday, May 24, 2020 7:32 AM > To: Vishal Sagar > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; linux-me...@vger.

RE: [PATCH v12 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Laurent, > -Original Message- > From: Laurent Pinchart > Sent: Sunday, May 24, 2020 7:16 AM > To: Vishal Sagar > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; hans.verk...@cisco.com; Luca > Ceresoli ; Jacopo Mondi ; >

RE: [PATCH v13 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Luca, Thanks for reviewing! > -Original Message- > From: Luca Ceresoli > Sent: Monday, May 25, 2020 6:44 PM > To: Vishal Sagar ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal

[PATCH v13 0/2] Add support for Xilinx CSI2 Receiver Subsystem

Fixed the ports as sink and source - Now use the v4l2fwnode API to get number of data-lanes - Added clock framework support - Removed the close() function - updated the set format function - Support only VFB enabled config Vishal Sagar (2): media: dt-bindings: media: xilinx: Add Xilinx MIPI CS

[PATCH v13 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

10bpc, RAW16, RAW20 are supported when the CSI v2.0 feature is enabled in design. When the VCX feature is enabled, the maximum number of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon Reviewed-by: Laurent Pinchart --- v13 - Based on Laurent's suggestions

[PATCH v13 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem. The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a D-PHY in Rx mode and a Video Format Bridge. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon Reviewed-by: Rob Herring Reviewed-by: Luca Ceresoli Reviewed

RE: [PATCH v12 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Laurent, Thanks for reviewing this patch. > -Original Message- > From: Laurent Pinchart > Sent: Wednesday, May 6, 2020 4:23 AM > To: Vishal Sagar > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; hans.verk...@cisco.com; Luca > Ce

RE: [PATCH v12 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Laurent, Thanks for reviewing. > -Original Message- > From: Laurent Pinchart > Sent: Tuesday, May 5, 2020 7:53 PM > To: Vishal Sagar > Cc: Hyun Kwon ; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; hans.verk...@cisco.com; Luca > Ceresoli ; Ja

[PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

parameters based on the ST352 packet embedded in the stream. In case the ST352 packet isn't present in the stream, the core's detected properties are used to set stream properties. The driver currently supports only the AXI4-Stream IP configuration. Signed-off-by: Vishal Sagar --- v2 - Added DV

[PATCH v2 0/2] Add support for Xilinx UHD-SDI Receiver subsystem

masking and shifting as per Joe Perches comments - Updated to latest as per Xilinx github repo driver like adding new DV timings not in mainline yet uptill 03/21/20 Vishal Sagar (2): media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem media: v4l: xilinx: Add Xilinx

[PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem

. Signed-off-by: Vishal Sagar --- v2 - Removed references to xlnx,video* - Fixed as per Sakari Ailus and Rob Herring's comments - Converted to yaml format .../bindings/media/xilinx/xlnx,sdirxss.yaml | 132 ++ 1 file changed, 132 insertions(+) create mode 100644 Documentation

[PATCH v10 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

10bpc, RAW16, RAW20 are supported when the CSI v2.0 feature is enabled in design. When the VCX feature is enabled, the maximum number of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon --- v10 - Removed all V4L2 controls and events based on Sakari's comments

[PATCH v10 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem. The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a DPHY in Rx mode, an optional I2C controller and a Video Format Bridge. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon Reviewed-by: Rob Herring Reviewed

[PATCH v10 0/2] Add support for Xilinx CSI2 Receiver Subsystem

nes - Added clock framework support - Removed the close() function - updated the set format function - Support only VFB enabled config Vishal Sagar (2): media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem dri

RE: [PATCH v9 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Sakari, Thanks for reviewing. > -Original Message- > From: Sakari Ailus [mailto:sakari.ai...@iki.fi] > Sent: Tuesday, June 18, 2019 8:50 PM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > mche...@kernel.org; robh...@kernel.org; mark.rutl.

RE: [PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Sakari, > -Original Message- > From: Sakari Ailus [mailto:sakari.ai...@iki.fi] > Sent: Tuesday, June 18, 2019 8:29 PM > To: Vishal Sagar > Cc: Sakari Ailus ; Vishal Sagar > ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh.

RE: [PATCH v9 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Luca, Thanks for the review. > -Original Message- > From: Luca Ceresoli [mailto:l...@lucaceresoli.net] > Sent: Monday, July 01, 2019 3:15 AM > To: Vishal Sagar ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org; mark.rutl.

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Hans, > -Original Message- > From: Hans Verkuil [mailto:hverk...@xs4all.nl] > Sent: Tuesday, June 18, 2019 5:38 PM > To: Vishal Sagar > Cc: linux-kernel@vger.kernel.org; linux-me...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; devicet...@vger.kernel

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Hans, > -Original Message- > From: Hans Verkuil [mailto:hverk...@xs4all.nl] > Sent: Saturday, June 15, 2019 1:25 PM > To: Vishal Sagar > Cc: linux-kernel@vger.kernel.org; linux-me...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; devicet...@vger.kernel

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Joe, Thanks for reviewing. > -Original Message- > From: linux-media-ow...@vger.kernel.org [mailto:linux-media- > ow...@vger.kernel.org] On Behalf Of Joe Perches > Sent: Friday, June 14, 2019 4:02 AM > To: Hyun Kwon ; Vishal Sagar > Cc: Hyun Kwon ; Laurent Pinchart

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Hyun, Thanks for reviewing the code. > -Original Message- > From: Hyun Kwon [mailto:hyun.k...@xilinx.com] > Sent: Friday, June 14, 2019 3:35 AM > To: Vishal Sagar > Cc: Hyun Kwon ; Laurent Pinchart > ; Mauro Carvalho Chehab > ; Michal Simek ; Rob Herring >

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

Hi Hans, Thanks for reviewing this patch. > -Original Message- > From: Hans Verkuil [mailto:hverk...@xs4all.nl] > Sent: Wednesday, June 05, 2019 6:28 PM > To: Vishal Sagar ; Hyun Kwon ; > Laurent Pinchart ; Mauro Carvalho > Chehab ; Michal Simek ; Rob > Herring

[PATCH v9 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

only the video format bridge enabled configuration. Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the CSI v2.0 feature is enabled in design. When the VCX feature is enabled, the maximum number of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar Reviewed-by: Hyun

[PATCH v9 0/2] Add support for Xilinx CSI2 Receiver Subsystem

rce - Now use the v4l2fwnode API to get number of data-lanes - Added clock framework support - Removed the close() function - updated the set format function - Support only VFB enabled config Vishal Sagar (2): media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem media:

[PATCH v9 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem. The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a DPHY in Rx mode, an optional I2C controller and a Video Format Bridge. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon Reviewed-by: Rob Herring Reviewed

RE: [PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Sakari, Thanks for reviewing. > -Original Message- > From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com] > Sent: Wednesday, June 05, 2019 6:19 PM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > mche...@kernel.org; robh...@ker

RE: [PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Hans, Thanks for reviewing. > -Original Message- > From: Hans Verkuil [mailto:hverk...@xs4all.nl] > Sent: Wednesday, June 05, 2019 6:14 PM > To: Vishal Sagar ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm

RE: [PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Sakari, > -Original Message- > From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com] > Sent: Thursday, June 06, 2019 5:43 PM > To: Vishal Sagar > Cc: Vishal Sagar ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org;

RE: [PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Sakari, > -Original Message- > From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com] > Sent: Wednesday, June 05, 2019 12:54 AM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.c

RE: [PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Sakari, Thanks for reviewing this. > -Original Message- > From: linux-media-ow...@vger.kernel.org [mailto:linux-media- > ow...@vger.kernel.org] On Behalf Of Sakari Ailus > Sent: Tuesday, June 04, 2019 8:56 PM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch..

[PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

parameters based on the ST352 packet embedded in the stream. In case the ST352 packet isn't present in the stream, the core's detected properties are used to set stream properties. The driver currently supports only the AXI4-Stream configuration. Signed-off-by: Vishal Sagar --- drivers/media/platform

[PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem

. Signed-off-by: Vishal Sagar --- .../bindings/media/xilinx/xlnx,sdirxss.txt | 80 ++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx

[PATCH 0/2] Add support for Xilinx UHD-SDI Receiver subsystem

c SDI-HDMI convertors. This patch set is being sent on top of v8 of Xilinx MIPI CSI2-Rx Subsystem driver patches. Vishal Sagar (2): media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver .../bindings/media/xi

[PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

only the video format bridge enabled configuration. Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the CSI v2.0 feature is enabled in design. When the VCX feature is enabled, the maximum number of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar Reviewed-by: Hyun

[PATCH v8 0/2] Add support for Xilinx CSI2 Receiver Subsystem

format function - Support only VFB enabled config Vishal Sagar (2): media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver .../bindings/media/xilinx/xlnx,csi2rxss.txt| 119 ++ drivers/media/platform/xilinx

[PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem. The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a DPHY in Rx mode, an optional I2C controller and a Video Format Bridge. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon Reviewed-by: Rob Herring Reviewed

RE: [PATCH v7 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Sakari, Thanks for the review. > -Original Message- > From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com] > Sent: Friday, March 22, 2019 9:31 PM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > mche...@kernel.org; robh...@ker

[PATCH v7 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon --- v7 - No change v6 - No change v5 - Removed bayer and updated related parts like set default format based on Luca Cersoli's comments. - Added correct YUV422 10bpc media bus format v4 - Removed irq member

[PATCH v5 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon --- v5 - Removed bayer and updated related parts like set default format based on Luca Cersoli's comments. - Added correct YUV422 10bpc media bus format v4 - Removed irq member from core structure - Consolidated

RE: [PATCH v3 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

- > ow...@vger.kernel.org] On Behalf Of Luca Ceresoli > Sent: Monday, February 11, 2019 4:12 PM > To: Vishal Sagar ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; linux-me...@vger.kernel.org; >

RE: [PATCH v4 0/2] Add support for Xilinx CSI2 Receiver Subsystem

Hi all, Please ignore this patch series as I missed addressing some comments in this patch. I will address them in the next series. Regards Vishal Sagar > -Original Message- > From: Vishal Sagar [mailto:vishal.sa...@xilinx.com] > Sent: Friday, March 08, 2019 11:01 PM > T

[PATCH v4 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon --- v4 - Removed irq member from core structure - Consolidated IP config prints in xcsi2rxss_log_ipconfig() - Return -EINVAL in case of invalid ioctl - Code formatting - Added reviewed by Hyun Kwon v3 - Fixed

[PATCH v4 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem. The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a DPHY in Rx mode, an optional I2C controller and a Video Format Bridge. Signed-off-by: Vishal Sagar Reviewed-by: Hyun Kwon --- v4 - Added reviewed by Hyun Kwon

[PATCH v4 0/2] Add support for Xilinx CSI2 Receiver Subsystem

as sink and source - Now use the v4l2fwnode API to get number of data-lanes - Added clock framework support - Removed the close() function - updated the set format function - Support only VFB enabled config Vishal Sagar (2): media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx

RE: [v3,2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Hyun, Thanks for reviewing. Apologies for the delayed response. > -Original Message- > From: Hyun Kwon [mailto:hyun.k...@xilinx.com] > Sent: Thursday, February 14, 2019 1:16 AM > To: Vishal Sagar > Cc: laurent.pinch...@ideasonboard.com; mche...@kernel.org; >

RE: [PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Luca, Apologies for the delayed response. > -Original Message- > From: Luca Ceresoli [mailto:l...@lucaceresoli.net] > Sent: Monday, February 11, 2019 8:01 PM > To: Vishal Sagar ; Vishal Sagar ; > Hyun Kwon ; laurent.pinch...@ideasonboard.com; > mche...@kernel.org;

RE: [PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Luca, Thanks for reviewing this. > -Original Message- > From: Luca Ceresoli [mailto:l...@lucaceresoli.net] > Sent: Monday, February 11, 2019 4:12 PM > To: Vishal Sagar ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org; ma

[PATCH v3 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem. The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a DPHY in Rx mode, an optional I2C controller and a Video Format Bridge. Signed-off-by: Vishal Sagar --- v3 - removed interrupt parent as suggested by Rob

[PATCH v3 0/2] Add support for Xilinx CSI2 Receiver Subsystem

and extra virtual channels - Fixed the ports as sink and source - Now use the v4l2fwnode API to get number of data-lanes - Added clock framework support - Removed the close() function - updated the set format function - Support only VFB enabled config Vishal Sagar (2): media: dt

[PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar --- v3 - Fixed comments given by Hyun. - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver - Minor code formatting - en_csi_v20 and vfb members removed from struct and made local to dt parsing - lock description updated

RE: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Rob, Thanks for reviewing. > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Thursday, January 31, 2019 1:11 AM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > mche...@kernel.org; mark.rutl...@arm.com; Michal

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Hyun, > -Original Message- > From: Hyun Kwon [mailto:hyun.k...@xilinx.com] > Sent: Tuesday, January 29, 2019 12:05 AM > To: Vishal Sagar > Cc: Hyun Kwon ; Vishal Sagar ; > laurent.pinch...@ideasonboard.com; mche...@kernel.org; > robh...@kernel.org; mark.rutl...@

RE: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Sakari, > -Original Message- > From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com] > Sent: Monday, January 28, 2019 5:30 PM > To: Vishal Sagar > Cc: Vishal Sagar ; Hyun Kwon ; > laurent.pinch...@ideasonboard.com; Michal Simek ; > linux-me...@vge

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Hyun, Thanks for the review. > -Original Message- > From: Hyun Kwon [mailto:hyun.k...@xilinx.com] > Sent: Saturday, January 26, 2019 7:45 AM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > mche...@kernel.org; robh...@kernel.org; mark.rutl.

RE: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Hyun, Thanks for the review. > -Original Message- > From: Hyun Kwon [mailto:hyun.k...@xilinx.com] > Sent: Saturday, January 26, 2019 7:45 AM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > mche...@kernel.org; robh...@kernel.org; mark.rutl.

[PATCH v2 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

of virtual channels becomes 16 from 4. Signed-off-by: Vishal Sagar --- v2 - Fixed comments given by Hyun and Sakari. - Made all bitmask using BIT() and GENMASK() - Removed unused definitions - Removed DPHY access. This will be done by separate DPHY PHY driver. - Added support for CSI v2.0 for YUV 422

[PATCH v2 0/2] Add support for Xilinx CSI2 Receiver Subsystem

enabled config Vishal Sagar (2): media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver .../bindings/media/xilinx/xlnx,csi2rxss.txt| 105 ++ drivers/media/platform/xilinx/Kconfig | 10 + drivers

[PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem. The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a DPHY in Rx mode, an optional I2C controller and a Video Format Bridge. Signed-off-by: Vishal Sagar --- v2 - updated the compatible string to latest version

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Sakari, Thanks for reviewing my patch. > -Original Message- > From: linux-media-ow...@vger.kernel.org [mailto:linux-media- > ow...@vger.kernel.org] On Behalf Of Sakari Ailus > Sent: Wednesday, January 09, 2019 5:22 PM > To: Vishal Sagar > Cc: Hyun Kw

RE: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Sakari, Thanks for reviewing this. > -Original Message- > From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com] > Sent: Tuesday, January 08, 2019 6:35 PM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > Michal Simek ; linux-me.

RE: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

Hi Rob, Thanks for the review. > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Wednesday, June 13, 2018 1:34 AM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > michal.si...@xilinx.com; linux-me...@vger.ker

Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

Hi Hyun Thanks for the review. > -Original Message- > From: Hyun Kwon > Sent: Thursday, June 01, 2018 6:46 AM > To: Vishal Sagar > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com; > michal.si...@xilinx.com; linux-me...@vger.kernel.org; > devicet...@vger.

RE: [PATCH v9 2/2] media:imx274 V4l2 driver for Sony imx274 CMOS sensor

be sufficient to confirm this in the probe() and fail. Does it make sense to add this in the probe()? Regards Vishal Sagar > -Original Message- > From: linux-media-ow...@vger.kernel.org [mailto:linux-media- > ow...@vger.kernel.org] On Behalf Of Leon Luo > Sent: Thursday, October 26

RE: [PATCH v9 2/2] media:imx274 V4l2 driver for Sony imx274 CMOS sensor

be sufficient to confirm this in the probe() and fail. Does it make sense to add this in the probe()? Regards Vishal Sagar > -Original Message- > From: linux-media-ow...@vger.kernel.org [mailto:linux-media- > ow...@vger.kernel.org] On Behalf Of Leon Luo > Sent: Thursday, October 26