On Wed, Oct 28, 2020 at 03:03:44PM +0100, Jessica Yu wrote:
> +++ Will Deacon [28/10/20 13:24 +]:
> > On Wed, Oct 28, 2020 at 01:27:01PM +0100, Ard Biesheuvel wrote:
> > > On Wed, 28 Oct 2020 at 11:00, Will Deacon wrote:
> > > > On Tue, Oct 27, 2020 at 04:11:32
On Tue, Oct 27, 2020 at 10:38:16AM +0200, Mike Rapoport wrote:
> On Mon, Oct 26, 2020 at 06:05:30PM +, Edgecombe, Rick P wrote:
> > On Mon, 2020-10-26 at 11:05 +0200, Mike Rapoport wrote:
> > > On Mon, Oct 26, 2020 at 01:13:52AM +, Edgecombe, Rick P wrote:
> > > > On Sun, 2020-10-25 at
On Tue, 27 Oct 2020 16:11:32 +0100, Ard Biesheuvel wrote:
> Geert reports that commit be2881824ae9eb92 ("arm64/build: Assert for
> unwanted sections") results in build errors on arm64 for configurations
> that have CONFIG_MODULES disabled.
>
> The commit in question added ASSERT()s to the arm64
On Mon, 26 Oct 2020 12:12:42 +, Vincenzo Frascino wrote:
> This series contains a set of fixes for the arm64 MTE kselftests [1].
>
> A version of the fixes rebased on 5.10-rc1 can be found at [2].
>
> To verify the fixes it is possible to use the command below:
>
> make -C
On Sat, Oct 24, 2020 at 11:51:49AM +0200, Dmitry Vyukov wrote:
> Hello ARM64/LOCKDEP maintainers,
>
> I've started experimenting with running syzkaller on ARM64 using
> QEMU/TCG. Total execution speed is very low and it ran just a handful
> of tests, but I am seeing massive amounts of locking
On Mon, 26 Oct 2020 20:37:46 +0100, Arnd Bergmann wrote:
> The icache_policy_str[] definition causes a warning when extra
> warning flags are enabled:
>
> arch/arm64/kernel/cpuinfo.c:38:26: warning: initialized field overwritten
> [-Woverride-init]
>38 | [ICACHE_POLICY_VIPT] = "VIPT",
>
On Fri, 23 Oct 2020 08:47:50 -0700, Stephen Boyd wrote:
> According to the SMCCC spec[1](7.5.2 Discovery) the
> ARM_SMCCC_ARCH_WORKAROUND_1 function id only returns 0, 1, and
> SMCCC_RET_NOT_SUPPORTED.
>
> 0 is "workaround required and safe to call this function"
> 1 is "workaround not required
On Tue, Oct 27, 2020 at 10:53:47PM -0700, John Stultz wrote:
> On Mon, Jul 13, 2020 at 1:41 PM Will Deacon wrote:
> > On Fri, Jul 10, 2020 at 03:21:53PM -0700, John Stultz wrote:
> > > On Fri, Jul 10, 2020 at 12:54 AM Will Deacon wrote:
> > > > On Thu, Jul 09,
On Mon, Oct 26, 2020 at 08:28:45PM +0100, Arnd Bergmann wrote:
> On Mon, Oct 26, 2020 at 6:27 PM Will Deacon wrote:
> > On Mon, Oct 26, 2020 at 05:13:30PM +, Peter Maydell wrote:
> > > On Mon, 26 Oct 2020 at 16:23, Mark Rutland wrote:
> > > > On Mon, Oct 26,
On Mon, Oct 26, 2020 at 05:13:30PM +, Peter Maydell wrote:
> On Mon, 26 Oct 2020 at 16:23, Mark Rutland wrote:
> > On Mon, Oct 26, 2020 at 05:03:31PM +0100, Arnd Bergmann wrote:
> > > From: Arnd Bergmann
> > >
> > > There are many warnings in this file when we re-enable the
> > >
On Mon, 19 Oct 2020 18:14:07 -0700, Nathan Chancellor wrote:
> As it stands now, the vdso32 Makefile hardcodes the linker to ld.bfd
> using -fuse-ld=bfd with $(CC). This was taken from the arm vDSO
> Makefile, as the comment notes, done in commit d2b30cd4b722 ("ARM:
> 8384/1: VDSO: force use of
t; break;
> }
> break;
> diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
> index 15c706fb0a37..0e50ba3e88d7 100644
> --- a/include/linux/arm-smccc.h
> +++ b/include/linux/arm-smccc.h
> @@ -86,6 +86,8 @@
> ARM_SMCCC_SMC_32,\
> 0, 0x7fff)
>
> +#define SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED 1
I thought we'd stick this in asm/spectre.h, but here is also good:
Acked-by: Will Deacon
Will
On Mon, Oct 26, 2020 at 09:23:31AM +1100, Gavin Shan wrote:
> On 10/25/20 8:52 PM, Marc Zyngier wrote:
> > On Sun, 25 Oct 2020 01:27:37 +0100,
> > Gavin Shan wrote:
> > >
> > > The 52-bits physical address is disabled until CONFIG_ARM64_PA_BITS_52
> > > is chosen. This uses option for that
On Fri, Oct 23, 2020 at 01:22:04PM +0200, Christophe Leroy wrote:
> Hi Dmitry,
>
> Le 28/09/2020 à 17:08, Dmitry Safonov a écrit :
> > On 9/27/20 8:43 AM, Christophe Leroy wrote:
> > >
> > >
> > > Le 21/09/2020 à 13:26, Will Deacon a écrit :
> &
mu/io-pgtable-arm-v7s.c | 34 +++---
> 1 file changed, 17 insertions(+), 17 deletions(-)
Acked-by: Will Deacon
(but see my later comments above doing this for some of the 'constants' too)
Will
pgtable.h | 4 ++--
> 3 files changed, 10 insertions(+), 5 deletions(-)
Acked-by: Will Deacon
Will
On Wed, Sep 30, 2020 at 03:06:34PM +0800, Yong Wu wrote:
> The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
> (4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
> 34bit.
>
> Signed-off-by: Yong Wu
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 13
On Wed, Sep 30, 2020 at 03:06:31PM +0800, Yong Wu wrote:
> Use the ias for the valid iova checking in arm_v7s_unmap. This is a
> preparing patch for supporting iova 34bit for MediaTek.
> BTW, change the ias/oas checking format in arm_v7s_map.
>
> Signed-off-by: Yong Wu
> ---
>
On Wed, Oct 21, 2020 at 08:29:58PM -0700, Stephen Boyd wrote:
> According to the SMCCC spec[1](7.5.2 Discovery) the
> ARM_SMCCC_ARCH_WORKAROUND_1 function id only returns 0, 1, and
> SMCCC_RET_NOT_SUPPORTED.
>
> 0 is "workaround required and safe to call this function"
> 1 is "workaround not
so_offsets.sh
Peter Collingbourne (1):
arm64: reject prctl(PR_PAC_RESET_KEYS) on compat tasks
Stephen Boyd (1):
arm64: proton-pack: Update comment to reflect new function name
Will Deacon (1):
arm64: spectre-v2: Favour CPU-specific mitigation at EL2
arch/
On Wed, Oct 21, 2020 at 09:12:02AM -0700, Stephen Boyd wrote:
> Quoting Will Deacon (2020-10-21 08:49:09)
> > On Wed, Oct 21, 2020 at 08:23:54AM -0700, Stephen Boyd wrote:
> > >
> > > If I'm reading the TF-A code correctly it looks like this will return
> >
On Wed, Oct 21, 2020 at 08:23:54AM -0700, Stephen Boyd wrote:
> Quoting Will Deacon (2020-10-21 00:57:23)
> > On Tue, Oct 20, 2020 at 02:45:43PM -0700, Stephen Boyd wrote:
> > > According to the SMCCC spec (7.5.2 Discovery) the
> > > ARM_SMCCC_ARCH_WORKAROUND_1 fu
On Tue, 20 Oct 2020 14:45:42 -0700, Stephen Boyd wrote:
> The first patch fixes a problem with spectre-v2 detection in guest
> kernels found on v5.4 and the second patch fixes an outdated comment.
>
> Cc: Andre Przywara
> Cc: Steven Price
> Cc: Marc Zyngier
> Cc: sta...@vger.kernel.org
>
>
On Wed, Oct 21, 2020 at 11:23:34AM +0100, Marc Zyngier wrote:
> On 2020-10-21 08:57, Will Deacon wrote:
> > On Tue, Oct 20, 2020 at 02:45:43PM -0700, Stephen Boyd wrote:
> > > According to the SMCCC spec (7.5.2 Discovery) the
> > > ARM_SMCCC_ARCH_WORKAROUND_1 fu
On Tue, Oct 20, 2020 at 02:45:43PM -0700, Stephen Boyd wrote:
> According to the SMCCC spec (7.5.2 Discovery) the
> ARM_SMCCC_ARCH_WORKAROUND_1 function id only returns 0, 1, and
> SMCCC_RET_NOT_SUPPORTED corresponding to "workaround required",
> "workaround not required but implemented", and "who
On Fri, 16 Oct 2020 17:26:37 -0700, Palmer Dabbelt wrote:
> I was going to copy this but I didn't want to chase around the build
> system stuff so I did it a different way.
Applied to arm64 (for-next/core), thanks!
[1/1] arm64: Fix a broken copyright header in gen_vdso_offsets.sh
On Fri, 16 Oct 2020 10:53:39 -0700, Nick Desaulniers wrote:
> With CONFIG_EXPERT=y, CONFIG_KASAN=y, CONFIG_RANDOMIZE_BASE=n,
> CONFIG_RELOCATABLE=n, we observe the following failure when trying to
> link the kernel image with LD=ld.lld:
>
> error: section: .exit.data is not contiguous with other
On Mon, Oct 19, 2020 at 06:14:07PM -0700, Nathan Chancellor wrote:
> As it stands now, the vdso32 Makefile hardcodes the linker to ld.bfd
> using -fuse-ld=bfd with $(CC). This was taken from the arm vDSO
> Makefile, as the comment notes, done in commit d2b30cd4b722 ("ARM:
> 8384/1: VDSO: force use
On Fri, Oct 16, 2020 at 05:26:37PM -0700, Palmer Dabbelt wrote:
> From: Palmer Dabbelt
>
> I was going to copy this but I didn't want to chase around the build
> system stuff so I did it a different way.
How did you end up doing it? I remember trying to parse the ELF object at
one time of day
On Mon, Oct 19, 2020 at 01:24:55PM +0100, Mark Rutland wrote:
> On Tue, Oct 06, 2020 at 05:13:31PM +0100, Alexandru Elisei wrote:
> > On 10/6/20 4:32 PM, Marc Zyngier wrote:
> > > On Tue, 06 Oct 2020 16:05:20 +0100,
> > > Alexandru Elisei wrote:
> > >> From ARM DDI 0487F.b, page D9-2807:
> > >>
>
On Wed, 14 Oct 2020 00:53:05 +, Kalesh Singh wrote:
> This is a repost of the mremap speed up patches, adding Kirill's
> Acked-by's (from a separate discussion). The previous versions are
> posted at:
> v1 - https://lore.kernel.org/r/20200930222130.4175584-1-kaleshsi...@google.com
> v2 -
did not enable it on arm64 at the time because
> of performance issues with flushing the TLB on every PMD move. These
> issues have since been addressed in more recent releases with
> improvements to the arm64 TLB invalidation and core mmu_gather code as
> Will Deacon mentioned in [2
ecutable.
>
> Signed-off-by: Joe Perches
> ---
> scripts/atomic/atomics.tbl | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
>
> diff --git a/scripts/atomic/atomics.tbl b/scripts/atomic/atomics.tbl
> old mode 100755
> new mode 100644
Acked-by: Will Deacon
Will
On Wed, Oct 14, 2020 at 09:12:03PM +0200, Nicolas Saenz Julienne wrote:
> crashkernel might reserve memory located in ZONE_DMA. We plan to delay
> ZONE_DMA's initialization after unflattening the devicetree and ACPI's
> boot table initialization, so move it later in the boot process.
>
emmap_populate_basepages().
>
> Signed-off-by: Sudarshan Rajagopalan
> Reviewed-by: Gavin Shan
> Reviewed-by: Anshuman Khandual
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Anshuman Khandual
> Cc: Mark Rutland
> Cc: Logan Gunthorpe
> Cc: David Hildenbrand
On Mon, Oct 12, 2020 at 01:44:56PM -0700, Kees Cook wrote:
> On Mon, Oct 12, 2020 at 09:31:16AM +0100, Will Deacon wrote:
> > On Fri, Oct 09, 2020 at 09:13:34AM -0700, Sami Tolvanen wrote:
> > > Allow CONFIG_LTO_CLANG and CONFIG_THINLTO to be enabled.
> > >
> &g
On Sat, Oct 10, 2020 at 12:28:39AM +1100, Michael Ellerman wrote:
> Peter Zijlstra writes:
> > Patch 4 makes it all far worse by exposing it to pretty much everybody.
> >
> > Now, I think we can fix at least the user mappings with the below delta,
> > but if archs are using non-page-table MMU
On Fri, Oct 09, 2020 at 09:13:34AM -0700, Sami Tolvanen wrote:
> Allow CONFIG_LTO_CLANG and CONFIG_THINLTO to be enabled.
>
> Signed-off-by: Sami Tolvanen
> Reviewed-by: Kees Cook
> ---
> arch/arm64/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/Kconfig
tion and initial sysreg configuration
arm64: mte: Add specific SIGSEGV codes
arm64: mte: Handle synchronous and asynchronous tag check faults
arm64: mte: Tags-aware copy_{user_,}highpage() implementations
arm64: mte: Kconfig entry
arm64: mte: Add Memory Tagging Extension documen
On Fri, Oct 09, 2020 at 11:24:38AM +0100, Mark Rutland wrote:
> On Fri, Oct 09, 2020 at 10:43:18AM +0100, Mark Rutland wrote:
> > Hi Qian,
> >
> > On Fri, Oct 09, 2020 at 09:51:15AM +0100, Will Deacon wrote:
> > > On Thu, Oct 08, 2020 at 09:18:24PM -0400, Qian Cai
On Fri, Oct 09, 2020 at 11:09:27AM +0200, Peter Zijlstra wrote:
> On Thu, Oct 01, 2020 at 06:57:46AM -0700, kan.li...@linux.intel.com wrote:
> > +/*
> > + * Return the MMU page size of a given virtual address
> > + */
> > +static u64 __perf_get_page_size(struct mm_struct *mm, unsigned long addr)
>
have
> > been allocated (which can change CPU0's offset).
> >
> > So that init_this_cpu_offset() isn't subject to any instrumentation that
> > might consume the per-cpu offset, it is marked with noinstr, preventing
> > instrumentation.
> >
> > Signed-off-by: Mark Rutland
>
On Tue, 6 Oct 2020 20:44:53 +0100, Andre Przywara wrote:
> Commit 9bceb80b3cc4 ("arm64: kaslr: Use standard early random
> function") removed the direct calls of the __arm64_rndr() and
> __early_cpu_has_rndr() functions, but left the dummy prototypes in the
> #else branch of the #ifdef
Define a statically allocated seqlock_t
> * @sl: Name of the seqlock_t instance
> */
> #define DEFINE_SEQLOCK(sl) \
Acked-by: Will Deacon
Will
On Tue, Oct 06, 2020 at 11:01:21AM +0100, Dave Martin wrote:
> On Tue, Oct 06, 2020 at 09:27:48AM +0100, Will Deacon wrote:
> > On Mon, Oct 05, 2020 at 10:48:54PM -0500, Jeremy Linton wrote:
> > > The AES code uses a 'br x7' as part of a function called by
> > > a macro
__xts_crypt8
> + bl \do8
>
> ldp q16, q17, [sp, #.Lframe_local_offset]
> ldp q18, q19, [sp, #.Lframe_local_offset + 32]
Acked-by: Will Deacon
Catalin -- can you pick this for 5.9 please?
Will
On Tue, Oct 06, 2020 at 01:08:23AM -0700, syzbot wrote:
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:549738f1 Linux 5.9-rc8
> git tree: upstream
> console output: https://syzkaller.appspot.com/x/log.txt?x=15b97ba390
> kernel config:
On Fri, 2 Oct 2020 17:26:24 +0530, Amit Daniel Kachhap wrote:
> These patch series adds below kselftests to test the user-space support for
> the
> ARMv8.5 Memory Tagging Extension present in arm64 tree [1]. This patch
> series is based on Linux v5.9-rc3.
>
> 1) This test-case verifies that the
On Mon, Oct 05, 2020 at 10:23:51AM -0400, Alan Stern wrote:
> On Mon, Oct 05, 2020 at 10:12:48AM +0100, Will Deacon wrote:
> > On Mon, Oct 05, 2020 at 09:20:03AM +0100, Will Deacon wrote:
> > > On Sun, Oct 04, 2020 at 10:38:46PM -0400, Alan Stern wrote:
> > > > Consid
On Mon, Oct 05, 2020 at 09:20:03AM +0100, Will Deacon wrote:
> On Sun, Oct 04, 2020 at 10:38:46PM -0400, Alan Stern wrote:
> > On Sun, Oct 04, 2020 at 04:31:46PM -0700, Paul E. McKenney wrote:
> > > Nice simple exampl
On Fri, Oct 02, 2020 at 04:48:00PM +0100, Colin King wrote:
> From: Colin Ian King
>
> Currently the failure check on dtc->irq is always false because
> dtc->irq is an unsigned int. Fix this by using a temporary signed
> int for the less than zero error check.
>
> Addresses-Coverity: ("Unsigned
On Sun, Oct 04, 2020 at 10:38:46PM -0400, Alan Stern wrote:
> On Sun, Oct 04, 2020 at 04:31:46PM -0700, Paul E. McKenney wrote:
> > Nice simple example! How about like this?
> >
> > Thanx, Paul
> >
> >
On Wed, Sep 30, 2020 at 05:31:35PM +0800, Wei Li wrote:
> Armv8.3 extends the SPE by adding:
> - Alignment field in the Events packet, and filtering on this event
> using PMSEVFR_EL1.
> - Support for the Scalable Vector Extension (SVE).
>
> The main additions for SVE are:
> - Recording the
On Wed, Sep 30, 2020 at 09:05:23AM +0100, Will Deacon wrote:
> Please pull these arm-smmu updates for 5.10. Summary in the tag, but the
> big thing here is the long-awaited SVM enablement from Jean-Philippe.
> We're not quite done yet, but this pull extends the SMMUv3 driver so that
>
a page
dirty, as the TLB is permitted to cache the old read-only entry.
Cc: Catalin Marinas
Link: https://lore.kernel.org/r/20200728092220.GA21800@willie-the-truck
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/pgtable.h | 8
arch/arm64/mm/fault.c| 4 +++-
2 files
Jiri Slaby
Link: https://lore.kernel.org/r/20200811101313.GA6970@willie-the-truck
Signed-off-by: Peter Zijlstra
Tested-by: Will Deacon
Signed-off-by: Will Deacon
---
drivers/tty/serial/amba-pl011.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/s
lit pagetables
iommu/arm-smmu: Prepare for the adreno-smmu implementation
Rob Clark (1):
iommu/arm-smmu: Constify some helpers
Will Deacon (1):
Merge branch 'for-next/svm' of git://git.kernel.org/.../arm64/linux into
for-joerg/arm-smmu/updates
Yu Kuai (1):
iommu/qcom: add miss
lds.S | 6
> arch/arm64/kvm/pmu.c | 5 ++-
> 5 files changed, 87 insertions(+), 6 deletions(-)
Acked-by: Will Deacon
But one comment for Marc below...
> diff --git a/arch/arm64/include/asm/kvm_asm.h
> b/arch/arm64/include/asm/kvm_asm.h
> index 911d91787fa0..863f669
On Thu, Sep 24, 2020 at 07:55:19PM +0800, Hou Tao wrote:
> The following is the newest performance data:
>
> aarch64 host (4 sockets, 24 cores per sockets)
>
> * v4.19.111
>
> no writer, reader cn| 24| 48|
> 72| 96
> rate of
On Tue, Sep 29, 2020 at 08:46:46AM -0500, Rob Herring wrote:
> On Mon, Sep 28, 2020 at 1:26 PM Will Deacon wrote:
> > On Fri, Sep 11, 2020 at 03:51:09PM -0600, Rob Herring wrote:
> > > +static int emulate_pmu(struct pt_regs *regs, u32 insn)
> > > +{
> > > +
ll
^^^ Missing space between "Scull" and "<".
> Signed-off-by: David Brazdil
> ---
> arch/arm64/include/asm/kvm_mmu.h | 20
> arch/arm64/kvm/arm.c | 16
> 2 files changed, 36 deletions(-)
Acked-by: Will Deacon
Will
| 3 +++
> arch/arm64/kvm/hyp/nvhe/switch.c | 3 +++
> 4 files changed, 19 insertions(+), 2 deletions(-)
Acked-by: Will Deacon
Marc: please take a look at for-next/ghostbusters on the arm64 tree, as
that has the patches which remove this stuff entirely. I had to rebase
the branch today becau
on VHE/nVHE.
>
> Simplify this now that the hyp mode case can be handled using the
> __KVM_VHE/NVHE_HYPERVISOR__ macros.
>
> Acked-by: Andrew Scull
> Acked-by: Will Deacon
> Signed-off-by: David Brazdil
> ---
> arch/arm64/include/asm/assembler.h | 29
| 4 ++--
> 7 files changed, 36 insertions(+), 32 deletions(-)
Looks good, thanks for the respin!
Acked-by: Will Deacon
Will
On Tue, Sep 29, 2020 at 12:08:35PM -0500, Gustavo A. R. Silva wrote:
> Fix unsigned comparison to less than zero by assigning the returned
> value of function platform_get_irq() to a new integer variable _ret_
> and then make the comparison. In case the returned value is greater
> than or equal to
On Tue, 29 Sep 2020 09:40:37 +0800, Yu Kuai wrote:
> if of_find_device_by_node() succeed, qcom_iommu_of_xlate() doesn't have
> a corresponding put_device(). Thus add put_device() to fix the exception
> handling for this function implementation.
Applied to will (for-joerg/arm-smmu/updates),
On Tue, Sep 29, 2020 at 01:34:24PM +0530, Anshuman Khandual wrote:
>
>
> On 09/29/2020 02:05 AM, Will Deacon wrote:
> > On Thu, Sep 17, 2020 at 02:16:42PM +0530, Anshuman Khandual wrote:
> >> During memory hotplug process, the linear mapping should not be created for
&
Hi Anthony,
On Mon, Sep 28, 2020 at 10:10:32PM -0400, Anthony Steinhauser wrote:
> > Are you sure copy_thread() is the right place for this? afaict, that would
> > also apply to plain fork(), which isn't what we want. It looks like
> > arch_setup_new_exec() is a better fit, and matches what x86
On Tue, 22 Sep 2020 23:04:10 +1000, Gavin Shan wrote:
> This series bases on 5.9.rc5 and extracted from (v4) series of "Refactoring
> SDEI client driver", which is prepatory work to support SDEI virtualizaton.
> This series can be checkout from github.
>
>g...@github.com:gwshan/linux.git
On Thu, 24 Sep 2020 12:06:59 +0100, Alexandru Elisei wrote:
> The series changes the arm_pmu driver to use NMIs for the perf interrupt
> when NMIs are available on the platform (currently, only arm64 + GICv3). To
> make it easier to play with the patches, I've pushed a branch at [1]:
>
> $ git
On Fri, Sep 04, 2020 at 12:56:37PM +0530, Sumit Garg wrote:
> With the recent feature added to enable perf events to use pseudo NMIs
> as interrupts on platforms which support GICv3 or later, its now been
> possible to enable hard lockup detector (or NMI watchdog) on arm64
> platforms. So enable
On Mon, Sep 21, 2020 at 09:45:57PM +0100, Will Deacon wrote:
> On Tue, Sep 22, 2020 at 03:13:53AM +0800, kernel test robot wrote:
> > Thank you for the patch! Perhaps something to improve:
> >
> > [auto build test WARNING on iommu/next]
> > [also build test WARNING on
On Wed, Sep 23, 2020 at 08:32:43AM +0200, Auger Eric wrote:
> On 9/21/20 10:45 PM, Will Deacon wrote:
> > On Mon, Sep 14, 2020 at 11:13:07AM -0700, Vennila Megavannan wrote:
> >> From: Srinath Mannam
> >>
> >> Add provision to change default value of MSI IOVA b
t; arch_add_memory() validates memory hot add range for its potential linear
> mapping requirement, before creating it with __create_pgd_mapping().
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Mark Rutland
> Cc: Ard Biesheuvel
> Cc: Steven Price
> Cc: Robi
On Fri, Sep 11, 2020 at 03:51:09PM -0600, Rob Herring wrote:
> From: Raphael Gault
>
> This patch introduces a protection for the userspace processes which are
> trying to access the registers from the pmu registers on a big.LITTLE
> environment. It introduces a hook to handle undefined
by kvm_destroy_vm(). Prevent
> running the irq_work for a non-existent vcpu by calling irq_work_sync() on
> the PMU destroy path.
>
> Cc: Julien Thierry
> Cc: Marc Zyngier
> Cc: Will Deacon
> Cc: Mark Rutland
> Cc: Catalin Marinas
> Cc: James Morse
> Cc: Suzuki
[+ Lorenzo]
On Tue, Sep 22, 2020 at 06:33:24PM +0800, Baolin Wang wrote:
> If the BIOS disabled the NUMA configuration, but did not change the
> proximity domain description in the SRAT table, so the PCI root bus
> device may get a incorrect node id by acpi_get_node().
How "incorrect" are we
Hi Anthony,
On Tue, Sep 22, 2020 at 02:21:53AM -0700, Anthony Steinhauser wrote:
> Support of Spectre v4 PR_SPEC_DISABLE_NOEXEC mitigation mode for on arm64.
>
> PR_SPEC_DISABLE_NOEXEC turns the mitigation on, but it is automatically
> turned off whenever a new program is being execve'ed.
>
>
On Mon, Sep 21, 2020 at 11:03:49PM +0100, Robin Murphy wrote:
> On 2020-09-21 19:03, Will Deacon wrote:
> > On Fri, Sep 11, 2020 at 07:57:18PM +0530, Sai Prakash Ranjan wrote:
> > > Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
> > > attributes set in TCR for
On Sat, Sep 05, 2020 at 01:04:06PM -0700, Rob Clark wrote:
> From: Rob Clark
>
> NOTE: I have re-ordered the series, and propose that we could merge this
> series in the following order:
>
>1) 01-11 - merge via drm / msm-next
>2) 12-15 - merge via iommu, no dependency on
On Sat, Sep 12, 2020 at 10:25:59PM -0500, Bjorn Andersson wrote:
> On Fri 11 Sep 12:13 CDT 2020, Robin Murphy wrote:
> > On 2020-09-04 16:55, Bjorn Andersson wrote:
> > > Add a new operation to allow platform implementations to inherit any
> > > stream mappings from the boot loader.
> >
> > Is
On Mon, Sep 14, 2020 at 11:13:07AM -0700, Vennila Megavannan wrote:
> From: Srinath Mannam
>
> Add provision to change default value of MSI IOVA base to platform's
> suitable IOVA using module parameter. The present hardcoded MSI IOVA base
> may not be the accessible IOVA ranges of platform.
>
On Tue, Sep 22, 2020 at 03:13:53AM +0800, kernel test robot wrote:
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on iommu/next]
> [also build test WARNING on linus/master v5.9-rc6 next-20200921]
> [cannot apply to robclark/msm-next]
> [If your patch is
On Fri, Sep 11, 2020 at 07:57:18PM +0530, Sai Prakash Ranjan wrote:
> Add a quirk IO_PGTABLE_QUIRK_SYS_CACHE to override the
> attributes set in TCR for the page table walker when
> using system cache.
I wonder if the panfrost folks can reuse this for the issue discussed
over at:
On Mon, Sep 21, 2020 at 04:41:00PM +0100, Alexandru Elisei wrote:
> On 9/21/20 2:59 PM, Will Deacon wrote:
> > On Wed, Aug 19, 2020 at 02:34:12PM +0100, Alexandru Elisei wrote:
> >> The series makes the arm_pmu driver use NMIs for the perf interrupt when
> >> NMIs ar
On Fri, Sep 18, 2020 at 09:13:57AM +0800, Yu Kuai wrote:
> if of_find_device_by_node() succeed, qcom_iommu_of_xlate() doesn't have
> a corresponding put_device(). Thus add put_device() to fix the exception
> handling for this function implementation.
>
> Fixes: e86d1aa8b60f ("iommu/arm-smmu: Move
On Mon, Sep 21, 2020 at 05:37:10PM +0200, Alexander Potapenko wrote:
> On Mon, Sep 21, 2020 at 4:58 PM Alexander Potapenko wrote:
> >
> > On Mon, Sep 21, 2020 at 4:31 PM Will Deacon wrote:
> > >
> > > On Mon, Sep 21, 2020 at 03:26:04PM +0200, Marco Elver wrote:
On Thu, Sep 10, 2020 at 08:48:40PM +, sudar...@codeaurora.org wrote:
> On 2020-09-10 03:50, Anshuman Khandual wrote:
> > The proposed patch tried to mix both approaches. Regardless, the first
> > approach
> > here seems better and is the case in vmemmap_populate_hugepages()
> > implementation
On Mon, Sep 21, 2020 at 03:53:20PM +0100, David Brazdil wrote:
> > Cosmetic, but I think it would be cleaner just to define two variants of the
> > macro here:
> >
> > #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
> > .macro this_cpu_offset, dst
> > mrs
On Mon, Sep 21, 2020 at 03:26:04PM +0200, Marco Elver wrote:
> Add architecture specific implementation details for KFENCE and enable
> KFENCE for the arm64 architecture. In particular, this implements the
> required interface in . Currently, the arm64 version does
> not yet use a statically
On Wed, Aug 19, 2020 at 02:34:12PM +0100, Alexandru Elisei wrote:
> The series makes the arm_pmu driver use NMIs for the perf interrupt when
> NMIs are available on the platform (currently, only arm64 + GICv3). To make
> it easier to play with the patches, I've pushed a branch at [1]:
This mostly
g the interrupt.
>
> Define sets of callbacks for operations commonly done on the interrupt. The
> appropriate set of callbacks is selected at interrupt request time and
> simplifies interrupt enabling/disabling and freeing.
>
> Cc: Julien Thierry
> Cc: Will Deacon
> Cc: Mark R
e previously programmed event
> overflowing, but which we wrongly attribute to the event that we are
> enabling.
>
> In the process, remove the comment that refers to the ARMv7 PMU.
>
> Cc: Julien Thierry
> Cc: Will Deacon
> Cc: Peter Zijlstra
> Cc: Ingo Molnar
> C
On Fri, Aug 21, 2020 at 09:54:20PM +0800, John Garry wrote:
> As mentioned in [0], the CPU may consume many cycles processing
> arm_smmu_cmdq_issue_cmdlist(). One issue we find is the cmpxchg() loop to
> get space on the queue takes a lot of time once we start getting many
> CPUs contending - from
On Wed, Aug 19, 2020 at 02:34:17PM +0100, Alexandru Elisei wrote:
> From: Julien Thierry
>
> kvm_vcpu_kick() is not NMI safe. When the overflow handler is called from
> NMI context, defer waking the vcpu to an irq_work queue.
>
> Cc: Julien Thierry
> Cc: Marc Zyngier
&g
On Fri, Jul 17, 2020 at 01:10:06PM +0200, Peter Zijlstra wrote:
> The first MMU_GATHER_TABLE_FREE user showed a logic error in the
> tlb_needs_table_invalidate() definition. Make sure any TABLE_FREE has
> it defined.
Could you elaborate on the logic error, please? It's difficult to see
through
> to 0
> * @r: the refcount
> * @lock: the spinlock to be locked
> - * @flags: saved IRQ-flags if the is acquired
> + * @flags: saved IRQ-flags if the is @lock acquired
This still isn't quite right. If we go with:
@flags: saved IRQ-flags if @lock is acquired
then:
Acked-by: Will Deacon
Will
On Fri, Aug 28, 2020 at 12:14:28PM +1000, Michael Ellerman wrote:
> Dmitry Safonov <0x7f454...@gmail.com> writes:
> > On Wed, 26 Aug 2020 at 15:39, Michael Ellerman wrote:
> >> Christophe Leroy writes:
> >> We added a test for vdso unmap recently because it happened to trigger a
> >> KAUP
On Wed, Jul 29, 2020 at 01:11:20PM +0200, pet...@infradead.org wrote:
> On Tue, Jul 28, 2020 at 11:56:38AM +0100, David Howells wrote:
> > Peter Zijlstra wrote:
> >
> > > > Please do not _undo_ the changes; just add the API you need.
> > >
> > > add_return and sub_return are horrible interface
Hi Anthony,
On Sun, Sep 20, 2020 at 03:25:23AM -0700, Anthony Steinhauser wrote:
> > As a heads up: I'm currently reworking most of this, and hope to post
> > something within the next two weeks.
>
> Sure. Let me know whether you want to implement the
> PR_SPEC_DISABLE_NOEXEC support directly or
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