Re: [PATCH RFC 1/3] vmx: allow ioeventfd for EPT violations

On 08/31/2015 03:46 PM, Michael S. Tsirkin wrote: On Mon, Aug 31, 2015 at 10:53:58AM +0800, Xiao Guangrong wrote: On 08/30/2015 05:12 PM, Michael S. Tsirkin wrote: Even when we skip data decoding, MMIO is slightly slower than port IO because it uses the page-tables, so the CPU must do

Re: [GIT PULL] Early batch of KVM changes for 4.3 merge window

Linus, I am sorry for the annoyance. On 09/01/2015 08:47 AM, Linus Torvalds wrote: Hmm: On Fri, Aug 14, 2015 at 4:57 PM, Paolo Bonzini <pbonz...@redhat.com> wrote: Xiao Guangrong (9): KVM: MMU: fully check zero bits for sptes The above commit causes an annoying new compiler w

Re: [PATCH RFC 1/3] vmx: allow ioeventfd for EPT violations

On 08/31/2015 07:27 PM, Michael S. Tsirkin wrote: On Mon, Aug 31, 2015 at 04:32:52PM +0800, Xiao Guangrong wrote: On 08/31/2015 03:46 PM, Michael S. Tsirkin wrote: On Mon, Aug 31, 2015 at 10:53:58AM +0800, Xiao Guangrong wrote: On 08/30/2015 05:12 PM, Michael S. Tsirkin wrote: Even

Re: [PATCH RFC 1/3] vmx: allow ioeventfd for EPT violations

On 08/30/2015 05:12 PM, Michael S. Tsirkin wrote: Even when we skip data decoding, MMIO is slightly slower than port IO because it uses the page-tables, so the CPU must do a pagewalk on each access. This overhead is normally masked by using the TLB cache: but not so for KVM MMIO, where PTEs

Re: [PATCH RFC 1/3] vmx: allow ioeventfd for EPT violations

On 08/30/2015 05:12 PM, Michael S. Tsirkin wrote: Even when we skip data decoding, MMIO is slightly slower than port IO because it uses the page-tables, so the CPU must do a pagewalk on each access. This overhead is normally masked by using the TLB cache: but not so for KVM MMIO, where PTEs

[PATCH 3/9] KVM: x86: add pcommit support

Pass PCOMMIT CPU feature to guest to enable PCOMMIT instruction Currently we do not catch pcommit instruction for L1 guest and allow L1 to catch this instruction for L2 The specification locates at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Signed-off-by: Xiao

[PATCH 5/9] KVM: VMX: simplify rdtscp handling in vmx_cpuid_update()

if vmx_rdtscp_supported() is true SECONDARY_EXEC_RDTSCP must have already been set in current vmcs by vmx_secondary_exec_control() Signed-off-by: Xiao Guangrong --- arch/x86/kvm/vmx.c | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch

[PATCH 4/9] KVM: VMX: drop rdtscp_enabled check in prepare_vmcs02()

SECONDARY_EXEC_RDTSCP set for L2 guest comes from vmcs12 Signed-off-by: Xiao Guangrong --- arch/x86/kvm/vmx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index b526c61..f7a721e 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm

[PATCH 6/9] KVM: VMX: simplify invpcid handling in vmx_cpuid_update()

-by: Xiao Guangrong --- arch/x86/kvm/vmx.c | 19 ++- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 99f638e..0d68140 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -8684,20 +8684,13 @@ static void vmx_cpuid_update

[PATCH 8/9] KVM: VMX: introduce set_clear_2nd_exec_ctrl()

It's used to clean up the code Signed-off-by: Xiao Guangrong --- arch/x86/kvm/vmx.c | 42 +++--- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 4f238b7..58f7b89 100644 --- a/arch/x86/kvm/vmx.c

[PATCH 7/9] KVM: VMX: unify SECONDARY_VM_EXEC_CONTROL update

Unify the update in vmx_cpuid_update() Signed-off-by: Xiao Guangrong --- arch/x86/kvm/vmx.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 0d68140..4f238b7 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86

[PATCH 9/9] KVM: VMX: drop rdtscp_enabled field

Check cpuid bit instead of it Signed-off-by: Xiao Guangrong --- arch/x86/kvm/cpuid.h | 8 arch/x86/kvm/vmx.c | 19 ++- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index aed7bfe..d434ee9 100644

[PATCH 0/9] KVM: x86: enable cflushopt/clwb/pcommit and simplify code

these three instructions for guest patch 4 ~ patch 9 simplify current VMX code Xiao Guangrong (9): KVM: MMU: fix use uninitialized value KVM: x86: allow guest to use cflushopt anc clwb KVM: x86: add pcommit support KVM: VMX: drop rdtscp_enabled check in prepare_vmcs02() KVM: VMX: simplify

[PATCH 1/9] KVM: MMU: fix use uninitialized value

ere int root, leaf; It's true as shadow_walk_init() may stop the loop Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 70c375f..a8a5b8d 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/

[PATCH 2/9] KVM: x86: allow guest to use cflushopt anc clwb

Pass its CPU feature to guest to enable them in guest These are needed by nvdimm drivers The specification locates at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Signed-off-by: Xiao Guangrong --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH 3/9] KVM: x86: add pcommit support

Pass PCOMMIT CPU feature to guest to enable PCOMMIT instruction Currently we do not catch pcommit instruction for L1 guest and allow L1 to catch this instruction for L2 The specification locates at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Signed-off-by: Xiao

[PATCH 5/9] KVM: VMX: simplify rdtscp handling in vmx_cpuid_update()

if vmx_rdtscp_supported() is true SECONDARY_EXEC_RDTSCP must have already been set in current vmcs by vmx_secondary_exec_control() Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/vmx.c | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff

[PATCH 4/9] KVM: VMX: drop rdtscp_enabled check in prepare_vmcs02()

SECONDARY_EXEC_RDTSCP set for L2 guest comes from vmcs12 Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/vmx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index b526c61..f7a721e 100644 --- a/arch/x86

[PATCH 1/9] KVM: MMU: fix use uninitialized value

root, leaf; It's true as shadow_walk_init() may stop the loop Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 70c375f..a8a5b8d 100644 --- a/arch

[PATCH 6/9] KVM: VMX: simplify invpcid handling in vmx_cpuid_update()

-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/vmx.c | 19 ++- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 99f638e..0d68140 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -8684,20 +8684,13

[PATCH 8/9] KVM: VMX: introduce set_clear_2nd_exec_ctrl()

It's used to clean up the code Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/vmx.c | 42 +++--- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 4f238b7..58f7b89

[PATCH 7/9] KVM: VMX: unify SECONDARY_VM_EXEC_CONTROL update

Unify the update in vmx_cpuid_update() Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/vmx.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 0d68140..4f238b7 100644 --- a/arch

[PATCH 9/9] KVM: VMX: drop rdtscp_enabled field

Check cpuid bit instead of it Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/cpuid.h | 8 arch/x86/kvm/vmx.c | 19 ++- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index

[PATCH 0/9] KVM: x86: enable cflushopt/clwb/pcommit and simplify code

these three instructions for guest patch 4 ~ patch 9 simplify current VMX code Xiao Guangrong (9): KVM: MMU: fix use uninitialized value KVM: x86: allow guest to use cflushopt anc clwb KVM: x86: add pcommit support KVM: VMX: drop rdtscp_enabled check in prepare_vmcs02() KVM: VMX: simplify

[PATCH 2/9] KVM: x86: allow guest to use cflushopt anc clwb

Pass its CPU feature to guest to enable them in guest These are needed by nvdimm drivers The specification locates at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/cpuid.c | 2 +- 1

Re: [PATCH v2 8/9] KVM: MMU: fully check zero bits for sptes

On 08/05/2015 06:12 PM, Paolo Bonzini wrote: On 05/08/2015 06:04, Xiao Guangrong wrote: - for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) + for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { + leaf = iterator.level; + + if (!root

Re: [PATCH v2 8/9] KVM: MMU: fully check zero bits for sptes

On 08/05/2015 06:12 PM, Paolo Bonzini wrote: On 05/08/2015 06:04, Xiao Guangrong wrote: - for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) + for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { + leaf = iterator.level; + + if (!root

[PATCH v2 2/9] KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c

FNAME(is_rsvd_bits_set) does not depend on guest mmu mode, move it to mmu.c to stop being compiled multiple times Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 8 arch/x86/kvm/paging_tmpl.h | 13 ++--- 2 files changed, 10 insertions(+), 11 deletions(-) diff

[PATCH v2 0/9] KVM: MMU: fix and improve validation of mmio page fault

only check the reserved bits on hardware but also check other bits that spte never used Xiao Guangrong (9): KVM: MMU: fix validation of mmio page fault KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c KVM: MMU: introduce rsvd_bits_validate KVM: MMU: split reset_rsvds_bits_mask KVM:

[PATCH v2 3/9] KVM: MMU: introduce rsvd_bits_validate

These two fields, rsvd_bits_mask and bad_mt_xwr, in "struct kvm_mmu" are used to check if reserved bits set on guest ptes, move them to a data struct so that the approach can be applied to check host shadow page table entries as well Signed-off-by: Xiao Guangrong --- arch/x86/i

[PATCH v2 5/9] KVM: MMU: split reset_rsvds_bits_mask_ept

Since shdow ept page tables and intel nested guest page tables have the same format, split reset_rsvds_bits_mask_ept so that the logic can be reused by later patches which check zero bits on sptes Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 14 ++ 1 file changed, 10

[PATCH v2 6/9] KVM: MMU: introduce the framework to check zero bits on sptes

We have abstracted the data struct and functions which are used to check reserved bit on guest page tables, now we extend the logic to check zero bits on shadow page tables The zero bits on sptes include not only reserved bits on hardware but also the bits sptes nerve used Signed-off-by: Xiao

[PATCH v2 1/9] KVM: MMU: fix validation of mmio page fault

r backport. Full check will be introduced in later patches Reported-by: Pavel Shirshov Tested-by: Pavel Shirshov Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 45 - 1 file changed, 45 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/m

[PATCH v2 8/9] KVM: MMU: fully check zero bits for sptes

but also the bits spte never used, then dump the shadow page table hierarchy if the real bug is detected Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 41 +++-- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch

[PATCH v2 9/9] KVM: VMX: drop ept misconfig check

The logic used to check ept misconfig is completely contained in common reserved bits check for sptes, so it can be removed Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 22 arch/x86/kvm/mmu.h | 1 - arch/x86/kvm/vmx.c | 74

[PATCH v2 4/9] KVM: MMU: split reset_rsvds_bits_mask

Since softmmu & AMD nested shadow page tables and guest page tables have the same format, split reset_rsvds_bits_mask so that the logic can be reused by later patches which check zero bits on sptes Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 26 ++ 1

[PATCH v2 7/9] KVM: MMU: introduce is_shadow_zero_bits_set()

We have the same data struct to check reserved bits on guest page tables and shadow page tables, split is_rsvd_bits_set() so that the logic can be shared between these two paths Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 28 +++- 1 file changed, 19 insertions

Re: [PATCH] KVM: MTRR: Use default type for non-MTRR-covered gfn before WARN_ON

On 08/05/2015 12:58 AM, Alex Williamson wrote: The patch was munged on commit to re-order these tests resulting in excessive warnings when trying to do device assignment. Return to original ordering: https://lkml.org/lkml/2015/7/15/769 Reviewed-by: Xiao Guangrong -- To unsubscribe from

Re: [PATCH 6/9] KVM: MMU: introduce the framework to check reserved bits on sptes

On 08/04/2015 09:23 PM, Paolo Bonzini wrote: On 04/08/2015 15:10, Xiao Guangrong wrote: This should be cpu_has_nx, I think. cpu_has_nx() checks the feature on host CPU, however, this is the shadow page table which completely follow guest's features. E.g, if guest does not execution

Re: [PATCH 6/9] KVM: MMU: introduce the framework to check reserved bits on sptes

On 08/04/2015 08:14 PM, Paolo Bonzini wrote: On 04/08/2015 12:59, Xiao Guangrong wrote: +/* + * the page table on host is the shadow page table for the page + * table in guest or amd nested guest, its mmu features completely + * follow the features in guest. + */ +void

Re: [PATCH 0/9] KVM: MMU: fix and improve validation of mmio page fault

CCed Pavel Shirshov Sorry, git tool missed to CC mail to the person tagged with "Reported-by" and "Tested-by". :( On 08/04/2015 06:59 PM, Xiao Guangrong wrote: Current code validating mmio #PF is buggy, it was spotted by Pavel Shirshov, the bug is that qemu complained wit

[PATCH 2/9] KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c

FNAME(is_rsvd_bits_set) does not depend on guest mmu mode, move it to mmu.c to stop being compiled multiple times Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 8 arch/x86/kvm/paging_tmpl.h | 13 ++--- 2 files changed, 10 insertions(+), 11 deletions(-) diff

[PATCH 4/9] KVM: MMU: split reset_rsvds_bits_mask

Since softmmu & AMD nested shadow page tables and guest page tables have the same format, split reset_rsvds_bits_mask so that the logic can be reused by later patches which check reserved bits on sptes Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 26 ++ 1

[PATCH 0/9] KVM: MMU: fix and improve validation of mmio page fault

s on guest pte to check sptes Xiao Guangrong (9): KVM: MMU: fix validation of mmio page fault KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c KVM: MMU: introduce rsvd_bits_validate KVM: MMU: split reset_rsvds_bits_mask KVM: MMU: split reset_rsvds_bits_mask_ept KVM: MMU: introduce the

[PATCH 1/9] KVM: MMU: fix validation of mmio page fault

r backport. Full check will be introduced in later patches Reported-by: Pavel Shirshov Tested-by: Pavel Shirshov Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 45 - 1 file changed, 45 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/m

[PATCH 3/9] KVM: MMU: introduce rsvd_bits_validate

These two fields, rsvd_bits_mask and bad_mt_xwr, in "struct kvm_mmu" are used to check if reserved bits set on guest ptes, move them to a data struct so that the approach can be applied to check reserved bits on host shadow page table entries Signed-off-by: Xiao Guangrong --- arch/x

[PATCH 6/9] KVM: MMU: introduce the framework to check reserved bits on sptes

We have abstracted the data struct and functions which are used to check reserved bit on guest page tables, now we extend the logic to check reserved bits on shadow page tables Signed-off-by: Xiao Guangrong --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/mmu.c | 51

[PATCH 7/9] KVM: MMU: introduce is_shadow_rsvd_bits_set()

We have the same data struct to check reserved bits on guest page tables and shadow page tables, split is_rsvd_bits_set() so that the logic can be shared between these two paths Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 28 +++- 1 file changed, 19 insertions

[PATCH 8/9] KVM: MMU: fully check reserved bits for sptes

is the real bug is detected Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 41 +++-- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 3f9ce29..6b0e9c9 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86

[PATCH 9/9] KVM: VMX: drop ept misconfig check

The logic used to check ept misconfig is completely contained in common reserved bits check for sptes, so it can be removed Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 22 arch/x86/kvm/mmu.h | 1 - arch/x86/kvm/vmx.c | 74

[PATCH 5/9] KVM: MMU: split reset_rsvds_bits_mask_ept

Since shdow ept page tables and intel nested guest page tables have the same format, split reset_rsvds_bits_mask_ept so that the logic can be reused by later patches which check reserved bits on sptes Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mmu.c | 14 ++ 1 file changed, 10

Re: [PATCH 0/9] KVM: MMU: fix and improve validation of mmio page fault

CCed Pavel Shirshov ru.pc...@gmail.com Sorry, git tool missed to CC mail to the person tagged with Reported-by and Tested-by. :( On 08/04/2015 06:59 PM, Xiao Guangrong wrote: Current code validating mmio #PF is buggy, it was spotted by Pavel Shirshov, the bug is that qemu complained with KVM

[PATCH 5/9] KVM: MMU: split reset_rsvds_bits_mask_ept

Since shdow ept page tables and intel nested guest page tables have the same format, split reset_rsvds_bits_mask_ept so that the logic can be reused by later patches which check reserved bits on sptes Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 14

[PATCH 9/9] KVM: VMX: drop ept misconfig check

The logic used to check ept misconfig is completely contained in common reserved bits check for sptes, so it can be removed Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 22 arch/x86/kvm/mmu.h | 1 - arch/x86/kvm/vmx.c | 74

[PATCH 8/9] KVM: MMU: fully check reserved bits for sptes

is the real bug is detected Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 41 +++-- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 3f9ce29..6b0e9c9 100644 --- a/arch

[PATCH 7/9] KVM: MMU: introduce is_shadow_rsvd_bits_set()

We have the same data struct to check reserved bits on guest page tables and shadow page tables, split is_rsvd_bits_set() so that the logic can be shared between these two paths Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 28

[PATCH 1/9] KVM: MMU: fix validation of mmio page fault

check will be introduced in later patches Reported-by: Pavel Shirshov ru.pc...@gmail.com Tested-by: Pavel Shirshov ru.pc...@gmail.com Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 45 - 1 file changed, 45 deletions

[PATCH 3/9] KVM: MMU: introduce rsvd_bits_validate

These two fields, rsvd_bits_mask and bad_mt_xwr, in struct kvm_mmu are used to check if reserved bits set on guest ptes, move them to a data struct so that the approach can be applied to check reserved bits on host shadow page table entries Signed-off-by: Xiao Guangrong guangrong.x

[PATCH 6/9] KVM: MMU: introduce the framework to check reserved bits on sptes

We have abstracted the data struct and functions which are used to check reserved bit on guest page tables, now we extend the logic to check reserved bits on shadow page tables Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm

[PATCH 2/9] KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c

FNAME(is_rsvd_bits_set) does not depend on guest mmu mode, move it to mmu.c to stop being compiled multiple times Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 8 arch/x86/kvm/paging_tmpl.h | 13 ++--- 2 files changed, 10

[PATCH 4/9] KVM: MMU: split reset_rsvds_bits_mask

Since softmmu AMD nested shadow page tables and guest page tables have the same format, split reset_rsvds_bits_mask so that the logic can be reused by later patches which check reserved bits on sptes Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 26

[PATCH 0/9] KVM: MMU: fix and improve validation of mmio page fault

pte to check sptes Xiao Guangrong (9): KVM: MMU: fix validation of mmio page fault KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c KVM: MMU: introduce rsvd_bits_validate KVM: MMU: split reset_rsvds_bits_mask KVM: MMU: split reset_rsvds_bits_mask_ept KVM: MMU: introduce the framework

Re: [PATCH 6/9] KVM: MMU: introduce the framework to check reserved bits on sptes

On 08/04/2015 09:23 PM, Paolo Bonzini wrote: On 04/08/2015 15:10, Xiao Guangrong wrote: This should be cpu_has_nx, I think. cpu_has_nx() checks the feature on host CPU, however, this is the shadow page table which completely follow guest's features. E.g, if guest does not execution

Re: [PATCH 6/9] KVM: MMU: introduce the framework to check reserved bits on sptes

On 08/04/2015 08:14 PM, Paolo Bonzini wrote: On 04/08/2015 12:59, Xiao Guangrong wrote: +/* + * the page table on host is the shadow page table for the page + * table in guest or amd nested guest, its mmu features completely + * follow the features in guest. + */ +void

Re: [PATCH] KVM: MTRR: Use default type for non-MTRR-covered gfn before WARN_ON

On 08/05/2015 12:58 AM, Alex Williamson wrote: The patch was munged on commit to re-order these tests resulting in excessive warnings when trying to do device assignment. Return to original ordering: https://lkml.org/lkml/2015/7/15/769 Reviewed-by: Xiao Guangrong guangrong.x

[PATCH v2 7/9] KVM: MMU: introduce is_shadow_zero_bits_set()

We have the same data struct to check reserved bits on guest page tables and shadow page tables, split is_rsvd_bits_set() so that the logic can be shared between these two paths Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 28

[PATCH v2 3/9] KVM: MMU: introduce rsvd_bits_validate

These two fields, rsvd_bits_mask and bad_mt_xwr, in struct kvm_mmu are used to check if reserved bits set on guest ptes, move them to a data struct so that the approach can be applied to check host shadow page table entries as well Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com

[PATCH v2 0/9] KVM: MMU: fix and improve validation of mmio page fault

the reserved bits on hardware but also check other bits that spte never used Xiao Guangrong (9): KVM: MMU: fix validation of mmio page fault KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c KVM: MMU: introduce rsvd_bits_validate KVM: MMU: split reset_rsvds_bits_mask KVM: MMU: split

[PATCH v2 5/9] KVM: MMU: split reset_rsvds_bits_mask_ept

Since shdow ept page tables and intel nested guest page tables have the same format, split reset_rsvds_bits_mask_ept so that the logic can be reused by later patches which check zero bits on sptes Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 14

[PATCH v2 2/9] KVM: MMU: move FNAME(is_rsvd_bits_set) to mmu.c

FNAME(is_rsvd_bits_set) does not depend on guest mmu mode, move it to mmu.c to stop being compiled multiple times Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 8 arch/x86/kvm/paging_tmpl.h | 13 ++--- 2 files changed, 10

[PATCH v2 4/9] KVM: MMU: split reset_rsvds_bits_mask

Since softmmu AMD nested shadow page tables and guest page tables have the same format, split reset_rsvds_bits_mask so that the logic can be reused by later patches which check zero bits on sptes Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 26

[PATCH v2 6/9] KVM: MMU: introduce the framework to check zero bits on sptes

We have abstracted the data struct and functions which are used to check reserved bit on guest page tables, now we extend the logic to check zero bits on shadow page tables The zero bits on sptes include not only reserved bits on hardware but also the bits sptes nerve used Signed-off-by: Xiao

[PATCH v2 1/9] KVM: MMU: fix validation of mmio page fault

check will be introduced in later patches Reported-by: Pavel Shirshov ru.pc...@gmail.com Tested-by: Pavel Shirshov ru.pc...@gmail.com Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 45 - 1 file changed, 45 deletions

[PATCH v2 8/9] KVM: MMU: fully check zero bits for sptes

but also the bits spte never used, then dump the shadow page table hierarchy if the real bug is detected Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 41 +++-- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git

[PATCH v2 9/9] KVM: VMX: drop ept misconfig check

The logic used to check ept misconfig is completely contained in common reserved bits check for sptes, so it can be removed Signed-off-by: Xiao Guangrong guangrong.x...@linux.intel.com --- arch/x86/kvm/mmu.c | 22 arch/x86/kvm/mmu.h | 1 - arch/x86/kvm/vmx.c | 74

Re: [PATCH] KVM: x86: rename quirk constants to KVM_X86_QUIRK_*

On 07/23/2015 02:26 PM, Paolo Bonzini wrote: Make them clearly architecture-dependent; the capability is valid for all architectures, but the argument is not. Reviewed-by: Xiao Guangrong Okay, i saw you already have adjusted and merged my patchset, thanks for your work

Re: [PATCH 1/3] KVM: MTRR: fix memory type handling if MTRR is completely disabled

On 07/23/2015 02:21 PM, Paolo Bonzini wrote: On 16/07/2015 06:10, Alex Williamson wrote: On Thu, 2015-07-16 at 03:25 +0800, Xiao Guangrong wrote: From: Xiao Guangrong Currently code uses default memory type if MTRR is fully disabled, fix it by using UC instead Signed-off-by: Xiao

Re: [PATCH 3/3] KVM: x86: quirkily apply WB to all memory if cache is disabled

On 07/23/2015 01:56 PM, Paolo Bonzini wrote: On 15/07/2015 21:25, Xiao Guangrong wrote: From: Xiao Guangrong Current firmware depends on WB to fast boot, please refer to https://lkml.org/lkml/2015/7/12/115 Let's us WB if CR0.CD is set to make this kind of firmware happy

Re: [PATCH 3/3] KVM: x86: quirkily apply WB to all memory if cache is disabled

On 07/23/2015 01:56 PM, Paolo Bonzini wrote: On 15/07/2015 21:25, Xiao Guangrong wrote: From: Xiao Guangrong guangrong.x...@intel.com Current firmware depends on WB to fast boot, please refer to https://lkml.org/lkml/2015/7/12/115 Let's us WB if CR0.CD is set to make this kind

Re: [PATCH 1/3] KVM: MTRR: fix memory type handling if MTRR is completely disabled

On 07/23/2015 02:21 PM, Paolo Bonzini wrote: On 16/07/2015 06:10, Alex Williamson wrote: On Thu, 2015-07-16 at 03:25 +0800, Xiao Guangrong wrote: From: Xiao Guangrong guangrong.x...@intel.com Currently code uses default memory type if MTRR is fully disabled, fix it by using UC instead

Re: [PATCH] KVM: x86: rename quirk constants to KVM_X86_QUIRK_*

On 07/23/2015 02:26 PM, Paolo Bonzini wrote: Make them clearly architecture-dependent; the capability is valid for all architectures, but the argument is not. Reviewed-by: Xiao Guangrong guangrong.x...@linux.intel.com Okay, i saw you already have adjusted and merged my patchset, thanks

Re: MTRR setup in OVMF [was: PATCH v3 01/10 KVM: MMU: fix decoding cache type from MTRR]

Hi, I have posted the pachset to make OVMF happy and have CCed you guys, could you please check it if it works for you? On 07/15/2015 05:15 AM, Paolo Bonzini wrote: The long delay that Alex reported (for the case when all guest memory was set to UC up-front) is due to the fact that the SEC

[PATCH 3/3] KVM: x86: quirkily apply WB to all memory if cache is disabled

From: Xiao Guangrong Current firmware depends on WB to fast boot, please refer to https://lkml.org/lkml/2015/7/12/115 Let's us WB if CR0.CD is set to make this kind of firmware happy This quirk can be dropped by using KVM_ENABLE_CAP API with KVM_CAP_DISABLE_QUIRKS if the broken firmware

[PATCH 1/3] KVM: MTRR: fix memory type handling if MTRR is completely disabled

From: Xiao Guangrong Currently code uses default memory type if MTRR is fully disabled, fix it by using UC instead Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mtrr.c | 21 - 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/mtrr.c b/arch/x86/kvm

[PATCH 2/3] KVM: MTRR: simplify kvm_mtrr_get_guest_memory_type

From: Xiao Guangrong kvm_mtrr_get_guest_memory_type never returns -1 which is implied in the current code since if @type = -1 (means no MTRR contains the range), iter.partial_map must be true Simplify the code to indicate this fact Signed-off-by: Xiao Guangrong --- arch/x86/kvm/mtrr.c | 19

[PATCH 2/3] KVM: MTRR: simplify kvm_mtrr_get_guest_memory_type

From: Xiao Guangrong guangrong.x...@intel.com kvm_mtrr_get_guest_memory_type never returns -1 which is implied in the current code since if @type = -1 (means no MTRR contains the range), iter.partial_map must be true Simplify the code to indicate this fact Signed-off-by: Xiao Guangrong

[PATCH 1/3] KVM: MTRR: fix memory type handling if MTRR is completely disabled

From: Xiao Guangrong guangrong.x...@intel.com Currently code uses default memory type if MTRR is fully disabled, fix it by using UC instead Signed-off-by: Xiao Guangrong guangrong.x...@intel.com --- arch/x86/kvm/mtrr.c | 21 - 1 file changed, 20 insertions(+), 1 deletion

Re: MTRR setup in OVMF [was: PATCH v3 01/10 KVM: MMU: fix decoding cache type from MTRR]

Hi, I have posted the pachset to make OVMF happy and have CCed you guys, could you please check it if it works for you? On 07/15/2015 05:15 AM, Paolo Bonzini wrote: The long delay that Alex reported (for the case when all guest memory was set to UC up-front) is due to the fact that the SEC

[PATCH 3/3] KVM: x86: quirkily apply WB to all memory if cache is disabled

From: Xiao Guangrong guangrong.x...@intel.com Current firmware depends on WB to fast boot, please refer to https://lkml.org/lkml/2015/7/12/115 Let's us WB if CR0.CD is set to make this kind of firmware happy This quirk can be dropped by using KVM_ENABLE_CAP API with KVM_CAP_DISABLE_QUIRKS

Re: [PATCH v3 01/10] KVM: MMU: fix decoding cache type from MTRR

On 07/13/2015 11:13 PM, Paolo Bonzini wrote: On 13/07/2015 16:45, Xiao Guangrong wrote: +/* MTRR is completely disabled, use UC for all of physical memory. */ +if (!(mtrr_state->enabled & 0x2)) +return MTRR_TYPE_UNCACHABLE; actually disappears in commit fa61213746

Re: [PATCH v3 01/10] KVM: MMU: fix decoding cache type from MTRR

On 07/13/2015 03:32 PM, Paolo Bonzini wrote: I'm seeing a significant regression in boot performance on Intel hardware with assigned devices that bisects back to this patch. There's a long delay with Seabios between the version splash and execution of option ROMs, and a _very_ long delay with

Re: [PATCH v3 01/10] KVM: MMU: fix decoding cache type from MTRR

On 07/13/2015 03:32 PM, Paolo Bonzini wrote: I'm seeing a significant regression in boot performance on Intel hardware with assigned devices that bisects back to this patch. There's a long delay with Seabios between the version splash and execution of option ROMs, and a _very_ long delay with

Re: [PATCH v3 01/10] KVM: MMU: fix decoding cache type from MTRR

On 07/13/2015 11:13 PM, Paolo Bonzini wrote: On 13/07/2015 16:45, Xiao Guangrong wrote: +/* MTRR is completely disabled, use UC for all of physical memory. */ +if (!(mtrr_state-enabled 0x2)) +return MTRR_TYPE_UNCACHABLE; actually disappears in commit fa61213746a7 (KVM: MTRR

Re: [PATCH v3 01/10] KVM: MMU: fix decoding cache type from MTRR

On 07/13/2015 01:33 AM, Alex Williamson wrote: On Wed, 2015-05-13 at 14:42 +0800, Xiao Guangrong wrote: There are some bugs in current get_mtrr_type(); 1: bit 1 of mtrr_state->enabled is corresponding bit 11 of IA32_MTRR_DEF_TYPE MSR which completely control MTRR's enablem

Re: [PATCH v3 01/10] KVM: MMU: fix decoding cache type from MTRR

On 07/13/2015 01:33 AM, Alex Williamson wrote: On Wed, 2015-05-13 at 14:42 +0800, Xiao Guangrong wrote: There are some bugs in current get_mtrr_type(); 1: bit 1 of mtrr_state-enabled is corresponding bit 11 of IA32_MTRR_DEF_TYPE MSR which completely control MTRR's enablement

Re: [PATCH] KVM: svm: remove KVM_QUIRK_CD_NW_CLEARED quirk

tables. This behavior is consistent with VMX, where CD/NW are not touched by vmentry/vmexit. Note that buggy firmware that does not clear CD/NW is _seriously_ old: SeaBIOS for example has been doing it since October 2008. Reviewed-by: Xiao Guangrong -- To unsubscribe from this list: send

Re: [PATCH 2/4] KVM: SVM: use NPT page attributes

On 07/10/2015 06:47 PM, Paolo Bonzini wrote: On 10/07/2015 03:19, Xiao Guangrong wrote: yes, this is correct. QEMU still does not have support for disabling "quirks", so gCR0.CD is currently hidden on SVM. I would like to include this series in 4.2, while for 4.3 I will disable

Re: [PATCH 2/4] KVM: SVM: use NPT page attributes

On 07/10/2015 06:47 PM, Paolo Bonzini wrote: On 10/07/2015 03:19, Xiao Guangrong wrote: yes, this is correct. QEMU still does not have support for disabling quirks, so gCR0.CD is currently hidden on SVM. I would like to include this series in 4.2, while for 4.3 I will disable the quirk

Re: [PATCH] KVM: svm: remove KVM_QUIRK_CD_NW_CLEARED quirk

tables. This behavior is consistent with VMX, where CD/NW are not touched by vmentry/vmexit. Note that buggy firmware that does not clear CD/NW is _seriously_ old: SeaBIOS for example has been doing it since October 2008. Reviewed-by: Xiao Guangrong guangrong.x...@linux.intel.com

Re: [PATCH 2/4] KVM: SVM: use NPT page attributes

On 07/09/2015 11:18 PM, Paolo Bonzini wrote: On 09/07/2015 04:30, Xiao Guangrong wrote: diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 602b974a60a6..0f125c1860ec 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -1085,6 +1085,47 @@ static u64 svm_compute_tsc_offset

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