From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao <y...@rock-chips.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6:
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes
com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Split all DTS changes, and provide backward compatibility. Mark old
properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gp
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7:
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6:
- Simply the co
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile fail
m>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
hpd when hpd detect failed.
Changes in v2: No
Add dt binding documentation for rockchip display port PHY.
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (R
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Tested-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
Hi Javier,
On 10/20/2015 05:48 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/20/2015 04:10 AM, Yakir Yang wrote:
Hi Javier,
On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/10/2015 05:35 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP
Hi Javier,
On 10/20/2015 05:48 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/20/2015 04:10 AM, Yakir Yang wrote:
Hi Javier,
On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/10/2015 05:35 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP
Hi Javier,
On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/10/2015 05:35 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge
Hi Javier,
On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/10/2015 05:35 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge
Hi Javierm
On 10/13/2015 05:21 PM, Javier Martinez Canillas wrote:
Hello Yakir,
Sorry for the delay but I was on holidays.
On 10/10/2015 04:31 PM, Yakir Yang wrote:
Hi Javier,
[snip]
Maybe you can email me the method the run mainline kernel on Peach
Pit, so I can debug the analogix_dp
Hi Javierm
On 10/13/2015 05:21 PM, Javier Martinez Canillas wrote:
Hello Yakir,
Sorry for the delay but I was on holidays.
On 10/10/2015 04:31 PM, Yakir Yang wrote:
Hi Javier,
[snip]
Maybe you can email me the method the run mainline kernel on Peach
Pit, so I can debug the analogix_dp
Hi Kishon,
On 10/13/2015 06:28 AM, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
This phy driver is binded with the Rockchip DisplayPort
driver, here are the brief properties:
edp_phy: edp-phy@ff770274 {
compatible
Hi Kishon
On 10/12/2015 11:02 PM, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly
On 10/12/2015 02:54 PM, Krzysztof Kozlowski wrote:
On 12.10.2015 13:29, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT
On 10/12/2015 02:54 PM, Krzysztof Kozlowski wrote:
On 12.10.2015 13:29, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT
Hi Kishon
On 10/12/2015 11:02 PM, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly
Hi Kishon,
On 10/13/2015 06:28 AM, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
This phy driver is binded with the Rockchip DisplayPort
driver, here are the brief properties:
edp_phy: edp-phy@ff770274 {
compatible
-by: Yakir Yang
---
*just add a note that this is v7 of only fifth patch.*
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -EOVERFLOW error (Krzysztof
On 10/12/2015 11:51 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 11:43, Yakir Yang wrote:
On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 09:37, Yakir Yang wrote:
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can
On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 09:37, Yakir Yang wrote:
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup
On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 09:37, Yakir Yang wrote:
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video
-by: Yakir Yang <y...@rock-chips.com>
---
*just add a note that this is v7 of only fifth patch.*
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -
On 10/12/2015 11:51 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 11:43, Yakir Yang wrote:
On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
On 12.10.2015 09:37, Yakir Yang wrote:
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
Both hsync/vsync polarity and interlace mode can
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit me
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes i
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
directly, but we can take
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Fix compiled error (Heiko)
- Using
clock-names = "24m";
#phy-cells = <0>;
};
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
elemets in docume
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Remove
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Yakir Yang
---
Changes in v6:
- Fix Peach Pit hpd property name error:
- hpd-gpio = < 6 0>;
+ hpd-gpios = < 6 0>;
C
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5
-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool" to get backword timing valu
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v6:
- Fix the wrong code in previous series
e readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i2c(...
...);
+ retval =
+ exynos_dp_read_bytes_from_i2c(..);
- Get panel node with remote-endpoint method, and create devicetree bin
Hi Javier,
On 10/08/2015 08:40 AM, Yakir Yang wrote:
On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
On 10/07/2015 01:05 PM, Yakir Yang wrote:
On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
On 10/07/2015 11:02 AM, Yakir Yang wrote:
On 10/07/2015 04:46 PM, Javier Martinez
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6:
- Fix the wron
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of do
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5:
clock-names = "24m";
#phy-cells = <0>;
};
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Cha
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count lim
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski <k.kozlow...@samsung.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6:
- Fix Peach Pit hpd property name error:
- hpd-
From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao <y...@rock-chips.com>
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
e readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i2c(...
...);
+ retval =
+ exynos_dp_read_bytes_from_i2c(..);
- Get panel node with remote-endpoint method, and create devicetree bin
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr va
Hi Javier,
On 10/08/2015 08:40 AM, Yakir Yang wrote:
On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
On 10/07/2015 01:05 PM, Yakir Yang wrote:
On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
On 10/07/2015 11:02 AM, Yakir Yang wrote:
On 10/07/2015 04:46 PM, Javier Martinez
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP h
-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property
Oh, I haven't noticed that those patches already have been
merged into linux-next :-)
On 10/08/2015 03:17 AM, Russell King - ARM Linux wrote:
On Wed, Oct 07, 2015 at 06:40:11PM +0800, Yakir Yang wrote:
On 10/07/2015 05:48 PM, Russell King - ARM Linux wrote:
On Wed, Oct 07, 2015 at 12:05
Oh, I haven't noticed that those patches already have been
merged into linux-next :-)
On 10/08/2015 03:17 AM, Russell King - ARM Linux wrote:
On Wed, Oct 07, 2015 at 06:40:11PM +0800, Yakir Yang wrote:
On 10/07/2015 05:48 PM, Russell King - ARM Linux wrote:
On Wed, Oct 07, 2015 at 12:05
Hi Javier,
On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 01:05 PM, Yakir Yang wrote:
Hi Javier,
On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 11:02 AM, Yakir Yang wrote:
Hi Javier,
On 10/07/2015 04:46 PM, Javier
On 10/07/2015 05:18 PM, Russell King - ARM Linux wrote:
On Wed, Oct 07, 2015 at 11:50:53AM +0800, Yakir Yang wrote:
On 08/09/2015 12:04 AM, Russell King wrote:
On a mode set, DRM makes the following sequence of calls:
* for_each_encoder
* bridge mode_fixup
* encoder mode_fixup
Hi Javier,
On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 08:25 AM, Yakir Yang wrote:
Hi all,
Friendly ping. :)
Best regards,
- Yakir
Do you have a tree that I can use to test these patches?
Wow, thanks a lot, I do have a tree on github
Hi all,
Friendly ping. :)
Best regards,
- Yakir
On 09/22/2015 03:20 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288
Hi all,
Friendly ping. :)
Best regards,
- Yakir
On 09/22/2015 03:20 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288
Hi Javier,
On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 08:25 AM, Yakir Yang wrote:
Hi all,
Friendly ping. :)
Best regards,
- Yakir
Do you have a tree that I can use to test these patches?
Wow, thanks a lot, I do have a tree on github
Hi Javier,
On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 01:05 PM, Yakir Yang wrote:
Hi Javier,
On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
Hello Yakir,
On 10/07/2015 11:02 AM, Yakir Yang wrote:
Hi Javier,
On 10/07/2015 04:46 PM, Javier
On 10/07/2015 05:18 PM, Russell King - ARM Linux wrote:
On Wed, Oct 07, 2015 at 11:50:53AM +0800, Yakir Yang wrote:
On 08/09/2015 12:04 AM, Russell King wrote:
On a mode set, DRM makes the following sequence of calls:
* for_each_encoder
* bridge mode_fixup
* encoder mode_fixup
On 08/09/2015 12:04 AM, Russell King wrote:
On a mode set, DRM makes the following sequence of calls:
* for_each_encoder
* bridge mode_fixup
* encoder mode_fixup
* crtc mode_fixup
* for_each_encoder
* bridge disable
* encoder prepare
* bridge
eply.
Tested-by: Yakir Yang
- Yakir
---
drivers/gpu/drm/bridge/dw_hdmi.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c
index 7f764716f3c4..578d7362cd65 100644
--- a/drivers/gpu/drm/bridge/dw_hd
and I have backport those 06/12 & 07/12 to chrome-3.14
tree, audio still works rightly when I changing the display resolutions.
So I would like to share:
Tested-by: Yakir Yang
Besides, Andy, would you like to share your ACK here :)
Best regards,
- Yakir
---
drivers/gpu/d
before, feel better about
this one, and I have backport those 06/12 & 07/12 to chrome-3.14
tree, audio still works rightly when I changing the display resolutions.
So I would like to share:
Tested-by: Yakir Yang <y...@rock-chips.com>
Besides, Andy, would you like to share your ACK here :)
.org.uk>
Some to 06/12 reply.
Tested-by: Yakir Yang <y...@rock-chips.com>
- Yakir
---
drivers/gpu/drm/bridge/dw_hdmi.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c
in
On 08/09/2015 12:04 AM, Russell King wrote:
On a mode set, DRM makes the following sequence of calls:
* for_each_encoder
* bridge mode_fixup
* encoder mode_fixup
* crtc mode_fixup
* for_each_encoder
* bridge disable
* encoder prepare
* bridge
Hi Krzysztof,
On 09/30/2015 04:26 PM, Krzysztof Kozlowski wrote:
On 30.09.2015 17:20, Yakir Yang wrote:
Hi Krzysztof,
On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
On 30.09.2015 16:19, Yakir Yang wrote:
Hi Krzysztof,
On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16
Hi Krzysztof,
On 09/30/2015 01:39 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:43, Yakir Yang wrote:
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from
Hi Krzysztof,
On 09/30/2015 01:22 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:34, Yakir Yang wrote:
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Resequence
Hi Krzysztof,
On 09/30/2015 01:17 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:29, Yakir Yang wrote:
Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.
Beside the new analogix_dp driver
Hi Krzysztof,
On 09/30/2015 01:39 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:43, Yakir Yang wrote:
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from
Hi Krzysztof,
On 09/30/2015 01:17 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:29, Yakir Yang wrote:
Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.
Beside the new analogix_dp driver
Hi Krzysztof,
On 09/30/2015 01:22 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16:34, Yakir Yang wrote:
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
C
Hi Krzysztof,
On 09/30/2015 04:26 PM, Krzysztof Kozlowski wrote:
On 30.09.2015 17:20, Yakir Yang wrote:
Hi Krzysztof,
On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
On 30.09.2015 16:19, Yakir Yang wrote:
Hi Krzysztof,
On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
On 22.09.2015 16
On 09/29/2015 05:55 PM, Yakir Yang wrote:
On 09/29/2015 05:28 PM, Sjoerd Simons wrote:
When doing the initial setup both the hclk and the aclk need to be
enabled otherwise the board will simply hang. This only occurs when
building the vop driver as a module, when its built-in the initial
shuts of unused clocks
(including the aclk).
While there also switch to doing prepare and enable in one step rather
then separate steps to reduce the amount of code required.
Signed-off-by: Sjoerd Simons
Looks good and test on chromeos-3.14 tree, no problem, so
Tested-by: Yakir Yang
On 09/29/2015 05:55 PM, Yakir Yang wrote:
On 09/29/2015 05:28 PM, Sjoerd Simons wrote:
When doing the initial setup both the hclk and the aclk need to be
enabled otherwise the board will simply hang. This only occurs when
building the vop driver as a module, when its built-in the initial
em, so
Tested-by: Yakir Yang <y...@rock-chips.com>
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 +++--
1 file changed, 14 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.
Changes in v3:
- m
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes i
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag. (Thierry)
Changes
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