On Mon, Jan 18, 2021 at 08:31:12PM +0100, Borislav Petkov wrote:
> On Sat, Jan 16, 2021 at 02:33:53PM +0000, Yazen Ghannam wrote:
> > +static struct {
> > + u32 base, limit;
> > +} f17h_scrub_regs = {F17H_M30H_SCR_BASE_ADDR, F17H_M30H_SCR_LIMIT_ADDR};
>
> Why n
On Mon, Jan 18, 2021 at 04:30:58AM +0300, WGH wrote:
> On 16/01/2021 17:33, Yazen Ghannam wrote:
> > From: Yazen Ghannam
> >
> > The Family 17h scrubber registers moved to different offset starting
> > with Model 30h. The new register offsets are used for all currently
From: Yazen Ghannam
The Family 17h scrubber registers moved to different offset starting
with Model 30h. The new register offsets are used for all currently
available models since then.
Use the new register addresses as the defaults.
Set the proper scrub register addresses during module init
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 76e2fc63ca40977af893b724b00cc2f8e9ce47a4
Gitweb:
https://git.kernel.org/tip/76e2fc63ca40977af893b724b00cc2f8e9ce47a4
Author:Yazen Ghannam
AuthorDate:Mon, 11 Jan 2021 11:04:29 +01:00
From: Yazen Ghannam
Give these messages a debug severity as they are really only useful to
the module developers.
Also, drop the "(broken BIOS?)" phrase, since this can cause churn for
BIOS folks. The PCI IDs needed by the module, at least on modern systems,
are fixed in hardware.
ove, can this be changed to the following?
if (pvt->fam < 0x10 || pvt->fam >= 0x17)
> + return 0;
> + return attr->mode;
> +}
> +
Everything else looks good to me.
Reviewed-by: Yazen Ghannam
Thanks,
Yazen
he function static and shorten
> static function names.
>
> No functional changes.
>
> Signed-off-by: Borislav Petkov
Reviewed-by: Yazen Ghannam
Thanks,
Yazen
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: 8de0c9917cc1297bc5543b61992d5bdee4ce621a
Gitweb:
https://git.kernel.org/tip/8de0c9917cc1297bc5543b61992d5bdee4ce621a
Author:Yazen Ghannam
AuthorDate:Mon, 09 Nov 2020 21:06:58
Committer
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: db970bd231c2264a062e0de4dcf4ead5e6669e7a
Gitweb:
https://git.kernel.org/tip/db970bd231c2264a062e0de4dcf4ead5e6669e7a
Author:Yazen Ghannam
AuthorDate:Mon, 09 Nov 2020 21:06:57
Committer
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: cb09a379724d299c603a7a79f444f52a9a75b8d2
Gitweb:
https://git.kernel.org/tip/cb09a379724d299c603a7a79f444f52a9a75b8d2
Author:Yazen Ghannam
AuthorDate:Mon, 09 Nov 2020 21:06:59
Committer
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: 028c221ed1904af9ac3c5162ee98f48966de6b3d
Gitweb:
https://git.kernel.org/tip/028c221ed1904af9ac3c5162ee98f48966de6b3d
Author:Yazen Ghannam
AuthorDate:Mon, 09 Nov 2020 21:06:56
Committer
From: Yazen Ghannam
The edac_mce_amd module calls decode_dram_ecc() on AMD Family17h and
later systems. This function is used in amd64_edac_mod to do
system-specific decoding for DRAM ECC errors. The function takes a
"NodeId" as a parameter.
In AMD documentation, NodeId is used t
From: Yazen Ghannam
CPUID Leaf 0x1F defines a DIE_TYPE level, but CPUID Leaf 0xB does not.
However, detect_extended_topology() will set struct
cpuinfo_x86.cpu_die_id regardless of whether a valid Die ID was found.
Only set cpu_die_id if a DIE_TYPE level is found. CPU topology code may
use
From: Yazen Ghannam
The Last Level Cache ID is returned by amd_get_nb_id(). In practice,
this value is the same as the AMD NodeId for callers of this function.
The NodeId is saved in struct cpuinfo_x86.cpu_die_id.
Replace calls to amd_get_nb_id() with the logical CPU's cpu_die_id and
remove
From: Yazen Ghannam
AMD systems provide a "NodeId" value that represents a global ID
indicating to which "Node" a logical CPU belongs. The "Node" is a
physical structure equivalent to a Die, and it should not be confused
with logical structures like NUMA nodes.
From: Yazen Ghannam
AMD-based systems currently use a "NodeId" when referencing a
software-visible hardware structure. This may be referred to as a "Die"
in x86 documentation, "Node" in some AMD documentation, and "Package" in
Linux documentation.
Recentl
From: Yazen Ghannam
AMD Family 19h Models 20h-2Fh use the same PCI IDs as Family 17h Models
70h-7Fh. The same family ops and number of channels also apply.
Use the Family17h Model 70h family_type and ops for Family 19h Models
20h-2Fh. Update the controller name to match the system.
Signed-off
On Mon, Sep 28, 2020 at 08:14:07PM +0200, Borislav Petkov wrote:
> On Mon, Sep 28, 2020 at 10:53:50AM -0500, Yazen Ghannam wrote:
>
> > I agree that the translation code is implementation-specific and applies
> > only to DRAM ECC errors, so it make sense to have it in amd64_
On Mon, Sep 28, 2020 at 11:47:59AM +0200, Borislav Petkov wrote:
> On Fri, Sep 25, 2020 at 02:51:27PM -0500, Yazen Ghannam wrote:
>
> > The address translation needs to be done before the notfiers that need
> > it, and EDAC comes after all of them. There's also the case
On Fri, Sep 25, 2020 at 09:22:31AM +0200, Borislav Petkov wrote:
> On Wed, Sep 23, 2020 at 11:25:10AM -0500, Yazen Ghannam wrote:
> > I don't remember the original reason, and I was recently asked about
> > this code living in a module. I did some looking after this ask, and I
&g
On Fri, Sep 25, 2020 at 09:54:06AM +0900, Punit Agrawal wrote:
> Borislav Petkov writes:
>
> > On Thu, Sep 24, 2020 at 12:23:27PM -0500, Smita Koralahalli Channabasappa
> > wrote:
> >> > Even though it's not defined in the UEFI spec, it doesn't mean a
> >> > structure definition cannot be
On Wed, Sep 23, 2020 at 10:20:39AM +0200, Borislav Petkov wrote:
> On Thu, Sep 03, 2020 at 08:01:44PM +0000, Yazen Ghannam wrote:
> > From: Muralidhara M K
> >
> > Add support for new memory interleaving modes used in current AMD systems.
> >
> > Check if t
On Wed, Sep 23, 2020 at 10:05:56AM +0200, Borislav Petkov wrote:
> On Thu, Sep 03, 2020 at 08:01:42PM +0000, Yazen Ghannam wrote:
> > From: Yazen Ghannam
> >
> > Remove the "tmp" variable used to save register values. Save the values
> > in existing variable
On Thu, Sep 17, 2020 at 06:40:48PM +0200, Borislav Petkov wrote:
> On Thu, Sep 17, 2020 at 11:20:53AM -0500, Yazen Ghannam wrote:
> > But newer systems support CPUID Leaf 0xB, so cpu_die_id will get
> > explicitly set by detect_extended_topology(). The value set is
> > d
On Thu, Sep 17, 2020 at 12:37:20PM +0200, Borislav Petkov wrote:
> On Wed, Sep 16, 2020 at 02:51:52PM -0500, Yazen Ghannam wrote:
> > What do you think?
>
> Yeah, forget logical_proc_id - the galactic senate of x86 maintainers
> said that we're keeping that for when BI
On Tue, Sep 15, 2020 at 10:35:15AM +0200, Borislav Petkov wrote:
...
> > Yeah, I think example 4b works here. The mismatch though is with
> > phys_proc_id and package on AMD systems. You can see above that
> > phys_proc_id gives a socket number, and the AMD NodeId gives a package
> > number.
>
>
On Thu, Sep 10, 2020 at 12:14:43PM +0200, Borislav Petkov wrote:
> On Wed, Sep 09, 2020 at 03:17:55PM -0500, Yazen Ghannam wrote:
> > We need to access specific instances of hardware registers in the
> > Northbridge or Data Fabric. The code in arch/x86/kernel/amd_nb.c does
> &
On Wed, Sep 09, 2020 at 08:06:47PM +0200, Borislav Petkov wrote:
> On Thu, Sep 03, 2020 at 08:01:37PM +0000, Yazen Ghannam wrote:
> > From: Yazen Ghannam
> >
> > AMD systems provide a "NodeId" value that represents a global ID
> > indicating to which &q
From: Yazen Ghannam
AMD systems provide a "NodeId" value that represents a global ID
indicating to which "Node" a logical CPU belongs. The "Node" is a
physical structure equivalent to a Die, and it should not be confused
with logical structures like NUMA node. Logic
From: Yazen Ghannam
The Last Level Cache ID is returned by amd_get_nb_id(). In practice,
this value is the same as the AMD NodeId for callers of this function.
The NodeId is saved in struct cpuinfo_x86.node_id.
Replace calls to amd_get_nb_id() with the logical CPU's node_id and
remove
From: Yazen Ghannam
...so that bitfield extraction can be done together to simplify future
patches.
Signed-off-by: Yazen Ghannam
---
Link:
https://lkml.kernel.org/r/20200814191449.183998-3-yazen.ghan...@amd.com
v1 -> v2:
* New patch based on comments for v1 Patch 2.
arch/x86/kernel/cpu/
From: Yazen Ghannam
Remove the "tmp" variable used to save register values. Save the values
in existing variables, if possible.
The register values are 32 bits. Use separate "reg_" variables to hold
the register values if the existing variable sizes doesn't match
on the interleaving option used.
Fixes: 6e846239e548 ("EDAC/amd64: Add Family 17h Model 30h PCI IDs")
Signed-off-by: Muralidhara M K
Co-developed-by: Naveen Krishna Chtradhi
Signed-off-by: Naveen Krishna Chtradhi
Co-developed-by: Yazen Ghannam
Signed-off-by: Yazen Ghannam
---
Link:
https://lkml.
From: Yazen Ghannam
Define macros to get individual bits and bitfields. Use these to make
the code more readable.
Signed-off-by: Yazen Ghannam
---
Link:
https://lkml.kernel.org/r/20200814191449.183998-3-yazen.ghan...@amd.com
v1 -> v2:
* New patch based on comments for v1 Patch 2.
arch/
From: Yazen Ghannam
Replace raw register offset values in the AMD address translation code
with named definitions.
Also, drop comments that only note the register names.
Signed-off-by: Yazen Ghannam
---
Link:
https://lkml.kernel.org/r/20200814191449.183998-3-yazen.ghan...@amd.com
v1 ->
From: Yazen Ghannam
This patchset includes updates for the MCA Address Translation process
on recent AMD systems.
Patches 1 & 3:
Fixes an input to the address translation function. The translation
requires a physical Die ID (NodeId in AMD documentation) rather than a
logicial NUMA nod
From: Yazen Ghannam
The edac_mce_amd module calls decode_dram_ecc() on AMD Family17h and
later systems. This function is used in amd64_edac_mod to do
system-specific decoding for DRAM ECC errors. The function takes a
"NodeId" as a parameter.
In AMD documentation, NodeId is used t
On Fri, Aug 28, 2020 at 03:33:31PM -0500, Smita Koralahalli wrote:
...
> +int apei_mce_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64
> lapic_id)
> +{
> + const u64 *i_mce = ((const void *) (ctx_info + 1));
> + unsigned int cpu;
> + struct mce m;
> +
> + if
binary. However, in the case where it doesn't fit,
an additional page (4kB) of memory will be added to the binary to
accommodate the extra data.
Signed-off-by: Akshay Gupta
[ Adjust commit message and code comment. ]
Signed-off-by: Yazen Ghannam
---
Link:
https://lkml.kernel.org/r
On Thu, Aug 20, 2020 at 06:15:15PM +, Luck, Tony wrote:
> >> How much does vmlinux size grow with your change?
> >>
> >
> > It seems to get smaller.
> >
> > -rwxrwxr-x 1 yghannam yghannam 807634088 Aug 20 17:51 vmlinux-32banks
> > -rwxrwxr-x 1 yghannam yghannam 807634072 Aug 20 17:50
On Thu, Aug 20, 2020 at 07:15:18PM +0200, Borislav Petkov wrote:
> On Thu, Aug 20, 2020 at 05:06:24PM +0000, Yazen Ghannam wrote:
> > From: Akshay Gupta
> >
> > ...because future AMD systems will support up to 64 MCA banks per CPU.
> >
> > MAX_NR_BANKS is
with 32 or
fewer MCA banks per CPU.
Signed-off-by: Akshay Gupta
[ Adjust commit message and code comment. ]
Signed-off-by: Yazen Ghannam
---
arch/x86/include/asm/mce.h | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
The following commit has been merged into the ras/core branch of tip:
Commit-ID: 368d1887200d68075c064a62a9aa191168cf1eed
Gitweb:
https://git.kernel.org/tip/368d1887200d68075c064a62a9aa191168cf1eed
Author:Yazen Ghannam
AuthorDate:Mon, 20 Jul 2020 14:53:53
Committer
On Sat, Aug 15, 2020 at 11:13:36AM +0200, Ingo Molnar wrote:
>
> * Yazen Ghannam wrote:
>
> > + /* Read D18F1x208 (System Fabric ID Mask 0). */
> > + if (amd_df_indirect_read(nid, 1, 0x208, umc, ))
> > + goto out_err;
> > +
> > +
The following commit has been merged into the ras/core branch of tip:
Commit-ID: 5f2c67bd0f8a470a12c38a8786c42c043e100014
Gitweb:
https://git.kernel.org/tip/5f2c67bd0f8a470a12c38a8786c42c043e100014
Author:Yazen Ghannam
AuthorDate:Mon, 20 Jul 2020 14:53:53
Committer
On Mon, Aug 17, 2020 at 11:40:07AM +0200, Borislav Petkov wrote:
> On Mon, Jul 20, 2020 at 02:53:53PM +0000, Yazen Ghannam wrote:
> > From: Yazen Ghannam
> >
> > The Extended Error Code Bitmap (xec_bitmap) for a Scalable MCA bank type
> > was intended to be used
On Sat, Aug 15, 2020 at 10:42:12AM +0200, Ingo Molnar wrote:
>
> * Yazen Ghannam wrote:
>
> > From: Yazen Ghannam
> >
> > The edac_mce_amd module calls decode_dram_ecc() on AMD Family17h and
> > later systems. This function is used in amd64_edac_mod to do
>
From: Yazen Ghannam
The edac_mce_amd module calls decode_dram_ecc() on AMD Family17h and
later systems. This function is used in amd64_edac_mod to do
system-specific decoding for DRAM ECC errors. The function takes a
"NodeId" as a parameter.
In AMD documentation, NodeId is used t
on the interleaving option used.
Fixes: 6e846239e548 ("EDAC/amd64: Add Family 17h Model 30h PCI IDs")
Signed-off-by: Muralidhara M K
Co-developed-by: Naveen Krishna Chtradhi
Signed-off-by: Naveen Krishna Chtradhi
Co-developed-by: Yazen Ghannam
Signed-off-by: Yazen Ghannam
---
arch/x86/kernel/cpu
From: Yazen Ghannam
This patchset includes updates for the MCA Address Translation process
on recent AMD systems.
Patch 1:
Fixes an input to the address translation function. The translation
requires a physical Die ID (NodeId in AMD documentation) rather than a
logicial NUMA node ID
On Sun, Aug 09, 2020 at 12:35:59PM +0800, Feng zhou wrote:
> From: zhoufeng
>
> The edac_mce_amd module calls decode_dram_ecc() on AMD Family17h and
> later systems. This function is used in amd64_edac_mod to do
> system-specific decoding for DRAM ECC errors. The function takes a
> "NodeId" as a
From: Yazen Ghannam
The Extended Error Code Bitmap (xec_bitmap) for a Scalable MCA bank type
was intended to be used by the kernel to filter out invalid error codes
on a system. However, this is unnecessary because the hardware will only
report valid error codes.
Remove the xec_bitmap field
From: Yazen Ghannam
A few existing MCA bank types will have new error types in future SMCA
systems.
Add the descriptions for the new error types.
Signed-off-by: Yazen Ghannam
---
drivers/edac/mce_amd.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers
ivers/hwmon/k10temp.c | 2 ++
> > include/linux/pci_ids.h | 1 +
> > 5 files changed, 25 insertions(+)
> >
PCI IDs and EDAC look good to me.
Acked-by: Yazen Ghannam
Thanks,
Yazen
_mce.status & ~MCI_STATUS_UC);
> > + i_mce.status &= ~MCI_STATUS_UC;
>
> Boris: "git blame" says you wrote this code. Patch looks right (in
> that it makes the code do what the comment just above says it is trying
> to do):
>
> * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC
>
> But this is AMD specific, so I'll defer judgement
>
Acked-by: Yazen Ghannam
Thanks,
Yazen
On Fri, May 29, 2020 at 07:57:20AM -0400, Borislav Petkov wrote:
> On Fri, May 29, 2020 at 01:55:29PM +0300, Dmitry Antipov wrote:
> > Hello,
> >
> > I'm facing the following kernel messages running Debian 9 with
> > custom 5.6.12 kernel running on AMD EPYC 7502 - based hardware:
> >
> >
On Sun, May 10, 2020 at 04:48:42PM -0400, Alexander Monakov wrote:
> Add support for AMD Renoir (4000-series Ryzen CPUs).
>
> Signed-off-by: Alexander Monakov
> Cc: Thomas Gleixner
> Cc: Borislav Petkov
> Cc: x...@kernel.org
> Cc: Yazen Ghannam
> Cc: Brian Woods
>
islav Petkov
> Cc: x...@kernel.org
> Cc: Yazen Ghannam
> Cc: Brian Woods
> Cc: Clemens Ladisch
> Cc: Jean Delvare
> Cc: Guenter Roeck
> Cc: linux-hw...@vger.kernel.org
> Cc: linux-e...@vger.kernel.org
Acked-by: Yazen Ghannam
Thanks,
Yazen
Commit-ID: 068b053dca0e2ab40b3d953b102a178654eec282
Gitweb: https://git.kernel.org/tip/068b053dca0e2ab40b3d953b102a178654eec282
Author: Yazen Ghannam
AuthorDate: Fri, 7 Jun 2019 20:18:06 +
Committer: Borislav Petkov
CommitDate: Tue, 11 Jun 2019 15:23:34 +0200
x86/MCE: Determine
Commit-ID: c7d314f386e987be8b51eeb7dd947756ae23f6b6
Gitweb: https://git.kernel.org/tip/c7d314f386e987be8b51eeb7dd947756ae23f6b6
Author: Yazen Ghannam
AuthorDate: Fri, 7 Jun 2019 20:18:05 +
Committer: Borislav Petkov
CommitDate: Tue, 11 Jun 2019 15:23:09 +0200
x86/MCE: Make
Commit-ID: 95d057f54664f3c6e8f650faf5690b82b30a9e52
Gitweb: https://git.kernel.org/tip/95d057f54664f3c6e8f650faf5690b82b30a9e52
Author: Yazen Ghannam
AuthorDate: Fri, 7 Jun 2019 20:18:04 +
Committer: Borislav Petkov
CommitDate: Tue, 11 Jun 2019 15:22:41 +0200
x86/MCE/AMD: Don't
Commit-ID: b4914508f1fe0eca1cd011b6026ff762a1aa62d5
Gitweb: https://git.kernel.org/tip/b4914508f1fe0eca1cd011b6026ff762a1aa62d5
Author: Yazen Ghannam
AuthorDate: Fri, 7 Jun 2019 20:18:04 +
Committer: Borislav Petkov
CommitDate: Tue, 11 Jun 2019 15:22:13 +0200
x86/MCE: Make
Commit-ID: 95fdce6b24f3526c2bd1aad15978d238b79da6bd
Gitweb: https://git.kernel.org/tip/95fdce6b24f3526c2bd1aad15978d238b79da6bd
Author: Yazen Ghannam
AuthorDate: Fri, 7 Jun 2019 20:18:03 +
Committer: Borislav Petkov
CommitDate: Tue, 11 Jun 2019 15:13:51 +0200
x86/MCE: Make struct
Commit-ID: 45d4b7b9cb88526f6d5bd4c03efab88d75d10e4f
Gitweb: https://git.kernel.org/tip/45d4b7b9cb88526f6d5bd4c03efab88d75d10e4f
Author: Yazen Ghannam
AuthorDate: Mon, 25 Mar 2019 16:34:22 +
Committer: Borislav Petkov
CommitDate: Tue, 23 Apr 2019 18:04:47 +0200
x86/MCE: Add an MCE
Commit-ID: 71a84402b93e5fbd8f817f40059c137e10171788
Gitweb: https://git.kernel.org/tip/71a84402b93e5fbd8f817f40059c137e10171788
Author: Yazen Ghannam
AuthorDate: Mon, 25 Mar 2019 16:34:22 +
Committer: Borislav Petkov
CommitDate: Tue, 23 Apr 2019 18:16:07 +0200
x86/MCE/AMD: Don't
Commit-ID: 006c077041dc73b9490fffc4c6af5befe0687110
Gitweb: https://git.kernel.org/tip/006c077041dc73b9490fffc4c6af5befe0687110
Author: Yazen Ghannam
AuthorDate: Fri, 27 Jul 2018 16:40:09 -0500
Committer: Borislav Petkov
CommitDate: Wed, 27 Mar 2019 13:12:49 +0100
x86/mce: Handle
Commit-ID: 9308fd4074551f222f30322d1ee8c5aff18e9747
Gitweb: https://git.kernel.org/tip/9308fd4074551f222f30322d1ee8c5aff18e9747
Author: Yazen Ghannam
AuthorDate: Fri, 22 Mar 2019 20:29:00 +
Committer: Borislav Petkov
CommitDate: Sun, 24 Mar 2019 10:54:13 +0100
x86/MCE: Group AMD
Commit-ID: 3f4da372ec8e4ce58c17ac4f2e3c8891bbfea17e
Gitweb: https://git.kernel.org/tip/3f4da372ec8e4ce58c17ac4f2e3c8891bbfea17e
Author: Yazen Ghannam
AuthorDate: Tue, 12 Feb 2019 21:24:28 +
Committer: Borislav Petkov
CommitDate: Fri, 15 Feb 2019 14:25:58 +0100
EDAC/mce_amd: Decode
Commit-ID: a0bcd3c0b8a52ba0eb74371fa6be15ad0390ba67
Gitweb: https://git.kernel.org/tip/a0bcd3c0b8a52ba0eb74371fa6be15ad0390ba67
Author: Yazen Ghannam
AuthorDate: Tue, 12 Feb 2019 21:24:29 +
Committer: Borislav Petkov
CommitDate: Fri, 15 Feb 2019 14:36:31 +0100
EDAC/mce_amd: Decode
Commit-ID: 1c1522d32ac49065f88e5a8b3d6e3a5613b20118
Gitweb: https://git.kernel.org/tip/1c1522d32ac49065f88e5a8b3d6e3a5613b20118
Author: Yazen Ghannam
AuthorDate: Fri, 1 Feb 2019 22:55:54 +
Committer: Borislav Petkov
CommitDate: Mon, 4 Feb 2019 19:29:13 +0100
EDAC, mce_amd: Print
Commit-ID: e03447ee718b331be8f3abc388c7bf7d325dfab4
Gitweb: https://git.kernel.org/tip/e03447ee718b331be8f3abc388c7bf7d325dfab4
Author: Yazen Ghannam
AuthorDate: Fri, 1 Feb 2019 22:55:53 +
Committer: Borislav Petkov
CommitDate: Sun, 3 Feb 2019 13:16:50 +0100
EDAC, mce_amd: Match
Commit-ID: 3ad7e748c12cc771df6020a552def3e1727e8a17
Gitweb: https://git.kernel.org/tip/3ad7e748c12cc771df6020a552def3e1727e8a17
Author: Yazen Ghannam
AuthorDate: Fri, 1 Feb 2019 22:55:52 +
Committer: Borislav Petkov
CommitDate: Sun, 3 Feb 2019 13:01:57 +0100
x86/MCE/AMD, EDAC
Commit-ID: 8a5dd2cd2f2e94878cacc969655a69ca214795ab
Gitweb: https://git.kernel.org/tip/8a5dd2cd2f2e94878cacc969655a69ca214795ab
Author: Yazen Ghannam
AuthorDate: Fri, 1 Feb 2019 22:55:52 +
Committer: Borislav Petkov
CommitDate: Sun, 3 Feb 2019 13:05:16 +0100
x86/MCE/AMD, EDAC
Commit-ID: cbfa447edd6a3825fdb8a4ffae74ff7208f2d2c0
Gitweb: https://git.kernel.org/tip/cbfa447edd6a3825fdb8a4ffae74ff7208f2d2c0
Author: Yazen Ghannam
AuthorDate: Fri, 1 Feb 2019 22:55:51 +
Committer: Borislav Petkov
CommitDate: Sun, 3 Feb 2019 13:01:44 +0100
x86/MCE/AMD, EDAC
From: Yazen Ghannam
During mce_threshold_create_device() data structures are allocated for
each CPUs MCA banks and thresholding blocks. These data structures are
used to save information related to AMD's MCA Error Thresholding
feature. The structures are used in the thresholding interrupt
From: Yazen Ghannam
During mce_threshold_create_device() data structures are allocated for
each CPUs MCA banks and thresholding blocks. These data structures are
used to save information related to AMD's MCA Error Thresholding
feature. The structures are used in the thresholding interrupt
From: Yazen Ghannam
If threshold_init_device() fails then per_cpu(threshold_banks) will be
deallocated. The thresholding interrupt handler will still be active, so
it's possible to get a NULL pointer dereference if a THR interrupt
happens and any of the structures are NULL.
Exit the handler
From: Yazen Ghannam
If threshold_init_device() fails then per_cpu(threshold_banks) will be
deallocated. The thresholding interrupt handler will still be active, so
it's possible to get a NULL pointer dereference if a THR interrupt
happens and any of the structures are NULL.
Exit the handler
From: Yazen Ghannam
Linux reads MCG_CAP[Count] to find the number of MCA banks visible to a
CPU. Currently, this is assumed to be the same for all CPUs and a
warning is shown if there is a difference. The number of banks is
overwritten with the MCG_CAP[Count] value of each following CPU
From: Yazen Ghannam
Linux reads MCG_CAP[Count] to find the number of MCA banks visible to a
CPU. Currently, this is assumed to be the same for all CPUs and a
warning is shown if there is a difference. The number of banks is
overwritten with the MCG_CAP[Count] value of each following CPU
Commit-ID: 9c178663cbf2e754be322505078306b4a380a697
Gitweb: https://git.kernel.org/tip/9c178663cbf2e754be322505078306b4a380a697
Author: Yazen Ghannam <yazen.ghan...@amd.com>
AuthorDate: Fri, 4 May 2018 07:59:56 +0200
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Mon,
Commit-ID: 9c178663cbf2e754be322505078306b4a380a697
Gitweb: https://git.kernel.org/tip/9c178663cbf2e754be322505078306b4a380a697
Author: Yazen Ghannam
AuthorDate: Fri, 4 May 2018 07:59:56 +0200
Committer: Ingo Molnar
CommitDate: Mon, 14 May 2018 08:57:48 +0200
efi: Decode IA32/X64
Commit-ID: a32bc29ed19776ef6827d6336847de9a0b7a8dc5
Gitweb: https://git.kernel.org/tip/a32bc29ed19776ef6827d6336847de9a0b7a8dc5
Author: Yazen Ghannam <yazen.ghan...@amd.com>
AuthorDate: Fri, 4 May 2018 07:59:55 +0200
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Mon,
Commit-ID: a32bc29ed19776ef6827d6336847de9a0b7a8dc5
Gitweb: https://git.kernel.org/tip/a32bc29ed19776ef6827d6336847de9a0b7a8dc5
Author: Yazen Ghannam
AuthorDate: Fri, 4 May 2018 07:59:55 +0200
Committer: Ingo Molnar
CommitDate: Mon, 14 May 2018 08:57:48 +0200
efi: Decode IA32/X64 MS
Commit-ID: a9c1e3e791409e35207277b7873efc756b6fb625
Gitweb: https://git.kernel.org/tip/a9c1e3e791409e35207277b7873efc756b6fb625
Author: Yazen Ghannam <yazen.ghan...@amd.com>
AuthorDate: Fri, 4 May 2018 07:59:53 +0200
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Mon,
Commit-ID: c6bc4ac0aadede7a5c5260bcc315cd2b18c6b471
Gitweb: https://git.kernel.org/tip/c6bc4ac0aadede7a5c5260bcc315cd2b18c6b471
Author: Yazen Ghannam <yazen.ghan...@amd.com>
AuthorDate: Fri, 4 May 2018 07:59:54 +0200
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Mon,
Commit-ID: a9c1e3e791409e35207277b7873efc756b6fb625
Gitweb: https://git.kernel.org/tip/a9c1e3e791409e35207277b7873efc756b6fb625
Author: Yazen Ghannam
AuthorDate: Fri, 4 May 2018 07:59:53 +0200
Committer: Ingo Molnar
CommitDate: Mon, 14 May 2018 08:57:48 +0200
efi: Decode IA32/X64
Commit-ID: c6bc4ac0aadede7a5c5260bcc315cd2b18c6b471
Gitweb: https://git.kernel.org/tip/c6bc4ac0aadede7a5c5260bcc315cd2b18c6b471
Author: Yazen Ghannam
AuthorDate: Fri, 4 May 2018 07:59:54 +0200
Committer: Ingo Molnar
CommitDate: Mon, 14 May 2018 08:57:48 +0200
efi: Decode additional
Commit-ID: dc2d26e4b667c8005c58669e71de3efd17f4390f
Gitweb: https://git.kernel.org/tip/dc2d26e4b667c8005c58669e71de3efd17f4390f
Author: Yazen Ghannam <yazen.ghan...@amd.com>
AuthorDate: Fri, 4 May 2018 07:59:52 +0200
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Mon,
Commit-ID: dc2d26e4b667c8005c58669e71de3efd17f4390f
Gitweb: https://git.kernel.org/tip/dc2d26e4b667c8005c58669e71de3efd17f4390f
Author: Yazen Ghannam
AuthorDate: Fri, 4 May 2018 07:59:52 +0200
Committer: Ingo Molnar
CommitDate: Mon, 14 May 2018 08:57:47 +0200
efi: Decode UEFI-defined
Commit-ID: 7c9449b8c8a59511b7d749afb193c96353451c82
Gitweb: https://git.kernel.org/tip/7c9449b8c8a59511b7d749afb193c96353451c82
Author: Yazen Ghannam <yazen.ghan...@amd.com>
AuthorDate: Fri, 4 May 2018 07:59:51 +0200
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Mon,
Commit-ID: 7c9449b8c8a59511b7d749afb193c96353451c82
Gitweb: https://git.kernel.org/tip/7c9449b8c8a59511b7d749afb193c96353451c82
Author: Yazen Ghannam
AuthorDate: Fri, 4 May 2018 07:59:51 +0200
Committer: Ingo Molnar
CommitDate: Mon, 14 May 2018 08:57:47 +0200
efi: Decode IA32/X64
Commit-ID: f9e1bdb9f35f4f5cfa7c9025ac68c02909b6d3b1
Gitweb: https://git.kernel.org/tip/f9e1bdb9f35f4f5cfa7c9025ac68c02909b6d3b1
Author: Yazen Ghannam <yazen.ghan...@amd.com>
AuthorDate: Fri, 4 May 2018 07:59:50 +0200
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Mon,
Commit-ID: f9e1bdb9f35f4f5cfa7c9025ac68c02909b6d3b1
Gitweb: https://git.kernel.org/tip/f9e1bdb9f35f4f5cfa7c9025ac68c02909b6d3b1
Author: Yazen Ghannam
AuthorDate: Fri, 4 May 2018 07:59:50 +0200
Committer: Ingo Molnar
CommitDate: Mon, 14 May 2018 08:57:47 +0200
efi: Decode IA32/X64
Commit-ID: 742632d237ce180439ab4af31e9891df0df81233
Gitweb: https://git.kernel.org/tip/742632d237ce180439ab4af31e9891df0df81233
Author: Yazen Ghannam <yazen.ghan...@amd.com>
AuthorDate: Fri, 4 May 2018 07:59:49 +0200
Committer: Ingo Molnar <mi...@kernel.org>
CommitDate: Mon,
Commit-ID: 742632d237ce180439ab4af31e9891df0df81233
Gitweb: https://git.kernel.org/tip/742632d237ce180439ab4af31e9891df0df81233
Author: Yazen Ghannam
AuthorDate: Fri, 4 May 2018 07:59:49 +0200
Committer: Ingo Molnar
CommitDate: Mon, 14 May 2018 08:57:47 +0200
efi: Fix IA32/X64
Commit-ID: da6fa7ef67f07108a1b0cb9fd9e7fcaabd39c051
Gitweb: https://git.kernel.org/tip/da6fa7ef67f07108a1b0cb9fd9e7fcaabd39c051
Author: Yazen Ghannam <yazen.ghan...@amd.com>
AuthorDate: Tue, 3 Apr 2018 09:02:28 -0500
Committer: Thomas Gleixner <t...@linutronix.de>
CommitDate:
Commit-ID: da6fa7ef67f07108a1b0cb9fd9e7fcaabd39c051
Gitweb: https://git.kernel.org/tip/da6fa7ef67f07108a1b0cb9fd9e7fcaabd39c051
Author: Yazen Ghannam
AuthorDate: Tue, 3 Apr 2018 09:02:28 -0500
Committer: Thomas Gleixner
CommitDate: Thu, 26 Apr 2018 16:06:19 +0200
x86/smpboot: Don't
From: Yazen Ghannam <yazen.ghan...@amd.com>
Recent AMD systems support using MWAIT for C1 state. However, MWAIT will
not allow deeper cstates than C1 on current systems.
With play_dead() we expect the OS to use the deepest state available.
The deepest state available on AMD systems is r
From: Yazen Ghannam
Recent AMD systems support using MWAIT for C1 state. However, MWAIT will
not allow deeper cstates than C1 on current systems.
With play_dead() we expect the OS to use the deepest state available.
The deepest state available on AMD systems is reached through SystemIO
or HALT
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