Hi Nick
On 4/5/21 8:57 AM, Nick Kossifidis wrote:
> This patch series adds kexec/kdump and crash kernel
> support on RISC-V. For testing the patches a patched
> version of kexec-tools is needed (still a work in
> progress) which can be found at:
>
>
HI Andreas, Zong:
On Fri, Mar 19, 2021 at 4:51 PM Andreas Schwab wrote:
>
> On Mär 19 2021, Yixun Lan wrote:
>
> > what's the exact root cause? and any solution?
>
> Try reverting the five commits starting with
> 732374a0b440d9a79c8412f318a25cd37ba6f4e2.
>
I confirm r
; > That breaks ethernet on the fu540.
> > >
> >
> > I would check that, thanks for the report.
> >
>
> Hi Andreas,
>
> Could you please point me out how to test the ethernet from your side?
> I had tried to quick test by using iperf and wget, the ethernet seems
> to work fine to me.
>
I will give it a shot during this weekend, since I'm facing the same issue..
Yixun Lan
HI Andreas:
On Fri, Mar 19, 2021 at 8:28 AM Yixun Lan wrote:
>
> HI Andreas:
>
> On Wed, Mar 17, 2021 at 4:27 PM Andreas Schwab wrote:
> >
> > It turned out to be a broken clock driver.
> >
>
> what's the exact root cause? and any solution?
> seems I face
HI Andreas:
On Wed, Mar 17, 2021 at 4:27 PM Andreas Schwab wrote:
>
> It turned out to be a broken clock driver.
>
what's the exact root cause? and any solution?
seems I face the same issue, upgrade kernel to 5.11, then eth0 fail to bring up
Yixun Lan
Hi Jiuyang
On Tue, Mar 16, 2021 at 1:56 AM Jiuyang Liu wrote:
>
> Sorry for the noise, Andrew gave me feedbacks, and pointed two bugs in
> last patch.
> 1. asid should be thread safe, which is not the intent.
> 2. asid extracting logic was wrong.
>
> This patch fixes these bugs.
>
>
Hi Jerome, Jianxin:
see my comments
On 10:58 Wed 24 Oct , Jerome Brunet wrote:
> On Thu, 2018-10-18 at 13:07 +0800, Jianxin Pan wrote:
> > From: Yixun Lan
> >
> > Document the MMC sub clock controller driver, the potential consumer
> > of this driver is MMC o
Hi Jerome, Jianxin:
see my comments
On 10:58 Wed 24 Oct , Jerome Brunet wrote:
> On Thu, 2018-10-18 at 13:07 +0800, Jianxin Pan wrote:
> > From: Yixun Lan
> >
> > Document the MMC sub clock controller driver, the potential consumer
> > of this driver is MMC o
G platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Kconfig| 10 ++
drivers/clk/meson/Makefile | 1 +
drivers/clk
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
---
.../bindings/clock/amlogic,mmc-clkc.txt | 31
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/clk-phase-delay.c | 96 +
drivers/clk/meson/clkc.h| 13
3
G platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Kconfig| 10 ++
drivers/clk/meson/Makefile | 1 +
drivers/clk
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add four clock bindings IDs which
provided by this driver.
Reviewed-by: Rob Herring
Signed-off-by: Yixun Lan
---
.../bindings/clock/amlogic,mmc-clkc.txt | 31
Export the emmc sub clock phase delay ops which will be used
by the emmc sub clock driver itself.
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/clk-phase-delay.c | 96 +
drivers/clk/meson/clkc.h| 13
3
/20180710163658.6175-1-yixun@amlogic.com
[4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com
Yixun Lan (3):
clk: meson: add emmc sub clock phase delay driver
clk: meson: add DT documentation for emmc clock controller
clk: meson: add sub MMC clock controller driver
.../bindings/clock
/20180710163658.6175-1-yixun@amlogic.com
[4] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com
Yixun Lan (3):
clk: meson: add emmc sub clock phase delay driver
clk: meson: add DT documentation for emmc clock controller
clk: meson: add sub MMC clock controller driver
.../bindings/clock
Hi Jerome
On 07/30/18 16:57, Jerome Brunet wrote:
> On Fri, 2018-07-27 at 09:45 -0700, Stephen Boyd wrote:
>> Quoting Stephen Boyd (2018-07-27 09:41:40)
>>> Quoting Yixun Lan (2018-07-27 07:52:23)
>>>> HI Stephen:
>>>>
>>>> On 07/26/2018 11:20
Hi Jerome
On 07/30/18 16:57, Jerome Brunet wrote:
> On Fri, 2018-07-27 at 09:45 -0700, Stephen Boyd wrote:
>> Quoting Stephen Boyd (2018-07-27 09:41:40)
>>> Quoting Yixun Lan (2018-07-27 07:52:23)
>>>> HI Stephen:
>>>>
>>>> On 07/26/2018 11:20
patch 1,2 (documentation & header file)
- explain pinctrl IP
- notice GPIOE located in AO bank
[1] https://lkml.kernel.org/r/20180704224511.29350-1-yixun@amlogic.com
[2] https://lkml.kernel.org/r/20180714232754.5402-1-yixun@amlogic.com
Yixun Lan (2):
documentation: pinctrl: Add compati
from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.
Please note, the GPIOE is actually located at AO (always on) bank.
Acked-by: Martin Blumenstingl
Signed-off-by: Xingyu Chen
Signed-off-by: Yixun Lan
---
drivers
patch 1,2 (documentation & header file)
- explain pinctrl IP
- notice GPIOE located in AO bank
[1] https://lkml.kernel.org/r/20180704224511.29350-1-yixun@amlogic.com
[2] https://lkml.kernel.org/r/20180714232754.5402-1-yixun@amlogic.com
Yixun Lan (2):
documentation: pinctrl: Add compati
from 0 - 7, each can describe one pin,
the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
the mux pin function.
Please note, the GPIOE is actually located at AO (always on) bank.
Acked-by: Martin Blumenstingl
Signed-off-by: Xingyu Chen
Signed-off-by: Yixun Lan
---
drivers
Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.
Acked-by: Martin Blumenstingl
Reviewed-by: Rob Herring
Signed-off-by: Xingyu Chen
Signed-off-by: Yixun Lan
---
.../bindings/pinctrl/meson,pinctrl.txt
Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.
Acked-by: Martin Blumenstingl
Reviewed-by: Rob Herring
Signed-off-by: Xingyu Chen
Signed-off-by: Yixun Lan
---
.../bindings/pinctrl/meson,pinctrl.txt
hi Maxime:
On Sun, Aug 5, 2018 at 4:02 AM, Maxime Jourdan wrote:
>>> + sysctrl_DMC: system-controller@0 {
>>> + compatible =
>>> "amlogic,meson-gx-dmc-sysctrl", "syscon", "simple-mfd";
>>
>> we'd like to drop 'meson-' prefix, so better using
hi Maxime:
On Sun, Aug 5, 2018 at 4:02 AM, Maxime Jourdan wrote:
>>> + sysctrl_DMC: system-controller@0 {
>>> + compatible =
>>> "amlogic,meson-gx-dmc-sysctrl", "syscon", "simple-mfd";
>>
>> we'd like to drop 'meson-' prefix, so better using
HI Maxime
thanks for contributing the patches ;-)
On Thu, Aug 2, 2018 at 2:51 AM, Maxime Jourdan wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those
HI Maxime
thanks for contributing the patches ;-)
On Thu, Aug 2, 2018 at 2:51 AM, Maxime Jourdan wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those
Hi Maxime
great job! thanks for contributing the patches..
On Thu, Aug 2, 2018 at 2:51 AM, Maxime Jourdan wrote:
> Wrap the canvas node in a syscon node.
>
> Signed-off-by: Maxime Jourdan
> ---
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 17 +
> 1 file changed, 17
Hi Maxime
great job! thanks for contributing the patches..
On Thu, Aug 2, 2018 at 2:51 AM, Maxime Jourdan wrote:
> Wrap the canvas node in a syscon node.
>
> Signed-off-by: Maxime Jourdan
> ---
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 17 +
> 1 file changed, 17
Hi Boris
On 08/02/2018 05:50 AM, Boris Brezillon wrote:
> Hi Yixun,
>
> On Thu, 19 Jul 2018 17:46:12 +0800
> Yixun Lan wrote:
>
> I haven't finished reviewing the driver yet (I'll try to do that later
> this week), but I already pointed a few things to fix/improve.
>
Hi Boris
On 08/02/2018 05:50 AM, Boris Brezillon wrote:
> Hi Yixun,
>
> On Thu, 19 Jul 2018 17:46:12 +0800
> Yixun Lan wrote:
>
> I haven't finished reviewing the driver yet (I'll try to do that later
> this week), but I already pointed a few things to fix/improve.
>
We found the PCIe driver doesn't really work with
the mpll3 clock which is actually reserved for debug,
So drop it from the mux list.
Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver")
Tested-by: Jianxin Qin
Signed-off-by: Yixun Lan
---
hi Jerome:
I'm sorr
We found the PCIe driver doesn't really work with
the mpll3 clock which is actually reserved for debug,
So drop it from the mux list.
Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver")
Tested-by: Jianxin Qin
Signed-off-by: Yixun Lan
---
hi Jerome:
I'm sorr
HI Stephen:
On 07/26/2018 11:20 PM, Stephen Boyd wrote:
> Quoting Yixun Lan (2018-07-12 14:12:44)
>> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
>> new file mode 100644
>> index ..36c4c7cd69a6
>> --- /dev/null
>> +
HI Stephen:
On 07/26/2018 11:20 PM, Stephen Boyd wrote:
> Quoting Yixun Lan (2018-07-12 14:12:44)
>> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
>> new file mode 100644
>> index ..36c4c7cd69a6
>> --- /dev/null
>> +
HI Rob
On 07/25/2018 07:29 AM, Rob Herring wrote:
> On Thu, Jul 12, 2018 at 09:12:43PM +0000, Yixun Lan wrote:
>> Document the MMC sub clock controller driver, the potential consumer
>> of this driver is MMC or NAND. Also add three clock bindings IDs which
>> pr
HI Rob
On 07/25/2018 07:29 AM, Rob Herring wrote:
> On Thu, Jul 12, 2018 at 09:12:43PM +0000, Yixun Lan wrote:
>> Document the MMC sub clock controller driver, the potential consumer
>> of this driver is MMC or NAND. Also add three clock bindings IDs which
>> pr
HI Neil
On 07/26/2018 10:13 PM, Neil Armstrong wrote:
> The order between "syscon" and "simple-mfd" is important because in these
> particular cases, the node needs to be first a "simple-mfd" to expose
> it's sub-nodes, and later on a "syscon" to permit other nodes to access
> this register space
HI Neil
On 07/26/2018 10:13 PM, Neil Armstrong wrote:
> The order between "syscon" and "simple-mfd" is important because in these
> particular cases, the node needs to be first a "simple-mfd" to expose
> it's sub-nodes, and later on a "syscon" to permit other nodes to access
> this register space
HI Kevin
On 07/23/2018 10:12 PM, Kevin Hilman wrote:
> Yixun Lan writes:
>
> [...]
>
>>>
>>>> Second, we might like to convert eMMC driver to also use mmc-clkc model.
>>>
>>> IMO, this should be done as part of merging this series. Otherw
HI Kevin
On 07/23/2018 10:12 PM, Kevin Hilman wrote:
> Yixun Lan writes:
>
> [...]
>
>>>
>>>> Second, we might like to convert eMMC driver to also use mmc-clkc model.
>>>
>>> IMO, this should be done as part of merging this series. Otherw
On 07/19/2018 10:06 PM, Kevin Hilman wrote:
> Yixun Lan writes:
>
> [...]
>
>>>
>>> As Jerome said, I think consistency is an important goal, so leaving off
>>> the "meson-" for drivers/clk is fine with me.
>>>
>> ok
>>
On 07/19/2018 10:06 PM, Kevin Hilman wrote:
> Yixun Lan writes:
>
> [...]
>
>>>
>>> As Jerome said, I think consistency is an important goal, so leaving off
>>> the "meson-" for drivers/clk is fine with me.
>>>
>> ok
>>
Hi Boris:
see my comments, thanks for the quick response
On 07/19/18 17:57, Boris Brezillon wrote:
> On Thu, 19 Jul 2018 17:46:11 +0800
> Yixun Lan wrote:
>
>> From: Liang Yang
>>
>> Add Amlogic NAND controller dt-bindings for Meson SoC,
>> Current this dri
Hi Boris:
see my comments, thanks for the quick response
On 07/19/18 17:57, Boris Brezillon wrote:
> On Thu, 19 Jul 2018 17:46:11 +0800
> Yixun Lan wrote:
>
>> From: Liang Yang
>>
>> Add Amlogic NAND controller dt-bindings for Meson SoC,
>> Current this dri
HI Boris
On 07/19/18 16:39, Boris Brezillon wrote:
> Hi Yixun,
>
> On Thu, 19 Jul 2018 16:13:47 +0800
> Yixun Lan wrote:
>
>>>>> You're doing DMA on those buffers, and devm_kzalloc() is not
>>>>> DMA-friendly (returned buffers are not aligned
HI Boris
On 07/19/18 16:39, Boris Brezillon wrote:
> Hi Yixun,
>
> On Thu, 19 Jul 2018 16:13:47 +0800
> Yixun Lan wrote:
>
>>>>> You're doing DMA on those buffers, and devm_kzalloc() is not
>>>>> DMA-friendly (returned buffers are not aligned
- how to construct mtd->name
[1] https://lkml.kernel.org/r/20180613161314.14894-1-yixun@amlogic.com
[2] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com
Liang Yang (1):
dt-bindings: nand: meson: add Amlogic NAND controller driver
Yixun Lan (1):
mtd: rawnand: meson
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
---
.../bindings/mtd/amlogic,meson-nand.txt | 95 +++
1 file changed, 95 insertions(+)
create
- how to construct mtd->name
[1] https://lkml.kernel.org/r/20180613161314.14894-1-yixun@amlogic.com
[2] https://lkml.kernel.org/r/20180712211244.11428-1-yixun@amlogic.com
Liang Yang (1):
dt-bindings: nand: meson: add Amlogic NAND controller driver
Yixun Lan (1):
mtd: rawnand: meson
From: Liang Yang
Add Amlogic NAND controller dt-bindings for Meson SoC,
Current this driver support GXBB/GXL/AXG platform.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
---
.../bindings/mtd/amlogic,meson-nand.txt | 95 +++
1 file changed, 95 insertions(+)
create
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
---
drivers/mtd/nand/raw/Kconfig | 10 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/meson_nand.c | 1333
Add initial support for the Amlogic NAND flash controller which found
in the Meson-GXBB/GXL/AXG SoCs.
Signed-off-by: Liang Yang
Signed-off-by: Yixun Lan
---
drivers/mtd/nand/raw/Kconfig | 10 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/meson_nand.c | 1333
HI Boris:
thanks for the quick response.
On 07/19/18 03:08, Boris Brezillon wrote:
> Hi Yixun,
>
> On Wed, 18 Jul 2018 17:38:56 +0800
> Yixun Lan wrote:
>
>>>> +
>>>> +#define NFC_REG_CMD 0x00
>>>> +#define NFC_RE
HI Boris:
thanks for the quick response.
On 07/19/18 03:08, Boris Brezillon wrote:
> Hi Yixun,
>
> On Wed, 18 Jul 2018 17:38:56 +0800
> Yixun Lan wrote:
>
>>>> +
>>>> +#define NFC_REG_CMD 0x00
>>>> +#define NFC_RE
Hi Roris
thanks for all your suggestions!
It actually takes us some time to digest all your comments ;-)
and get back to you on these questions.
On 06/25/18 03:38, Boris Brezillon wrote:
>
>
> Hi Yixun,
>
> On Wed, 13 Jun 2018 16:13:14 +0000
> Yixun Lan wrote:
>
Hi Roris
thanks for all your suggestions!
It actually takes us some time to digest all your comments ;-)
and get back to you on these questions.
On 06/25/18 03:38, Boris Brezillon wrote:
>
>
> Hi Yixun,
>
> On Wed, 13 Jun 2018 16:13:14 +0000
> Yixun Lan wrote:
>
HI Martin
On 07/14/18 23:30, Martin Blumenstingl wrote:
> Hi Yixun,
>
> On Wed, Jul 4, 2018 at 4:50 PM Yixun Lan wrote:
>>
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
> my understanding is that:
HI Martin
On 07/14/18 23:30, Martin Blumenstingl wrote:
> Hi Yixun,
>
> On Wed, Jul 4, 2018 at 4:50 PM Yixun Lan wrote:
>>
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
> my understanding is that:
HI Jerome
On 07/16/18 17:54, Jerome Brunet wrote:
>
+/* uart_ao_a_ee */
+static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
+static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
>>>
>>> Same comment as Martin about naming consistency ... drop c2
HI Jerome
On 07/16/18 17:54, Jerome Brunet wrote:
>
+/* uart_ao_a_ee */
+static const unsigned int uart_ao_rx_a_c2_pins[]= { GPIOC_2 };
+static const unsigned int uart_ao_tx_a_c3_pins[]= { GPIOC_3 };
>>>
>>> Same comment as Martin about naming consistency ... drop c2
HI Kevin
just want to clarify..
On 07/16/18 21:38, Kevin Hilman wrote:
> Jerome Brunet writes:
>
>> On Tue, 2018-07-10 at 09:21 +0800, Yixun Lan wrote:
>>>
>>> On 07/10/18 05:53, Martin Blumenstingl wrote:
>>>> On Mon, Jul 9, 2018 at 1:14 PM Jian Hu
HI Kevin
just want to clarify..
On 07/16/18 21:38, Kevin Hilman wrote:
> Jerome Brunet writes:
>
>> On Tue, 2018-07-10 at 09:21 +0800, Yixun Lan wrote:
>>>
>>> On 07/10/18 05:53, Martin Blumenstingl wrote:
>>>> On Mon, Jul 9, 2018 at 1:14 PM Jian Hu
Hi Jerome
thanks for the review, see my comments below
On 07/16/18 00:16, Jerome Brunet wrote:
> On Sat, 2018-07-14 at 23:27 +0000, Yixun Lan wrote:
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
>>
>>
Hi Jerome
thanks for the review, see my comments below
On 07/16/18 00:16, Jerome Brunet wrote:
> On Sat, 2018-07-14 at 23:27 +0000, Yixun Lan wrote:
>> Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
>> the previous Meson-AXG SoC.
>>
>>
to
the mux pin function.
Please note, the GPIOE is actually located at AO (always on) bank.
Acked-by: Martin Blumenstingl
Signed-off-by: Xingyu Chen
Signed-off-by: Yixun Lan
---
drivers/pinctrl/meson/Kconfig |6 +
drivers/pinctrl/meson/Makefile |1 +
drivers
to
the mux pin function.
Please note, the GPIOE is actually located at AO (always on) bank.
Acked-by: Martin Blumenstingl
Signed-off-by: Xingyu Chen
Signed-off-by: Yixun Lan
---
drivers/pinctrl/meson/Kconfig |6 +
drivers/pinctrl/meson/Makefile |1 +
drivers
rg/r/20180704224511.29350-1-yixun@amlogic.com
Yixun Lan (2):
documentation: pinctrl: Add compatibles for Amlogic Meson G12A pin
controllers
pinctrl: meson-g12a: add pinctrl driver support
.../bindings/pinctrl/meson,pinctrl.txt|2 +
drivers/pinctrl/meson/Kconfig |6 +
dri
Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.
Acked-by: Martin Blumenstingl
Signed-off-by: Xingyu Chen
Signed-off-by: Yixun Lan
---
.../bindings/pinctrl/meson,pinctrl.txt| 2 +
include/dt-bindings
rg/r/20180704224511.29350-1-yixun@amlogic.com
Yixun Lan (2):
documentation: pinctrl: Add compatibles for Amlogic Meson G12A pin
controllers
pinctrl: meson-g12a: add pinctrl driver support
.../bindings/pinctrl/meson,pinctrl.txt|2 +
drivers/pinctrl/meson/Kconfig |6 +
dri
Add new compatible name for Amlogic's Meson-G12A pin controllers,
add a dt-binding header file which document the detail pin names.
Acked-by: Martin Blumenstingl
Signed-off-by: Xingyu Chen
Signed-off-by: Yixun Lan
---
.../bindings/pinctrl/meson,pinctrl.txt| 2 +
include/dt-bindings
HI Martin
thanks for the comments
On 07/14/2018 10:47 PM, Martin Blumenstingl wrote:
> Hi Yixun,
>
> On Wed, Jul 4, 2018 at 4:49 PM Yixun Lan wrote:
>>
>> Document the pins for Amlogic's Meson-G12A SoC.
> I suggest to combine patch 1 (adding the compatible
HI Martin
thanks for the comments
On 07/14/2018 10:47 PM, Martin Blumenstingl wrote:
> Hi Yixun,
>
> On Wed, Jul 4, 2018 at 4:49 PM Yixun Lan wrote:
>>
>> Document the pins for Amlogic's Meson-G12A SoC.
> I suggest to combine patch 1 (adding the compatible
Hi Martin
see my comments
On 07/14/2018 10:36 PM, Martin Blumenstingl wrote:
> On Tue, Jul 10, 2018 at 12:07 AM Martin Blumenstingl
> wrote:
>>
>> Hi Linus,
>>
>> On Mon, Jul 9, 2018 at 3:35 PM Linus Walleij
>> wrote:
>>>
>&g
Hi Martin
see my comments
On 07/14/2018 10:36 PM, Martin Blumenstingl wrote:
> On Tue, Jul 10, 2018 at 12:07 AM Martin Blumenstingl
> wrote:
>>
>> Hi Linus,
>>
>> On Mon, Jul 9, 2018 at 3:35 PM Linus Walleij
>> wrote:
>>>
>&g
Hi Rob, Jerome, Kevin
see my comments
On 07/13/18 08:15, Rob Herring wrote:
> On Thu, Jul 12, 2018 at 5:29 PM Yixun Lan wrote:
>>
>> HI Rob
>>
>> see my comments
>>
>> On 07/12/2018 10:17 PM, Rob Herring wrote:
>>> On Wed, Jul 11, 2018 at 8:47 PM
Hi Rob, Jerome, Kevin
see my comments
On 07/13/18 08:15, Rob Herring wrote:
> On Thu, Jul 12, 2018 at 5:29 PM Yixun Lan wrote:
>>
>> HI Rob
>>
>> see my comments
>>
>> On 07/12/2018 10:17 PM, Rob Herring wrote:
>>> On Wed, Jul 11, 2018 at 8:47 PM
HI Rob
see my comments
On 07/12/2018 10:17 PM, Rob Herring wrote:
> On Wed, Jul 11, 2018 at 8:47 PM Yixun Lan wrote:
>>
>> Hi Rob
>>
>> see my comments
>>
>> On 07/12/18 03:43, Rob Herring wrote:
>>> On Tue, Jul 10, 2018 at 04:36:56PM +,
HI Rob
see my comments
On 07/12/2018 10:17 PM, Rob Herring wrote:
> On Wed, Jul 11, 2018 at 8:47 PM Yixun Lan wrote:
>>
>> Hi Rob
>>
>> see my comments
>>
>> On 07/12/18 03:43, Rob Herring wrote:
>>> On Tue, Jul 10, 2018 at 04:36:56PM +,
G platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Kconfig| 9 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/
G platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Kconfig| 9 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add three clock bindings IDs which
provided by this driver.
Signed-off-by: Yixun Lan
---
.../bindings/clock/amlogic,mmc-clkc.txt | 31 +++
.../clock/amlogic,meson-mmc
Document the MMC sub clock controller driver, the potential consumer
of this driver is MMC or NAND. Also add three clock bindings IDs which
provided by this driver.
Signed-off-by: Yixun Lan
---
.../bindings/clock/amlogic,mmc-clkc.txt | 31 +++
.../clock/amlogic,meson-mmc
[2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com
[3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com
Yixun Lan (2):
clk: meson: add DT documentation for emmc clock controller
clk: meson: add sub MMC clock controller driver
.../bindings/clock
[2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com
[3] https://lkml.kernel.org/r/20180710163658.6175-1-yixun@amlogic.com
Yixun Lan (2):
clk: meson: add DT documentation for emmc clock controller
clk: meson: add sub MMC clock controller driver
.../bindings/clock
Hi Jerome
thanks for the review
On 07/12/18 17:09, Jerome Brunet wrote:
> On Tue, 2018-07-10 at 16:36 +0000, Yixun Lan wrote:
>> The patch will add a MMC clock controller driver which used by MMC or NAND,
>> It provide a mux and divider clock, and three phase clocks - core, tx
Hi Jerome
thanks for the review
On 07/12/18 17:09, Jerome Brunet wrote:
> On Tue, 2018-07-10 at 16:36 +0000, Yixun Lan wrote:
>> The patch will add a MMC clock controller driver which used by MMC or NAND,
>> It provide a mux and divider clock, and three phase clocks - core, tx
Hi Rob
On 07/12/18 03:45, Rob Herring wrote:
> On Tue, Jul 10, 2018 at 04:36:57PM +0000, Yixun Lan wrote:
>> Add two clock bindings IDs which provided by the MMC clock controller,
>> These two clocks will be used by MMC or NAND driver.
>
> I count 3 ids.
I will update this
Hi Rob
On 07/12/18 03:45, Rob Herring wrote:
> On Tue, Jul 10, 2018 at 04:36:57PM +0000, Yixun Lan wrote:
>> Add two clock bindings IDs which provided by the MMC clock controller,
>> These two clocks will be used by MMC or NAND driver.
>
> I count 3 ids.
I will update this
Hi Rob
see my comments
On 07/12/18 03:43, Rob Herring wrote:
> On Tue, Jul 10, 2018 at 04:36:56PM +0000, Yixun Lan wrote:
>> Document the MMC sub clock controller driver, the potential consumer
>> of this driver is MMC or NAND.
>
> So you all have decided to properly m
Hi Rob
see my comments
On 07/12/18 03:43, Rob Herring wrote:
> On Tue, Jul 10, 2018 at 04:36:56PM +0000, Yixun Lan wrote:
>> Document the MMC sub clock controller driver, the potential consumer
>> of this driver is MMC or NAND.
>
> So you all have decided to properly m
Hi Jerome:
just one comment
On 07/10/2018 05:54 PM, Jerome Brunet wrote:
> On Tue, 2018-07-10 at 09:21 +0800, Yixun Lan wrote:
>> HI Martin
>>
>>
>> On 07/10/18 05:53, Martin Blumenstingl wrote:
>>> On Mon, Jul 9, 2018 at 1:14 PM Jian Hu wrote:
>>&g
Hi Jerome:
just one comment
On 07/10/2018 05:54 PM, Jerome Brunet wrote:
> On Tue, 2018-07-10 at 09:21 +0800, Yixun Lan wrote:
>> HI Martin
>>
>>
>> On 07/10/18 05:53, Martin Blumenstingl wrote:
>>> On Mon, Jul 9, 2018 at 1:14 PM Jian Hu wrote:
>>&g
HI Martin
On 07/10/18 06:07, Martin Blumenstingl wrote:
> Hi Linus,
>
> On Mon, Jul 9, 2018 at 3:35 PM Linus Walleij wrote:
>>
>> On Wed, Jul 4, 2018 at 4:48 PM Yixun Lan wrote:
>>>
>>> This patch series try to add pinctrl driver support for
>>&
HI Martin
On 07/10/18 06:07, Martin Blumenstingl wrote:
> Hi Linus,
>
> On Mon, Jul 9, 2018 at 3:35 PM Linus Walleij wrote:
>>
>> On Wed, Jul 4, 2018 at 4:48 PM Yixun Lan wrote:
>>>
>>> This patch series try to add pinctrl driver support for
>>&
G platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Kconfig| 9 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/
- update compatible name
- adjust file name
- divider probe() into small functions, and re-use them
[1] https://lkml.kernel.org/r/20180628090034.0637a062@xps13
[2] https://lkml.kernel.org/r/20180703145716.31860-1-yixun@amlogic.com
Yixun Lan (3):
clk: meson: add DT documentation for emmc
Add two clock bindings IDs which provided by the MMC clock controller,
These two clocks will be used by MMC or NAND driver.
Signed-off-by: Yixun Lan
---
.../dt-bindings/clock/amlogic,meson-mmc-clkc.h | 16
1 file changed, 16 insertions(+)
create mode 100644 include/dt
G platform.
To specify which clock the MMC or NAND driver may consume,
the preprocessor macros in the dt-bindings/clock/emmc-clkc.h header
can be used in the device tree sources.
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Kconfig| 9 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/
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