Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.
CC: <devicet...@vger.kernel.org>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
include/dt-bindings/clock/axg-aoclkc.h | 26 ++
include/dt-bindings/reset/axg-a
Add dt-bindings headers for the Meson-AXG's AO clock and
reset controller.
CC:
Signed-off-by: Yixun Lan
---
include/dt-bindings/clock/axg-aoclkc.h | 26 ++
include/dt-bindings/reset/axg-aoclkc.h | 20
2 files changed, 46 insertions(+)
create mode
This patch try to add AO clock and Reset driver in Amlogic's
Meson-AXG SoC.
Please note this patchset actually depend on the clock regmap
conversion series [1].
[1] clk: meson: use regmap in clock controllers
https://lkml.kernel.org/r/20180131180945.18025-1-jbru...@baylibre.com
Yixun Lan
This patch try to add AO clock and Reset driver in Amlogic's
Meson-AXG SoC.
Please note this patchset actually depend on the clock regmap
conversion series [1].
[1] clk: meson: use regmap in clock controllers
https://lkml.kernel.org/r/20180131180945.18025-1-jbru...@baylibre.com
Yixun Lan
Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.
Signed-off-by: Qiufang Dai <qiufang@amlogic.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
drivers/clk/meson/Makefile| 2 +-
drivers/clk/meson/axg-a
Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson-AXG SoC.
Signed-off-by: Qiufang Dai
Signed-off-by: Yixun Lan
---
drivers/clk/meson/Makefile| 2 +-
drivers/clk/meson/axg-aoclk.c | 236 ++
drivers/clk/meson/axg
HI Jerome:
On 02/01/18 02:09, Jerome Brunet wrote:
> Meson clock controllers needs to move the classical iomem registers to
> regmap. This is triggered because the HHI controllers found on the GXBB
> and GXL host more than just clocks. To properly handle this, we would
> like to migrate HHI to
HI Jerome:
On 02/01/18 02:09, Jerome Brunet wrote:
> Meson clock controllers needs to move the classical iomem registers to
> regmap. This is triggered because the HHI controllers found on the GXBB
> and GXL host more than just clocks. To properly handle this, we would
> like to migrate HHI to
On 01/31/18 08:22, Kevin Hilman wrote:
> On Tue, Jan 30, 2018 at 4:04 PM, Kevin Hilman <khil...@baylibre.com> wrote:
>> Yixun Lan <yixun@amlogic.com> writes:
>>
>>> HI Kevin
>>> These are the UART DT updates for the Meson-AXG platform.
>
On 01/31/18 08:22, Kevin Hilman wrote:
> On Tue, Jan 30, 2018 at 4:04 PM, Kevin Hilman wrote:
>> Yixun Lan writes:
>>
>>> HI Kevin
>>> These are the UART DT updates for the Meson-AXG platform.
>>>
>>> The patch 1 is a general fix.
>
-by: Wolfram Sang <w...@the-dreams.de>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
drivers/i2c/busses/i2c-meson.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
index 37c4aa76f37a..90f5d0407d73 100644
-
-by: Wolfram Sang
Signed-off-by: Yixun Lan
---
drivers/i2c/busses/i2c-meson.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
index 37c4aa76f37a..90f5d0407d73 100644
--- a/drivers/i2c/busses/i2c-meson.c
+++ b/drivers/i2c
Hi Wolfram：
On 01/24/18 14:28, Wolfram Sang wrote:
> On Mon, Nov 20, 2017 at 10:54:12PM +0800, Yixun Lan wrote:
>> From: Jian Hu <jian...@amlogic.com>
>>
>> This patch try to add support for I2C controller in Meson-AXG SoC,
>> Due to the IP changes between I2C
Hi Wolfram：
On 01/24/18 14:28, Wolfram Sang wrote:
> On Mon, Nov 20, 2017 at 10:54:12PM +0800, Yixun Lan wrote:
>> From: Jian Hu
>>
>> This patch try to add support for I2C controller in Meson-AXG SoC,
>> Due to the IP changes between I2C controller, we need to int
According to datasheet, the od shift of sys_pll is 16,
fix the typo which introduced at previous commit.
Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
drivers/clk/meson/axg.c | 2 +-
1 file changed, 1 insertion
According to datasheet, the od shift of sys_pll is 16,
fix the typo which introduced at previous commit.
Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan
---
drivers/clk/meson/axg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 01/19/18 02:45, Jerome Brunet wrote:
> The pll driver perform the rate calculation in Mhz, which adds an
> unnecessary rounding down to the Mhz of the rate. Use 64bits long
> integer to perform this calculation safely on meson8b and perform the
> calculation in Hz instead
>
> Fixes:
On 01/19/18 02:45, Jerome Brunet wrote:
> The pll driver perform the rate calculation in Mhz, which adds an
> unnecessary rounding down to the Mhz of the rate. Use 64bits long
> integer to perform this calculation safely on meson8b and perform the
> calculation in Hz instead
>
> Fixes:
Simply adjust the pin group to _x _y _z style, as to
keep the consistency in DT with previous naming scheme.
Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG
SoC")
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
Hi Linus,
Please also
Simply adjust the pin group to _x _y _z style, as to
keep the consistency in DT with previous naming scheme.
Fixes: 83c566806a68 ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG
SoC")
Signed-off-by: Yixun Lan
---
Hi Linus,
Please also consider merging this patch into
On 01/17/2018 08:14 AM, Kevin Hilman wrote:
> Yixun Lan <yixun@amlogic.com> writes:
>
>> Hi Jerome:
>>
>> On 01/10/2018 03:28 PM, Jerome Brunet wrote:
>>> On Wed, 2018-01-10 at 10:12 +0800, Yixun Lan wrote:
>>>>
>>>> On 01/08/1
On 01/17/2018 08:14 AM, Kevin Hilman wrote:
> Yixun Lan writes:
>
>> Hi Jerome:
>>
>> On 01/10/2018 03:28 PM, Jerome Brunet wrote:
>>> On Wed, 2018-01-10 at 10:12 +0800, Yixun Lan wrote:
>>>>
>>>> On 01/08/18 16:52, Jerome Brunet wrote:
Hi Jerome：
On 01/11/18 16:37, Jerome Brunet wrote:
> On Thu, 2018-01-11 at 11:04 +0800, Yixun Lan wrote:
>> Comparing to RGMII interface, the RMII interface require few pins.
>> So it's worth describing them here.
>>
>> Signed-off-by: Yixun Lan <yixun@amlogic.c
Hi Jerome：
On 01/11/18 16:37, Jerome Brunet wrote:
> On Thu, 2018-01-11 at 11:04 +0800, Yixun Lan wrote:
>> Comparing to RGMII interface, the RMII interface require few pins.
>> So it's worth describing them here.
>>
>> Signed-off-by: Yixun Lan
>
> The o
Comparing to RGMII interface, the RMII interface require few pins.
So it's worth describing them here.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch
Comparing to RGMII interface, the RMII interface require few pins.
So it's worth describing them here.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson
The address space range is actually 0x18, fixed here.
Reviewed-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 10 +-
2 file
The UART_A is connected to a BT module on the S400 board.
Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot
The address space range is actually 0x18, fixed here.
Reviewed-by: Jerome Brunet
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 10 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch
The UART_A is connected to a BT module on the S400 board.
Acked-by: Jerome Brunet
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic
ogic.com
[1]
http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com
Yixun Lan (5):
ARM64: dts: meson: uart: fix address space range
ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
ARM64: dts: meson-axg: uart: Add the pinctrl info description
ARM64: dt
result in not requesting the 'pclk' clock, thus break the driver in the
end.
Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff
Describe the pinctrl info for the UART controller which is found
in the Meson-AXG SoCs.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/a
ogic.com
[1]
http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com
Yixun Lan (5):
ARM64: dts: meson: uart: fix address space range
ARM64: dts: meson-axg: uart: drop legacy compatible name from EE UART
ARM64: dts: meson-axg: uart: Add the pinctrl info description
ARM64: dt
result in not requesting the 'pclk' clock, thus break the driver in the
end.
Acked-by: Jerome Brunet
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch
Describe the pinctrl info for the UART controller which is found
in the Meson-AXG SoCs.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch
Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we may need to rely on bootloader for the initialization.
Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |
Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we may need to rely on bootloader for the initialization.
Acked-by: Jerome Brunet
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch
Hi Jerome:
On 01/10/2018 03:28 PM, Jerome Brunet wrote:
> On Wed, 2018-01-10 at 10:12 +0800, Yixun Lan wrote:
>>
>> On 01/08/18 16:52, Jerome Brunet wrote:
>>> On Mon, 2018-01-08 at 15:33 +0800, Yixun Lan wrote:
>>>> These two patches are general improvement fo
Hi Jerome:
On 01/10/2018 03:28 PM, Jerome Brunet wrote:
> On Wed, 2018-01-10 at 10:12 +0800, Yixun Lan wrote:
>>
>> On 01/08/18 16:52, Jerome Brunet wrote:
>>> On Mon, 2018-01-08 at 15:33 +0800, Yixun Lan wrote:
>>>> These two patches are general improvement fo
On 01/08/18 16:52, Jerome Brunet wrote:
> On Mon, 2018-01-08 at 15:33 +0800, Yixun Lan wrote:
>> These two patches are general improvement for meson pinctrl driver.
>> It make the two pinctrl trees (ee/ao) to share one uniform 'function' name
>> for
>> one hardwar
On 01/08/18 16:52, Jerome Brunet wrote:
> On Mon, 2018-01-08 at 15:33 +0800, Yixun Lan wrote:
>> These two patches are general improvement for meson pinctrl driver.
>> It make the two pinctrl trees (ee/ao) to share one uniform 'function' name
>> for
>> one hardwar
by Martin's question at [1]
[1]
http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=g...@mail.gmail.com
Yixun Lan (2):
pinctrl: meson: introduce a macro to have name/groups seperated
pinctrl: meson-axg: correct the pin expansion of UART_AO_B
drivers/pinctrl/meson/pinctrl
by Martin's question at [1]
[1]
http://lkml.kernel.org/r/CAFBinCCuQ-NK747+GHDkhZty_UMMgzCYOYFcNTrRDJgU8OM=g...@mail.gmail.com
Yixun Lan (2):
pinctrl: meson: introduce a macro to have name/groups seperated
pinctrl: meson-axg: correct the pin expansion of UART_AO_B
drivers/pinctrl/meson/pinctrl
but with different pin 'groups', as we face the sitiuation
that two pin groups may live inside different hardware domain (EE vs AO domain),
which mean we couldn't put them in one single group.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
drivers/pinctrl/meson/pinctrl-meson.h | 8 +
but with different pin 'groups', as we face the sitiuation
that two pin groups may live inside different hardware domain (EE vs AO domain),
which mean we couldn't put them in one single group.
Signed-off-by: Yixun Lan
---
drivers/pinctrl/meson/pinctrl-meson.h | 8 +---
1 file changed, 5 insertions
it short and more consistent.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c
b/drivers/pinctrl/meson/pinctrl-meson-axg.c
it short and more consistent.
Signed-off-by: Yixun Lan
---
drivers/pinctrl/meson/pinctrl-meson-axg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c
b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 1fda9d6c7ea3..308e5433bd04
HI Martin:
On 01/08/18 14:07, Yixun Lan wrote:
> Hi Martin
>
> On 01/08/18 04:19, Martin Blumenstingl wrote:
>> Hi Yixun,
>>
>> On Sat, Jan 6, 2018 at 1:10 AM, Yixun Lan <yixun@amlogic.com> wrote:
>>> Describe the pinctrl info for the UART controlle
HI Martin:
On 01/08/18 14:07, Yixun Lan wrote:
> Hi Martin
>
> On 01/08/18 04:19, Martin Blumenstingl wrote:
>> Hi Yixun,
>>
>> On Sat, Jan 6, 2018 at 1:10 AM, Yixun Lan wrote:
>>> Describe the pinctrl info for the UART controller which is found
>>&
Hi Martin
On 01/08/18 04:19, Martin Blumenstingl wrote:
> Hi Yixun,
>
> On Sat, Jan 6, 2018 at 1:10 AM, Yixun Lan <yixun@amlogic.com> wrote:
>> Describe the pinctrl info for the UART controller which is found
>> in the Meson-AXG SoCs.
>>
>> Signed-o
Hi Martin
On 01/08/18 04:19, Martin Blumenstingl wrote:
> Hi Yixun,
>
> On Sat, Jan 6, 2018 at 1:10 AM, Yixun Lan wrote:
>> Describe the pinctrl info for the UART controller which is found
>> in the Meson-AXG SoCs.
>>
>> Signed-off-by: Yixun Lan
>> --
The address space range is actually 0x18, fixed here.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 10 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch
Describe the pinctrl info for the UART controller which is found
in the Meson-AXG SoCs.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 97 ++
1 file changed, 97 insertions(+)
diff --git a/arch/arm64/boot/dts/a
The UART_A is connected to a BT module on the S400 board.
Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot
The UART_A is connected to a BT module on the S400 board.
Acked-by: Jerome Brunet
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic
The address space range is actually 0x18, fixed here.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 10 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson
Describe the pinctrl info for the UART controller which is found
in the Meson-AXG SoCs.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 97 ++
1 file changed, 97 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch
Jerome's Ack
[1]
http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com
[2]
http://lkml.kernel.org/r/20180105095621.196472-1-yixun@amlogic.com
Yixun Lan (5):
ARM64: dts: meson: uart: fix address space range
ARM64: dts: meson-axg: uart: drop legacy compatible name from
Jerome's Ack
[1]
http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com
[2]
http://lkml.kernel.org/r/20180105095621.196472-1-yixun@amlogic.com
Yixun Lan (5):
ARM64: dts: meson: uart: fix address space range
ARM64: dts: meson-axg: uart: drop legacy compatible name from
Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we may need to rely on bootloader for the initialization.
Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts |
ret = meson_uart_probe_clocks_legacy(pdev, port);
else
ret = meson_uart_probe_clocks(pdev, port);
Acked-by: Jerome Brunet <jbru...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 8 ++--
1 file ch
Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we may need to rely on bootloader for the initialization.
Acked-by: Jerome Brunet
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch
ret = meson_uart_probe_clocks_legacy(pdev, port);
else
ret = meson_uart_probe_clocks(pdev, port);
Acked-by: Jerome Brunet
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/ar
On 01/05/2018 06:28 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> Describe the pinctrl info for the UART controller which
.
>> +uart_a_cts_rts_pins: uart_a_cts_rts {
>> +
On 01/05/2018 06:28 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> Describe the pinctrl info for the UART controller which
.
>> +uart_a_cts_rts_pins: uart_a_cts_rts {
>> +
On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> The address space range is actually 0x18, fixed here.
>
> Isn't it the same for other meson SoC ? If they are compatible, it should.
> Could you please re-submit this cha
On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> The address space range is actually 0x18, fixed here.
>
> Isn't it the same for other meson SoC ? If they are compatible, it should.
> Could you please re-submit this cha
On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> For the UART controller in EE domain, they require 'pclk' to work.
>
> they ? "the driver" maybe ?
>
>> Current logic of the code will force to go for legacy
On 01/05/2018 06:30 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 17:56 +0800, Yixun Lan wrote:
>> For the UART controller in EE domain, they require 'pclk' to work.
>
> they ? "the driver" maybe ?
>
>> Current logic of the code will force to go for legacy
The address space range is actually 0x18, fixed here.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/a
The address space range is actually 0x18, fixed here.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index
For the UART controller in EE domain, they require 'pclk' to work.
Current logic of the code will force to go for legacy clock probe
if it found current compatible string match to 'amlogic,meson-ao-uart'.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic
For the UART controller in EE domain, they require 'pclk' to work.
Current logic of the code will force to go for legacy clock probe
if it found current compatible string match to 'amlogic,meson-ao-uart'.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
1 file
The UART_A is connect to a BT module in the S400 board.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/a
The UART_A is connect to a BT module in the S400 board.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index
Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we my rely on bootloader for the initialization.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm6
Explictly request the pinctrl info for the UART_AO_A controller,
otherwise we my rely on bootloader for the initialization.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg
Add the clock info description for the EE UART controller.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic
Add the clock info description for the EE UART controller.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 9636a7c5f6ed
T_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.
[1]
http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com
Yixun Lan (6):
ARM64: dts: meson-axg: uart: drop legacy compatible name fro
T_AO clock switch patch[1]
also, these patch request clocks, so they need the
tag:meson-clk-for-v4.16-2 from clk-meson's tree in order to compile.
[1]
http://lkml.kernel.org/r/20171215141741.175985-1-yixun@amlogic.com
Yixun Lan (6):
ARM64: dts: meson-axg: uart: drop legacy compatible name fro
Describe the pinctrl info for the UART controller which found
in the Meson-AXG SoCs.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/a
Describe the pinctrl info for the UART controller which found
in the Meson-AXG SoCs.
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 96 ++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch
Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.
Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogi
Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.
Reviewed-by: Neil Armstrong
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 ++
1
This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.
Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.
Reviewed-by: Neil Armstrong
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64
r/005735.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005694.html
[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005738.html
[6] git://github.com/BayLibre/clk-meson.git
Yixun Lan (2):
ARM64: dts: meson-axg: add ethernet mac controller
ARM64: dts:
r/005735.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005694.html
[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005738.html
[6] git://github.com/BayLibre/clk-meson.git
Yixun Lan (2):
ARM64: dts: meson-axg: add ethernet mac controller
ARM64: dts:
HI Kevin
On 12/16/2017 03:29 AM, Kevin Hilman wrote:
> Yixun Lan <yixun@amlogic.com> writes:
>
>> Add DT info for the stmmac ethernet MAC which found in
>> the Amlogic's Meson-AXG SoC, also describe the ethernet
>> pinctrl & clock information here.
>>
HI Kevin
On 12/16/2017 03:29 AM, Kevin Hilman wrote:
> Yixun Lan writes:
>
>> Add DT info for the stmmac ethernet MAC which found in
>> the Amlogic's Meson-AXG SoC, also describe the ethernet
>> pinctrl & clock information here.
>>
>> Reviewed-by: Nei
On 12/16/2017 03:48 AM, Kevin Hilman wrote:
> Yixun Lan <yixun@amlogic.com> writes:
>
>> This is DT part patchset for adding pinctrl support for
>> the Amlogic's Meson-AXG SoC.
>>
>> Changes since v3 at [3]
>> -- rebase to khilman's v4.16/dt6
On 12/16/2017 03:48 AM, Kevin Hilman wrote:
> Yixun Lan writes:
>
>> This is DT part patchset for adding pinctrl support for
>> the Amlogic's Meson-AXG SoC.
>>
>> Changes since v3 at [3]
>> -- rebase to khilman's v4.16/dt64 branch and re-send
>>
Hi Jerome
On 12/15/2017 11:01 PM, Jerome Brunet wrote:
> On Fri, 2017-12-15 at 22:59 +0800, Yixun Lan wrote:
>> Enable IR remote controller which found in Amlogic's Meson-AXG SoCs.
>>
>> Signed-off-by: Yixun Lan <yixun@amlogic.com>
>>
>> ---
>
Hi Jerome
On 12/15/2017 11:01 PM, Jerome Brunet wrote:
> On Fri, 2017-12-15 at 22:59 +0800, Yixun Lan wrote:
>> Enable IR remote controller which found in Amlogic's Meson-AXG SoCs.
>>
>> Signed-off-by: Yixun Lan
>>
>> ---
>>
>> Changes since v2 at
Enable IR remote controller which found in Amlogic's Meson-AXG SoCs.
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
Changes since v2 at [2]
- rebase to Kevin's v4.16/dt64 branch
- this patch depend on pinctrl DT driver
Changes since v1 at [1]:
- drop the compatbile 'amlogic,me
Enable IR remote controller which found in Amlogic's Meson-AXG SoCs.
Signed-off-by: Yixun Lan
---
Changes since v2 at [2]
- rebase to Kevin's v4.16/dt64 branch
- this patch depend on pinctrl DT driver
Changes since v1 at [1]:
- drop the compatbile 'amlogic,meson-gx-ir'
[2]
http
From: Sunny Luo <sunny@amlogic.com>
Add DT info for the SPICC controller which found in
the Amlogic's Meson-AXG SoC.
Signed-off-by: Sunny Luo <sunny@amlogic.com>
Signed-off-by: Yixun Lan <yixun@amlogic.com>
---
Changes int v2 since [1]
- rebase to Kevin's tree,
From: Sunny Luo
Add DT info for the SPICC controller which found in
the Amlogic's Meson-AXG SoC.
Signed-off-by: Sunny Luo
Signed-off-by: Yixun Lan
---
Changes int v2 since [1]
- rebase to Kevin's tree, branch v4.16/dt64
- this patch depend on clock & pinctrl DT patch
[1]
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