Re: [PATCH v2] dmaengine: k3dma: use the correct HiSilicon copyright

On 2021/4/1 下午7:50, Hao Fang wrote: s/Hisilicon/HiSilicon/g. It should use capital S, according to the official website. Signed-off-by: Hao Fang Thanks for the patch. Acked-by:  Zhangfei Gao --- V2: -remove the terms of use link. --- drivers/dma/k3dma.c | 4 ++-- 1 file changed, 2

Re: [PATCH] mmc: dw_mmc-k3: use the correct HiSilicon copyright

On Tue, Mar 30, 2021 at 2:46 PM Hao Fang wrote: > > s/Hisilicon/HiSilicon/g. > It should use capital S, according to > https://www.hisilicon.com/en/terms-of-use. > > Signed-off-by: Hao Fang Thanks for the fix. Acked-by: Zhangfei Gao > --- > drivers/mmc/host/dw_m

Re: [PATCH v2 3/3] PCI: set dma-can-stall for HiSilicon chip

Hi, Krzysztof On 2021/3/8 上午1:54, Krzysztof Wilczyński wrote: Hi, [...] Property dma-can-stall depends on patchset https://lore.kernel.org/linux-iommu/20210108145217.2254447-1-jean-phili...@linaro.org/ [...] If you plan to post another version of this patch to include the above link into

[PATCH v3 3/3] PCI: Set dma-can-stall for HiSilicon chips

/20210302092644.2553014-1-jean-phili...@linaro.org/ Signed-off-by: Zhangfei Gao Signed-off-by: Jean-Philippe Brucker Signed-off-by: Zhou Wang --- drivers/pci/quirks.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 873d27f..b866cdf 100644

[PATCH v3 2/3] PCI: Add a quirk to set pasid_no_tlp for HiSilicon chips

HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are actually on the AMBA bus. These fake PCI devices have PASID capability though not supporting TLP. Add a quirk to set pasid_no_tlp for these devices. Signed-off-by: Zhangfei Gao Signed-off-by: Jean-Philippe Brucker Signed

[PATCH v3 1/3] PCI: PASID can be enabled without TLP prefix

-by: Bjorn Helgaas Signed-off-by: Zhangfei Gao --- drivers/pci/ats.c | 2 +- include/linux/pci.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 793d381..88f981b 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -380,7 +38

[PATCH v3 0/3] PCI: Add a quirk to enable SVA for HiSilicon chip

kernel.org/linux-pci/20210112170230.GA1838341@bjorn-Precision-5520/ Zhangfei Gao (3): PCI: PASID can be enabled without TLP prefix PCI: Add a quirk to set pasid_no_tlp for HiSilicon chips PCI: Set dma-can-stall for HiSilicon chips drivers/pci/ats.c| 2 +- drive

[PATCH v2 2/3] PCI: Add a quirk to set pasid_no_tlp for HiSilicon chip

HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are actually on the AMBA bus. These fake PCI devices have PASID capability though not supporting TLP. Add a quirk to set pasid_no_tlp for these devices. Signed-off-by: Zhangfei Gao Signed-off-by: Jean-Philippe Brucker Signed

[PATCH v2 3/3] PCI: set dma-can-stall for HiSilicon chip

HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are actually on the AMBA bus. These fake PCI devices can support SVA via SMMU stall feature, by setting dma-can-stall for ACPI platforms. Signed-off-by: Zhangfei Gao Signed-off-by: Jean-Philippe Brucker Signed-off-by: Zhou Wang

[PATCH v2 1/3] PCI: PASID can be enabled without TLP prefix

-by: Bjorn Helgaas Signed-off-by: Zhangfei Gao --- drivers/pci/ats.c | 2 +- include/linux/pci.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index e36d601..b67b1b1 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -386,7 +38

[PATCH v2 0/3] PCI: Add a quirk to enable SVA for HiSilicon chip

x-pci/20210112170230.GA1838341@bjorn-Precision-5520/ Zhangfei Gao (3): PCI: PASID can be enabled without TLP prefix PCI: Add a quirk to set pasid_no_tlp for HiSilicon chip PCI: set dma-can-stall for HiSilicon chip drivers/pci/ats.c| 2 +- drivers/pci/quirks.c | 27 ++

Re: [PATCH] PCI: Add a quirk to enable SVA for HiSilicon chip

Hi, Bjorn Thanks for the suggestion. On 2021/1/13 上午1:02, Bjorn Helgaas wrote: On Tue, Jan 12, 2021 at 02:49:52PM +0800, Zhangfei Gao wrote: HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are actually on the AMBA bus. These fake PCI devices can not support tlp and have

[PATCH] PCI: Add a quirk to enable SVA for HiSilicon chip

-by: Zhangfei Gao Signed-off-by: Jean-Philippe Brucker Signed-off-by: Zhou Wang --- Property dma-can-stall depends on patchset https://lore.kernel.org/linux-iommu/20210108145217.2254447-1-jean-phili...@linaro.org/ drivers/pci/quirks.c | 25 + 1 file changed, 25 insertions(+) diff

Re: [PATCH] uacce: Use kobj_to_dev() instead of container_of()

On 2020/8/20 上午10:16, Tian Tao wrote: Use kobj_to_dev() instead of container_of() Signed-off-by: Tian Tao Reviewed-by: Zhou Wang Acked-by: Zhangfei Gao Thanks --- drivers/misc/uacce/uacce.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/uacce

Re: [PATCH] uacce: fix some coding styles

On 2020/7/30 下午2:13, Kai Ye wrote: 1. delete some redundant code. 2. modify the module author information. Signed-off-by: Kai Ye Thanks Kai Acked-by: Zhangfei Gao Thanks

Re: [PATCH] uacce: fix some coding styles

On 2020/7/20 下午3:18, Kai Ye wrote: 1. add some parameter check. 2. delete some redundant code. 3. modify the module author information. Signed-off-by: Kai Ye Reviewed-by: Zhou Wang Thanks Kai. --- drivers/misc/uacce/uacce.c | 28 +--- 1 file changed, 13

Re: [PATCH 0/2] Introduce PCI_FIXUP_IOMMU

Hi, Joerg On 2020/6/22 下午7:55, Joerg Roedel wrote: On Thu, Jun 04, 2020 at 09:33:07PM +0800, Zhangfei Gao wrote: +++ b/drivers/iommu/iommu.c @@ -2418,6 +2418,10 @@ int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode,     fwspec->iommu_fwnode = iommu_fwn

Re: [PATCH 0/2] Introduce PCI_FIXUP_IOMMU

Hi, Bjorn On 2020/6/16 上午7:52, Bjorn Helgaas wrote: On Sat, Jun 13, 2020 at 10:30:56PM +0800, Zhangfei Gao wrote: On 2020/6/11 下午9:44, Bjorn Helgaas wrote: +++ b/drivers/iommu/iommu.c @@ -2418,6 +2418,10 @@ int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode

[PATCH] uacce: remove uacce_vma_fault

off-by: Zhangfei Gao --- drivers/misc/uacce/uacce.c | 9 - 1 file changed, 9 deletions(-) diff --git a/drivers/misc/uacce/uacce.c b/drivers/misc/uacce/uacce.c index 107028e..aa91f69 100644 --- a/drivers/misc/uacce/uacce.c +++ b/drivers/misc/uacce/uacce.c @@ -179,14 +179,6 @@ static

[PATCH v2] crypto: hisilicon - fix strncpy warning with strscpy

Use strscpy to fix the warning warning: 'strncpy' specified bound 64 equals destination size Reported-by: kernel test robot Signed-off-by: Zhangfei Gao --- v2: Use strscpy instead of strlcpy since better truncation handling suggested by Herbert Rebase to 5.8-rc1 drivers/crypto

Re: [PATCH 0/2] Introduce PCI_FIXUP_IOMMU

On 2020/6/11 下午9:44, Bjorn Helgaas wrote: +++ b/drivers/iommu/iommu.c @@ -2418,6 +2418,10 @@ int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, fwspec->iommu_fwnode = iommu_fwnode; fwspec->ops = ops; dev_iommu_fwspec_set(dev,

Re: [RFC PATCH] PCI: Remove End-End TLP as PASID dependency

On 2020/6/12 上午1:41, Bjorn Helgaas wrote: [+cc Sinan] On Wed, Jun 10, 2020 at 12:18:14PM +0800, Zhangfei Gao wrote: Some platform devices appear as PCI and have PCI cfg space, but are actually on the AMBA bus. They can support PASID via smmu stall feature, but does not support tlp since

Re: [PATCH 0/2] Introduce PCI_FIXUP_IOMMU

On 2020/6/10 上午12:49, Bjorn Helgaas wrote: On Tue, Jun 09, 2020 at 11:15:06AM +0200, Arnd Bergmann wrote: On Tue, Jun 9, 2020 at 6:02 AM Zhangfei Gao wrote: On 2020/6/9 上午12:41, Bjorn Helgaas wrote: On Mon, Jun 08, 2020 at 10:54:15AM +0800, Zhangfei Gao wrote: On 2020/6/6 上午7:19, Bjorn

Re: [RFC PATCH] PCI: Remove End-End TLP as PASID dependency

On 2020/6/10 下午3:46, Jean-Philippe Brucker wrote: On Wed, Jun 10, 2020 at 12:18:14PM +0800, Zhangfei Gao wrote: Some platform devices appear as PCI and have PCI cfg space, but are actually on the AMBA bus. They can support PASID via smmu stall feature, but does not support tlp since

[RFC PATCH] PCI: Remove End-End TLP as PASID dependency

Some platform devices appear as PCI and have PCI cfg space, but are actually on the AMBA bus. They can support PASID via smmu stall feature, but does not support tlp since they are not real pci devices. So remove tlp as a PASID dependency. Signed-off-by: Zhangfei Gao --- drivers/pci/ats.c | 3

Re: [PATCH 0/2] Introduce PCI_FIXUP_IOMMU

Hi, Bjorn On 2020/6/9 上午12:41, Bjorn Helgaas wrote: On Mon, Jun 08, 2020 at 10:54:15AM +0800, Zhangfei Gao wrote: On 2020/6/6 上午7:19, Bjorn Helgaas wrote: On Thu, Jun 04, 2020 at 09:33:07PM +0800, Zhangfei Gao wrote: On 2020/6/2 上午1:41, Bjorn Helgaas wrote: On Thu, May 28, 2020 at 09:33

Re: [PATCH 0/2] Introduce PCI_FIXUP_IOMMU

Hi, Bjorn On 2020/6/6 上午7:19, Bjorn Helgaas wrote: On Thu, Jun 04, 2020 at 09:33:07PM +0800, Zhangfei Gao wrote: On 2020/6/2 上午1:41, Bjorn Helgaas wrote: On Thu, May 28, 2020 at 09:33:44AM +0200, Joerg Roedel wrote: On Wed, May 27, 2020 at 01:18:42PM -0500, Bjorn Helgaas wrote

Re: [PATCH] crypto: hisilicon - fix strncpy warning with strlcpy

On 2020/6/5 下午11:49, Eric Biggers wrote: On Fri, Jun 05, 2020 at 11:26:20PM +0800, Zhangfei Gao wrote: On 2020/6/5 下午8:17, Herbert Xu wrote: On Fri, Jun 05, 2020 at 05:34:32PM +0800, Zhangfei Gao wrote: Will add a check after the copy.     strlcpy(interface.name, pdev->driver-&g

Re: [PATCH] crypto: hisilicon - fix strncpy warning with strlcpy

On 2020/6/5 下午8:17, Herbert Xu wrote: On Fri, Jun 05, 2020 at 05:34:32PM +0800, Zhangfei Gao wrote: Will add a check after the copy.     strlcpy(interface.name, pdev->driver->name, sizeof(interface.name));     if (strlen(pdev->driver->name) != strlen(in

Re: [PATCH] crypto: hisilicon - fix strncpy warning with strlcpy

On 2020/6/4 下午2:50, Herbert Xu wrote: On Thu, Jun 04, 2020 at 02:44:16PM +0800, Zhangfei Gao wrote: I think it is fine. 1. Currently the name size is 64, bigger enough. Simply grep in driver name, 64 should be enough. We can make it larger when there is a request. 2. it does not matter what

Re: [PATCH 0/2] Introduce PCI_FIXUP_IOMMU

On 2020/6/2 上午1:41, Bjorn Helgaas wrote: On Thu, May 28, 2020 at 09:33:44AM +0200, Joerg Roedel wrote: On Wed, May 27, 2020 at 01:18:42PM -0500, Bjorn Helgaas wrote: Is this slowdown significant? We already iterate over every device when applying PCI_FIXUP_FINAL quirks, so if we used the

Re: [PATCH] crypto: hisilicon - fix strncpy warning with strlcpy

On 2020/6/4 下午2:18, Herbert Xu wrote: On Thu, Jun 04, 2020 at 02:10:37PM +0800, Zhangfei Gao wrote: Should this even allow truncation? Perhaps it'd be better to fail in case of an overrun? I think we do not need consider overrun, since it at most copy size-1 bytes to dest. From the manual

Re: [PATCH] crypto: hisilicon - fix strncpy warning with strlcpy

On 2020/6/4 上午11:39, Herbert Xu wrote: On Thu, Jun 04, 2020 at 11:32:04AM +0800, Zhangfei Gao wrote: Use strlcpy to fix the warning warning: 'strncpy' specified bound 64 equals destination size [-Wstringop-truncation] Reported-by: kernel test robot Signed-off-by: Zhangfei Gao

[PATCH] crypto: hisilicon - fix strncpy warning with strlcpy

Use strlcpy to fix the warning warning: 'strncpy' specified bound 64 equals destination size [-Wstringop-truncation] Reported-by: kernel test robot Signed-off-by: Zhangfei Gao --- drivers/crypto/hisilicon/qm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers

Re: [PATCH 2/2] iommu: calling pci_fixup_iommu in iommu_fwspec_init

On 2020/5/27 下午5:01, Greg Kroah-Hartman wrote: On Tue, May 26, 2020 at 07:49:09PM +0800, Zhangfei Gao wrote: Calling pci_fixup_iommu in iommu_fwspec_init, which alloc iommu_fwnode. Some platform devices appear as PCI but are actually on the AMBA bus, and they need fixup in drivers/pci

Re: [PATCH 0/2] Introduce PCI_FIXUP_IOMMU

Hi, Bjorn On 2020/5/28 上午2:18, Bjorn Helgaas wrote: On Tue, May 26, 2020 at 07:49:07PM +0800, Zhangfei Gao wrote: Some platform devices appear as PCI but are actually on the AMBA bus, and they need fixup in drivers/pci/quirks.c handling iommu_fwnode. Here introducing PCI_FIXUP_IOMMU, which

Re: [PATCH 0/2] Introduce PCI_FIXUP_IOMMU

On 2020/5/27 下午5:53, Arnd Bergmann wrote: On Wed, May 27, 2020 at 11:00 AM Greg Kroah-Hartman wrote: On Tue, May 26, 2020 at 07:49:07PM +0800, Zhangfei Gao wrote: Some platform devices appear as PCI but are actually on the AMBA bus, Why would these devices not just show up on the AMBA bus

Re: [PATCH 1/2] PCI: Introduce PCI_FIXUP_IOMMU

Hi, Christoph On 2020/5/26 下午10:46, Christoph Hellwig wrote: On Tue, May 26, 2020 at 07:49:08PM +0800, Zhangfei Gao wrote: Some platform devices appear as PCI but are actually on the AMBA bus, and they need fixup in drivers/pci/quirks.c handling iommu_fwnode. Here introducing PCI_FIXUP_IOMMU

Re: [PATCH 0/2] Let pci_fixup_final access iommu_fwnode

On 2020/5/25 下午9:43, Joerg Roedel wrote: On Tue, May 12, 2020 at 12:08:29PM +0800, Zhangfei Gao wrote: Some platform devices appear as PCI but are actually on the AMBA bus, and they need fixup in drivers/pci/quirks.c handling iommu_fwnode. So calling pci_fixup_final after iommu_fwnode

[PATCH 2/2] iommu: calling pci_fixup_iommu in iommu_fwspec_init

Calling pci_fixup_iommu in iommu_fwspec_init, which alloc iommu_fwnode. Some platform devices appear as PCI but are actually on the AMBA bus, and they need fixup in drivers/pci/quirks.c handling iommu_fwnode. So calling pci_fixup_iommu after iommu_fwnode is allocated. Signed-off-by: Zhangfei Gao

[PATCH 1/2] PCI: Introduce PCI_FIXUP_IOMMU

as all devices in fixup final list will be reprocessed. Suggested-by: Joerg Roedel Signed-off-by: Zhangfei Gao --- drivers/pci/quirks.c | 7 +++ include/asm-generic/vmlinux.lds.h | 3 +++ include/linux/pci.h | 8 3 files changed, 18 insertions(+) diff --git

[PATCH 0/2] Introduce PCI_FIXUP_IOMMU

e_sva); [1] https://www.spinics.net/lists/iommu/msg44591.html [2] https://www.spinics.net/lists/linux-pci/msg94559.html Zhangfei Gao (2): PCI: Introduce PCI_FIXUP_IOMMU iommu: calling pci_fixup_iommu in iommu_fwspec_init drivers/iommu/iommu.c | 4 drivers/pci/quirks.c

Re: [PATCH 0/2] Let pci_fixup_final access iommu_fwnode

Hi, Joerg On 2020/5/12 下午12:08, Zhangfei Gao wrote: Some platform devices appear as PCI but are actually on the AMBA bus, and they need fixup in drivers/pci/quirks.c handling iommu_fwnode. So calling pci_fixup_final after iommu_fwnode is allocated. For example: Hisilicon platform device need

[PATCH 0/2] Let pci_fixup_final access iommu_fwnode

_pcie_sva); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); Zhangfei Gao (2): iommu/of: Let pci_fixup_final access iommu_fwnode ACPI/IORT: Let pci_fixup_final access iommu_fwnode drivers/acpi/arm64/iort.c | 1 + drivers/iommu/of_iommu.c | 1 + 2 files c

[PATCH 1/2] iommu/of: Let pci_fixup_final access iommu_fwnode

Calling pci_fixup_final after of_pci_iommu_init, which alloc iommu_fwnode. Some platform devices appear as PCI but are actually on the AMBA bus, and they need fixup in drivers/pci/quirks.c handling iommu_fwnode. So calling pci_fixup_final after iommu_fwnode is allocated. Signed-off-by: Zhangfei

[PATCH 2/2] ACPI/IORT: Let pci_fixup_final access iommu_fwnode

Calling pci_fixup_final after iommu_fwspec_init, which alloc iommu_fwnode. Some platform devices appear as PCI but are actually on the AMBA bus, and they need fixup in drivers/pci/quirks.c handling iommu_fwnode. So calling pci_fixup_final after iommu_fwnode is allocated. Signed-off-by: Zhangfei

[PATCH v6 1/3] uacce: Add documents for uacce

Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao --- Documentation/misc-devices/uacce.rst | 297 +++ 1 file changed, 297 insertions(+) create mode 100644 Documentation/misc-devices/uacce.rst diff --git a/Documentation/misc-devices/uacce.rst b/Documentation

[PATCH v6 0/3] Add uacce module for Accelerator

: uacce: Add documents for uacce uacce: add uacce driver Zhangfei Gao (1): crypto: hisilicon - register zip engine to uacce Documentation/ABI/testing/sysfs-driver-uacce | 65 ++ Documentation/misc-devices/uacce.rst | 297 drivers/crypto/hisilicon/qm.c| 254

[PATCH v5 3/3] crypto: hisilicon - register zip engine to uacce

qm using uacce as an example, will resubmit after uacce is merged. Signed-off-by: Zhangfei Gao Signed-off-by: Zhou Wang --- drivers/crypto/hisilicon/qm.c | 254 ++-- drivers/crypto/hisilicon/qm.h | 13 +- drivers/crypto/hisilicon/zip/zip_main.c

[PATCH v5 2/3] uacce: add uacce driver

the hardware resource by interact with the queue file. By mmap the queue file space to user space, the process can directly put requests to the hardware without syscall to the kernel space. Signed-off-by: Kenneth Lee Signed-off-by: Zaibo Xu Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao

[PATCH v5 0/3] Add uacce module for Accelerator

no matter how, this can be a solid start point for new processor to be used as an "accelerator" as this is the essential requirement. Kenneth Lee (2): uacce: Add documents for uacce uacce: add uacce driver Zhangfei Gao (1): crypto: hisilicon - register zip engine to uacce Documen

[PATCH v5 1/3] uacce: Add documents for uacce

Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao --- Documentation/misc-devices/uacce.rst | 297 +++ 1 file changed, 297 insertions(+) create mode 100644 Documentation/misc-devices/uacce.rst diff --git a/Documentation/misc-devices/uacce.rst b/Documentation

[RESEND PATCH v4 2/2] uacce: add uacce driver

the hardware resource by interact with the queue file. By mmap the queue file space to user space, the process can directly put requests to the hardware without syscall to the kernel space. Signed-off-by: Kenneth Lee Signed-off-by: Zaibo Xu Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao

[RESEND PATCH v4 1/2] uacce: Add documents for uacce

Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao --- Documentation/misc-devices/uacce.rst | 297 +++ 1 file changed, 297 insertions(+) create mode 100644 Documentation/misc-devices/uacce.rst diff --git a/Documentation/misc-devices/uacce.rst b/Documentation

[RESEND PATCH v4 0/2] Add uacce module for Accelerator

Uacce (Unified/User-space-access-intended Accelerator Framework) targets to provide Shared Virtual Addressing (SVA) between accelerators and processes. So accelerator can access any data structure of the main cpu. This differs from the data sharing between cpu and io device, which share data

[PATCH v4 2/2] uacce: add uacce driver

the hardware resource by interact with the queue file. By mmap the queue file space to user space, the process can directly put requests to the hardware without syscall to the kernel space. Signed-off-by: Kenneth Lee Signed-off-by: Zaibo Xu Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao

[PATCH v4 0/2] Add uacce module for Accelerator

Uacce (Unified/User-space-access-intended Accelerator Framework) targets to provide Shared Virtual Addressing (SVA) between accelerators and processes. So accelerator can access any data structure of the main cpu. This differs from the data sharing between cpu and io device, which share data

[PATCH v4 1/2] uacce: Add documents for uacce

Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao --- Documentation/misc-devices/uacce.rst | 308 +++ 1 file changed, 308 insertions(+) create mode 100644 Documentation/misc-devices/uacce.rst diff --git a/Documentation/misc-devices/uacce.rst b/Documentation

[PATCH v3 1/2] uacce: Add documents for uacce

Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao --- Documentation/misc-devices/uacce.rst | 309 +++ 1 file changed, 309 insertions(+) create mode 100644 Documentation/misc-devices/uacce.rst diff --git a/Documentation/misc-devices/uacce.rst b/Documentation

[PATCH v3 2/2] uacce: add uacce driver

the hardware resource by interact with the queue file. By mmap the queue file space to user space, the process can directly put requests to the hardware without syscall to the kernel space. Signed-off-by: Kenneth Lee Signed-off-by: Zaibo Xu Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao

[PATCH v3 0/2] Add uacce module for Accelerator

Uacce (Unified/User-space-access-intended Accelerator Framework) targets to provide Shared Virtual Addressing (SVA) between accelerators and processes. So accelerator can access any data structure of the main cpu. This differs from the data sharing between cpu and io device, which share data

[PATCH v2 1/2] uacce: Add documents for uacce

Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao --- Documentation/misc-devices/uacce.rst | 309 +++ 1 file changed, 309 insertions(+) create mode 100644 Documentation/misc-devices/uacce.rst diff --git a/Documentation/misc-devices/uacce.rst b/Documentation

[PATCH v2 2/2] uacce: add uacce driver

the hardware resource by interact with the queue file. By mmap the queue file space to user space, the process can directly put requests to the hardware without syscall to the kernel space. Signed-off-by: Kenneth Lee Signed-off-by: Zaibo Xu Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao

[PATCH v2 0/2] Add uacce module for Accelerator

Uacce (Unified/User-space-access-intended Accelerator Framework) targets to provide Shared Virtual Addressing (SVA) between accelerators and processes. So accelerator can access any data structure of the main cpu. This differs from the data sharing between cpu and io device, which share data

[PATCH 2/2] uacce: add uacce module

Uacce also manages unify addresses between the hardware and user space of the process. So they can share the same virtual address in the communication. Signed-off-by: Kenneth Lee Signed-off-by: Zaibo Xu Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao --- drivers/misc/Kconfig|1

[PATCH 1/2] uacce: Add documents for WarpDrive/uacce

ified/User-space-access-intended Accelerator Framework". This patch add document to explain how it works. Signed-off-by: Kenneth Lee Signed-off-by: Zaibo Xu Signed-off-by: Zhou Wang Signed-off-by: Zhangfei Gao --- Documentation/misc-devices/warpdrive.rst | 351 +

[PATCH 0/2] A General Accelerator Framework, WarpDrive

*WarpDrive* is a general accelerator framework for the user application to access the hardware without going through the kernel in data path. WarpDrive is the name for the whole framework. The component in kernel is called uacce, meaning "Unified/User-space-access-intended Accelerator Framework".

Re: [PATCH 01/11] hisi_sas: add v2 hw support for ECC and AXI bus fatal error

On Wed, Nov 23, 2016 at 4:59 PM, John Garry <john.ga...@huawei.com> wrote: > On 16/11/2016 01:47, Zhangfei Gao wrote: >> >> On Mon, Nov 7, 2016 at 8:48 PM, John Garry <john.ga...@huawei.com> wrote: >>> >>> From: Xiang Chen <chenxian...@his

Re: [PATCH 01/11] hisi_sas: add v2 hw support for ECC and AXI bus fatal error

On Wed, Nov 23, 2016 at 4:59 PM, John Garry wrote: > On 16/11/2016 01:47, Zhangfei Gao wrote: >> >> On Mon, Nov 7, 2016 at 8:48 PM, John Garry wrote: >>> >>> From: Xiang Chen Reviewed-by: Zhangfei Gao >>> >>> For ECC 1bit error, l

Re: [PATCH 05/11] hisi_sas: replace WARN_ON() with dev_warn() for internal abort

; Signed-off-by: John Garry <john.ga...@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei@linaro.org> Sorry, miss this one.

Re: [PATCH 05/11] hisi_sas: replace WARN_ON() with dev_warn() for internal abort

On Mon, Nov 7, 2016 at 8:48 PM, John Garry wrote: > From: Xiang Chen > > Replace WARN_ON() with dev_warn() print when internal abort fails. > > Signed-off-by: Xiang Chen > Signed-off-by: John Garry Reviewed-by: Zhangfei Gao Sorry, miss this one.

Re: [PATCH 06/11] hisi_sas: modify return value of hisi_sas_query_task()

for LLDD errors just return TMF_RESP_FUNC_FAILED. > > Signed-off-by: Xiang Chen <chenxian...@hisilicon.com> > Signed-off-by: John Garry <john.ga...@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei@linaro.org>

Re: [PATCH 06/11] hisi_sas: modify return value of hisi_sas_query_task()

ed-off-by: Xiang Chen > Signed-off-by: John Garry Reviewed-by: Zhangfei Gao

Re: [PATCH 09/11] hisi_sas: check SATA FIS when directly attaching SATA device

restart OOB. > > Signed-off-by: Xiang Chen <chenxian...@hisilicon.com> > Signed-off-by: John Garry <john.ga...@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei@linaro.org>

Re: [PATCH 09/11] hisi_sas: check SATA FIS when directly attaching SATA device

igned-off-by: John Garry Reviewed-by: Zhangfei Gao

Re: [PATCH 11/11] hisi_sas: add PHY set linkrate support for v1 and v2 hw

> Signed-off-by: John Garry <john.ga...@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei@linaro.org>

Re: [PATCH 11/11] hisi_sas: add PHY set linkrate support for v1 and v2 hw

On Mon, Nov 7, 2016 at 8:48 PM, John Garry wrote: > From: Xiang Chen > > Add the function to set PHY min and max linkrate through > sysfs interface. > > Signed-off-by: Xiang Chen > Signed-off-by: John Garry Reviewed-by: Zhangfei Gao

Re: [PATCH 01/11] hisi_sas: add v2 hw support for ECC and AXI bus fatal error

On Mon, Nov 7, 2016 at 8:48 PM, John Garry wrote: > From: Xiang Chen > > For ECC 1bit error, logic can recover it, so we only print > a warning. > For ECC multi-bit and AXI bus fatal error, we panic. Is it possible to recover via resetting phy

Re: [PATCH 01/11] hisi_sas: add v2 hw support for ECC and AXI bus fatal error

On Mon, Nov 7, 2016 at 8:48 PM, John Garry wrote: > From: Xiang Chen > > For ECC 1bit error, logic can recover it, so we only print > a warning. > For ECC multi-bit and AXI bus fatal error, we panic. Is it possible to recover via resetting phy and device etc instead of panic? Thanks

Re: [PATCH 03/11] hisi_sas: only process broadcast change in phy_bcast_v2_hw()

rocess this. > > Signed-off-by: Xiang Chen <chenxian...@hisilicon.com> > Signed-off-by: John Garry <john.ga...@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei@linaro.org>

Re: [PATCH 03/11] hisi_sas: only process broadcast change in phy_bcast_v2_hw()

y: John Garry Reviewed-by: Zhangfei Gao

Re: [PATCH 08/11] hisi_sas: modify some values in get_ata_protocol()

y: John Garry <john.ga...@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei@linaro.org>

Re: [PATCH 08/11] hisi_sas: modify some values in get_ata_protocol()

On Mon, Nov 7, 2016 at 8:48 PM, John Garry wrote: > From: Xiang Chen > > Modify and add some SATA commands according to SATA protocol. > > Signed-off-by: Xiang Chen > Signed-off-by: John Garry Reviewed-by: Zhangfei Gao

Re: [PATCH 07/11] hisi_sas: delete repeated configuration in free_device_v2_hw()

t; > Signed-off-by: Xiang Chen <chenxian...@hisilicon.com> > Signed-off-by: John Garry <john.ga...@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei@linaro.org>

Re: [PATCH 10/11] hisi_sas: use atomic64_t for hisi_sas_device.running_req

g_req is not thread-safe. > > As such, the value for running_req may be actually incorrect, > so use atomic64_t instead. > > Signed-off-by: John Garry <john.ga...@huawei.com> > Reviewed-by: Xiang Chen <chenxian...@hisilicon.com> Reviewed-by: Zhangfei Gao <zhangfei@linaro.org>

Re: [PATCH 07/11] hisi_sas: delete repeated configuration in free_device_v2_hw()

On Mon, Nov 7, 2016 at 8:48 PM, John Garry wrote: > From: Xiang Chen > > Delete repeated configuration items for hisi_sas_device() when > we free a device. These items are now only set in > hisi_sas_dev_gone(). > > Signed-off-by: Xiang Chen > Signed-off-by: John Garry

Re: [PATCH 10/11] hisi_sas: use atomic64_t for hisi_sas_device.running_req

he value for running_req may be actually incorrect, > so use atomic64_t instead. > > Signed-off-by: John Garry > Reviewed-by: Xiang Chen Reviewed-by: Zhangfei Gao

Re: [PATCH 04/11] hisi_sas: fix port form bug in hisi_sas_port_notify_formed()

con.com> > Signed-off-by: John Garry <john.ga...@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei@linaro.org>

Re: [PATCH 04/11] hisi_sas: fix port form bug in hisi_sas_port_notify_formed()

On Mon, Nov 7, 2016 at 8:48 PM, John Garry wrote: > From: Xiang Chen > > When we form a wideport, we should use hardware PHY port_id instead > of sas_phy->id. > > Signed-off-by: Xiang Chen > Signed-off-by: John Garry Reviewed-by: Zhangfei Gao

Re: [PATCH 02/11] hisi_sas: alloc queue id of slot according to device id

nternal abort, the > allocation method is chosen to be the same for consistency. > > Signed-off-by: Xiang Chen <chenxian...@hisilicon.com> > Signed-off-by: John Garry <john.ga...@huawei.com> Reviewed-by: Zhangfei Gao <zhangfei@linaro.org>

Re: [PATCH 02/11] hisi_sas: alloc queue id of slot according to device id

ame for consistency. > > Signed-off-by: Xiang Chen > Signed-off-by: John Garry Reviewed-by: Zhangfei Gao

Re: [PATCH 0/5] hisi_sas: v2 hw SATA fixes

t for >4 SATA phys > hisi_sas: for v2 hw only set ITCT qw2 for SAS device > hisi_sas: update driver version to 1.4 For the series, Reviewed-by: Zhangfei Gao <zhangfei@linaro.org> Thanks

Re: [PATCH 0/5] hisi_sas: v2 hw SATA fixes

isi_sas: for v2 hw only set ITCT qw2 for SAS device > hisi_sas: update driver version to 1.4 For the series, Reviewed-by: Zhangfei Gao Thanks

[PATCH v4 4/4] phy: add phy-hi6220-usb

Add usb phy controller for hi6220 platform Signed-off-by: Zhangfei Gao --- drivers/phy/Kconfig | 9 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-hi6220-usb.c | 306 +++ 3 files changed, 316 insertions(+) create mode 100644 drivers

[PATCH v4 3/4] usb: dwc2: platform: add hi6220 support

Signed-off-by: Zhangfei Gao --- drivers/usb/dwc2/platform.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c index ae095f0..f7c67db 100644 --- a/drivers/usb/dwc2/platform.c +++ b/drivers/usb/dwc2

[PATCH v4 1/4] Documentation: dt-bindings: add dt binding info for hi6220 dwc2

Add necessary dwc2 binding documentation for Hisilicon soc: hi6220 Signed-off-by: Zhangfei Gao --- Documentation/devicetree/bindings/usb/dwc2.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt

[PATCH v4 0/4] add usb support for hi6220

: hi6220 usb controller is inherited from dwc2 add phy accordingly support otg gadget/host Zhangfei Gao (4): Documentation: dt-bindings: add dt binding info for hi6220 dwc2 Documentation: dt-bindings: add dt binding info for hi6220 usb: dwc2: platform: add hi6220 support phy: add phy-hi6220

[PATCH v4 2/4] Documentation: dt-bindings: add dt binding info for hi6220

Signed-off-by: Zhangfei Gao --- .../devicetree/bindings/usb/hi6220-usb.txt | 49 ++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/hi6220-usb.txt diff --git a/Documentation/devicetree/bindings/usb/hi6220-usb.txt b

[PATCH v4 4/4] phy: add phy-hi6220-usb

Add usb phy controller for hi6220 platform Signed-off-by: Zhangfei Gao zhangfei@linaro.org --- drivers/phy/Kconfig | 9 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-hi6220-usb.c | 306 +++ 3 files changed, 316 insertions

[PATCH v4 3/4] usb: dwc2: platform: add hi6220 support

Signed-off-by: Zhangfei Gao zhangfei@linaro.org --- drivers/usb/dwc2/platform.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c index ae095f0..f7c67db 100644 --- a/drivers/usb/dwc2/platform.c +++ b

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