On Mon, Apr 12, 2021 at 7:31 PM Andreas Schwab wrote:
>
> On Mär 31 2021, Zong Li wrote:
>
> > I found that the gemgxlpll was disabled immediately by power
> > management after macb driver install. The mainline's defconfig doesn't
> > enable CONFIG_PM, so the network
On Mon, Mar 29, 2021 at 6:37 PM Andreas Schwab wrote:
>
> On Mär 29 2021, Zong Li wrote:
>
> > Yes, I could get the network problem by using the defconfig you
> > provided, the system hung up when executing 'ifconfig' immediately
> > after installing macb driver m
On Fri, Mar 26, 2021 at 5:24 PM Andreas Schwab wrote:
>
> On Mär 26 2021, Zong Li wrote:
>
> > 1. Boot on openSUSE-Tumbleweed-RISC-V-JeOS-hifiveunleashed.riscv64.raw.xz
> > w/ plugging ethernet cable
> > - It seems that I encountered a different situation with you,
On Thu, Mar 25, 2021 at 5:22 PM Andreas Schwab wrote:
>
> On Mär 25 2021, Zong Li wrote:
>
> > take a look at this again. Could you also let me know which bootloader
> > you used (FSBL or U-boot-SPL)? Thanks.
>
> U-Boot SPL
>
> Please try this image:
>
> h
On Wed, Mar 24, 2021 at 6:36 PM Andreas Schwab wrote:
>
> Were you able to reproduce the problem?
>
Hi Andreas,
Sorry, I'm not available past few days, I'm just coming back, I would
take a look at this again. Could you also let me know which bootloader
you used (FSBL or U-boot-SPL)? Thanks.
>
On Thu, Mar 18, 2021 at 10:07 AM Zong Li wrote:
>
> On Wed, Mar 17, 2021 at 3:45 AM Andreas Schwab wrote:
> >
> > On Dez 09 2020, Zong Li wrote:
> >
> > > Add a driver for the SiFive FU740 PRCI IP block, which handles more
> > > clocks than FU540
On Wed, Mar 17, 2021 at 3:45 AM Andreas Schwab wrote:
>
> On Dez 09 2020, Zong Li wrote:
>
> > Add a driver for the SiFive FU740 PRCI IP block, which handles more
> > clocks than FU540. These patches also refactor the original
> > implementation by spliting the depend
From: Pragnesh Patel
Add new functions "sifive_prci_clock_enable(), sifive_prci_clock_disable()
and sifive_clk_is_enabled()" to enable or disable the PRCI clock
Signed-off-by: Pragnesh Patel
Tested-by: Zong Li
---
drivers/clk/sifive/fu540-prci.c | 6 +++
drivers/clk/sifive/fu
://www.sifive.com/boards/hifive-unmatched
This driver contains bug fixes and contributions from
Henry Styles
Erik Danie
Pragnesh Patel
Signed-off-by: Zong Li
Reviewed-by: Pragnesh Patel
Acked-by: Palmer Dabbelt
Cc: Henry Styles
Cc: Erik Danie
Cc: Pragnesh Patel
---
drivers/clk/sifive/Kconfig
The clk enable bit should be 31 instead of 24.
Signed-off-by: Zong Li
Reported-by: Pragnesh Patel
---
drivers/clk/sifive/sifive-prci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index 7e509dfb72d1
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Reviewed-by: Pragnesh Patel
---
arch/riscv/Kconfig.socs | 2 +-
drivers/clk/sifive/Kconfig | 6
to create patches.
- Rebase code to kernel v5.10-rc3.
Pragnesh Patel (1):
clk: sifive: Add clock enable and disable ops
Zong Li (4):
clk: sifive: Extract prci core to common base
clk: sifive: Use common name for prci configuration
clk: sifive: Add a driver for the SiFive FU740 PRCI IP b
it needs to get match data in probe
callback function, then use the data for initialization.
Signed-off-by: Zong Li
Reviewed-by: Pragnesh Patel
Acked-by: Palmer Dabbelt
---
drivers/clk/sifive/Makefile | 2 +-
drivers/clk/sifive/fu540-prci.c | 592
; [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Zong-Li/clk-add-driver-for-the-Si
The clk enable bit should be 31 instead of 24.
Signed-off-by: Zong Li
Reported-by: Pragnesh Patel
---
drivers/clk/sifive/sifive-prci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index 802fc8fb9c09
://www.sifive.com/boards/hifive-unmatched
This driver contains bug fixes and contributions from
Henry Styles
Erik Danie
Pragnesh Patel
Signed-off-by: Zong Li
Reviewed-by: Pragnesh Patel
Acked-by: Palmer Dabbelt
Cc: Henry Styles
Cc: Erik Danie
Cc: Pragnesh Patel
---
drivers/clk/sifive/Kconfig
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Reviewed-by: Pragnesh Patel
---
arch/riscv/Kconfig.socs | 2 +-
drivers/clk/sifive/Kconfig | 6
From: Pragnesh Patel
Add new functions "sifive_prci_clock_enable(), sifive_prci_clock_disable()
and sifive_clk_is_enabled()" to enable or disable the PRCI clock
Signed-off-by: Pragnesh Patel
Tested-by: Zong Li
---
drivers/clk/sifive/fu540-prci.c | 6 +++
drivers/clk/sifive/fu
nd disable ops
Zong Li (4):
clk: sifive: Extract prci core to common base
clk: sifive: Use common name for prci configuration
clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
clk: sifive: Fix the wrong bit field shift
arch/riscv/Kconfig.socs | 2 +-
d
it needs to get match data in probe
callback function, then use the data for initialization.
Signed-off-by: Zong Li
Reviewed-by: Pragnesh Patel
Acked-by: Palmer Dabbelt
---
drivers/clk/sifive/Makefile | 2 +
drivers/clk/sifive/fu540-prci.c | 579
From: Pragnesh Patel
Add new functions "sifive_prci_clock_enable(), sifive_prci_clock_disable()
and sifive_clk_is_enabled()" to enable or disable the PRCI clock
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 6 +++
drivers/clk/sifive/fu740-prci.c | 9
://www.sifive.com/boards/hifive-unmatched
This driver contains bug fixes and contributions from
Henry Styles
Erik Danie
Pragnesh Patel
Signed-off-by: Zong Li
Reviewed-by: Pragnesh Patel
Acked-by: Palmer Dabbelt
Cc: Henry Styles
Cc: Erik Danie
Cc: Pragnesh Patel
---
drivers/clk/sifive/Kconfig
The clk enable bit should be 31 instead of 24.
Signed-off-by: Zong Li
Reported-by: Pragnesh Patel
---
drivers/clk/sifive/sifive-prci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index 7e509dfb72d1
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Reviewed-by: Pragnesh Patel
---
arch/riscv/Kconfig.socs | 2 +-
drivers/clk/sifive/Kconfig | 6
changes in commit message.
- Using option -M and -C to create patches.
- Rebase code to kernel v5.10-rc3.
Pragnesh Patel (1):
clk: sifive: Add clock enable and disable ops
Zong Li (4):
clk: sifive: Extract prci core to common base
clk: sifive: Use common name for prci configuration
clk
it needs to get match data in probe
callback function, then use the data for initialization.
Signed-off-by: Zong Li
Reviewed-by: Pragnesh Patel
Acked-by: Palmer Dabbelt
---
drivers/clk/sifive/Makefile | 2 +-
drivers/clk/sifive/fu540-prci.c | 579
; [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Zong-Li/clk-add-driver-for-the-Si
Add YAML DT binding documentation for the SiFive FU740 PRCI. The
link of unmatched board as follow, the U740-C000 manual would be present
in the same page later.
https://www.sifive.com/boards/hifive-unmatched
Passes dt_binding_check.
Signed-off-by: Zong Li
---
.../bindings/clock/sifive
plements SoC-level clock tree controls and dividers.
> >
> > This driver contains bug fixes and contributions from
> > Henry Styles
> > Erik Danie
> > Pragnesh Patel
> >
> > Signed-off-by: Zong Li
> > Reviewed-by: Pragnesh Patel
> > Cc: Henr
meone needs to sort out issues in the future.
>
We have a product brief as follow in public now, I would add the link
of it in the next version patch. Thanks.
https://sifive.cdn.prismic.io/sifive/c05b8ddd-e043-45a6-8a29-2a137090236f_HiFive+Unmatched+Product+Brief+%28released%29.pdf
> >
On Sat, Nov 21, 2020 at 9:29 AM Palmer Dabbelt wrote:
>
> On Wed, 11 Nov 2020 02:06:08 PST (-0800), zong...@sifive.com wrote:
> > The clk enable bit should be 31 instead of 24.
> >
> > Signed-off-by: Zong Li
> > Reported-by: Pragnesh Patel
> > ---
>
On Sat, Nov 21, 2020 at 9:29 AM Palmer Dabbelt wrote:
>
> On Wed, 11 Nov 2020 02:06:06 PST (-0800), zong...@sifive.com wrote:
> > Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
> > patch is prepared for fu740 support.
> >
> > Signed
On Thu, Nov 12, 2020 at 2:02 PM Stephen Boyd wrote:
>
> Quoting Pragnesh Patel (2020-11-11 01:51:17)
> > >+#define RCI_GEMGXLPLLCFG1_CKE_SHIFT 24
> > >+#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 <<
> > >PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
> >
> > Same here, Other than this
> >
> > Reviewed-by:
to create patches.
- Rebase code to kernel v5.10-rc3.
Zong Li (4):
clk: sifive: Extract prci core to common base
clk: sifive: Use common name for prci configuration
clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
clk: sifive: Fix the wrong bit field shift
arch/riscv/Kconfig.socs
-by: Zong Li
Reviewed-by: Pragnesh Patel
Cc: Henry Styles
Cc: Erik Danie
Cc: Pragnesh Patel
---
drivers/clk/sifive/Kconfig| 4 +-
drivers/clk/sifive/Makefile | 1 +
drivers/clk/sifive/fu740-prci.c | 122 ++
drivers/clk/sifive
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Reviewed-by: Pragnesh Patel
---
arch/riscv/Kconfig.socs | 2 +-
drivers/clk/sifive/Kconfig | 6
it needs to get match data in probe
callback function, then use the data for initialization.
Signed-off-by: Zong Li
Reviewed-by: Pragnesh Patel
---
drivers/clk/sifive/Makefile | 2 +
drivers/clk/sifive/fu540-prci.c | 586 +-
drivers/clk/sifive/fu540
The clk enable bit should be 31 instead of 24.
Signed-off-by: Zong Li
Reported-by: Pragnesh Patel
---
drivers/clk/sifive/sifive-prci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index 802fc8fb9c09
On Wed, Nov 11, 2020 at 5:51 PM Pragnesh Patel
wrote:
>
> Hi Zong,
>
> >-Original Message-
> >From: Zong Li
> >Sent: 11 November 2020 15:05
> >To: Paul Walmsley ( Sifive) ; pal...@dabbelt.com;
> >sb...@kernel.org; sch...@linux-m68k.org; Pra
it needs to get match data in probe
callback function, then use the data for initialization.
Signed-off-by: Zong Li
---
drivers/clk/sifive/Makefile | 2 +
drivers/clk/sifive/fu540-prci.c | 586 +-
drivers/clk/sifive/fu540-prci.h | 21
definition for __prci_clock_array.
- Indicate the functional changes in commit message.
- Using option -M and -C to create patches.
- Rebase code to kernel v5.10-rc3.
Zong Li (3):
clk: sifive: Extract prci core to common base
clk: sifive: Use common name for prci configuration
clk: sifive: Add
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Reviewed-by: Pragnesh Patel
---
arch/riscv/Kconfig.socs | 2 +-
drivers/clk/sifive/Kconfig | 6
-by: Zong Li
Cc: Henry Styles
Cc: Erik Danie
Cc: Pragnesh Patel
---
drivers/clk/sifive/Kconfig| 4 +-
drivers/clk/sifive/Makefile | 1 +
drivers/clk/sifive/fu740-prci.c | 122 ++
drivers/clk/sifive/fu740-prci.h
On Wed, Nov 11, 2020 at 1:47 PM Pragnesh Patel
wrote:
>
> Hi Zong,
>
> >-Original Message-
> >From: linux-riscv On Behalf Of
> >Zong Li
> >Sent: 10 November 2020 12:58
> >To: Paul Walmsley ( Sifive) ; pal...@dabbelt.com;
> >sb...@kernel.org;
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
arch/riscv/Kconfig.socs | 2 +-
drivers/clk/sifive/Kconfig | 6 +++---
drivers/clk/sifive/Makefile
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.
This driver contains bug fixes and contributions from
Henry Styles and Erik Danie .
Signed-off-by: Zong Li
Cc
the functional changes in commit message.
- Using option -M and -C to create patches.
- Rebase code to kernel v5.10-rc3
Zong Li (3):
clk: sifive: Extract prci core to common base
clk: sifive: Use common name for prci configuration
clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
arch
it needs to get match data in probe
callback function, then use the data for initialization.
Signed-off-by: Zong Li
---
drivers/clk/sifive/Makefile | 2 +
drivers/clk/sifive/fu540-prci.c | 586 +-
drivers/clk/sifive/fu540-prci.h | 21
On Thu, Nov 5, 2020 at 5:19 PM Andreas Schwab wrote:
>
> On Nov 05 2020, Zong Li wrote:
>
> > I tried to add -M and -C option to find renames and copies, but it
> > doesn't detect anything here.
>
> -C40 finds a copy drivers/clk/sifive/{fu540-prci.c => sifive-prci.c
On Thu, Nov 5, 2020 at 10:45 AM Stephen Boyd wrote:
>
> Quoting Zong Li (2020-10-16 02:18:23)
> > Extract common core of prci driver to an independent file, it could
> > allow other chips to reuse it. Separate SoCs-dependent code 'fu540'
> > from prci core, then we can
On Thu, Nov 5, 2020 at 10:50 AM Stephen Boyd wrote:
>
> Quoting Zong Li (2020-10-16 02:18:26)
> > Refactor code by using DEFINE_PRCI_CLOCK to define each clock
> > and reduce duplicate code.
>
> What is duplicate?
Sorry for unclear description, actually, I want t
On Thu, Nov 5, 2020 at 10:46 AM Stephen Boyd wrote:
>
> Quoting Zong Li (2020-10-16 02:18:24)
> > Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
> > patch is prepared for fu740 support.
> >
> > Signed-off-by: Zong Li
> > ---
>
On Fri, Oct 16, 2020 at 10:56 PM Zong Li wrote:
>
> On Fri, Oct 16, 2020 at 10:17 PM Sean Anderson wrote:
> >
> > On 10/16/20 5:18 AM, Zong Li wrote:
> > > Add a driver for the SiFive FU740 PRCI IP block, which handles more
> > > clocks than FU540. Thes
t kern
> >el/stop_machine.c:491
> > #9 0xffe0002343be in smpboot_thread_fn (data=0x0) at kernel/smpboot.
> >c:165
> > #10 0xffe00022f894 in kthread (_create=0xffe01af13040) at kern
> >el/kthread.c:292
> > #11 0xffe000201fac in handle_exception
The following commit has been merged into the smp/urgent branch of tip:
Commit-ID: 4230e2deaa484b385aa01d598b2aea8e7f2660a6
Gitweb:
https://git.kernel.org/tip/4230e2deaa484b385aa01d598b2aea8e7f2660a6
Author:Zong Li
AuthorDate:Wed, 21 Oct 2020 15:38:39 +08:00
Committer
On Sat, Oct 24, 2020 at 3:29 AM Colin Ian King wrote:
>
> On 21/10/2020 08:38, Zong Li wrote:
> > Like the commit cb9d7fd51d9f ("watchdog: Mark watchdog touch functions
> > as notrace"), some architectures assume that the stopped CPUs don't make
> > function
on RISC-V.
The following patches added calls to these two functions, fix it by
adding the notrace annotations.
Fixes: 4ecf0a43e729 ("processor: get rid of cpu_relax_yield")
Fixes: 366237e7b083 ("stop_machine: Provide RCU quiescent state in
multi_cpu_stop()")
Signed-off-by: Z
On Wed, Oct 21, 2020 at 4:41 AM Steven Rostedt wrote:
>
> On Tue, 20 Oct 2020 19:18:01 +0800
> Guo Ren wrote:
>
> > > What platform are you testing ? We are seeing a crash while enabling
> > > any of the tracers multiple times
> > > on Qemu/HiFive Unleashed.
> > I use qemu for testing. I've
On Fri, Oct 16, 2020 at 10:17 PM Sean Anderson wrote:
>
> On 10/16/20 5:18 AM, Zong Li wrote:
> > Add a driver for the SiFive FU740 PRCI IP block, which handles more
> > clocks than FU540. These patches also refactor the original
> > implementation by spliting the
Refactor code by using DEFINE_PRCI_CLOCK to define each clock
and reduce duplicate code.
Signed-off-by: Zong Li
---
drivers/clk/sifive/fu540-prci.c | 38 ++--
drivers/clk/sifive/fu540-prci.h | 2 +-
drivers/clk/sifive/fu740-prci.c | 74
drivers
Extract common core of prci driver to an independent file, it could
allow other chips to reuse it. Separate SoCs-dependent code 'fu540'
from prci core, then we can easily add 'fu740' later.
Signed-off-by: Zong Li
---
drivers/clk/sifive/Makefile | 2 +
drivers/clk/sifive/fu540-prci.c
Add a driver for the SiFive FU740 PRCI IP block, which handles more
clocks than FU540. These patches also refactor the original
implementation by spliting the dependent-code of fu540 and fu740
respectively.
Zong Li (4):
clk: sifive: Extract prci core to common base
clk: sifive: Use common
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.
Signed-off-by: Zong Li
---
arch/riscv/Kconfig.socs | 2 +-
drivers/clk/sifive/Kconfig | 6 +++---
drivers/clk/sifive/Makefile | 2 +-
3 files changed, 5 insertions(+), 5 deletions
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.
This driver contains bug fixes and contributions from
Henry Styles and Erik Danie .
Signed-off-by: Zong Li
Cc
Hi Atish,
I can take out some time to take a look at it together, if anyone here
fixes it or has ideas, please share the information, thanks.
On Sun, Oct 4, 2020 at 1:33 AM Atish Patra wrote:
>
> Hi Alan and Zong,
> I initially suspected ftrace is broken between v5.6 & v5.7 as Kolin pointed
>
AT_VECTOR_SIZE_ARCH should be defined with the maximum number of
NEW_AUX_ENT entries that ARCH_DLINFO can contain, but it wasn't defined
for RISC-V at all even though ARCH_DLINFO will contain one NEW_AUX_ENT
for the VDSO address.
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
---
arch
Set cacheinfo.{size,sets,line_size} for each cache node, then we can
get these information from userland through auxiliary vector.
Signed-off-by: Zong Li
---
arch/riscv/kernel/cacheinfo.c | 66 +++
1 file changed, 51 insertions(+), 15 deletions(-)
diff --git
properties.
Zong Li (3):
riscv: Set more data to cacheinfo
riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO
riscv: Add cache information in AUX vector
arch/riscv/include/asm/cacheinfo.h | 5 ++
arch/riscv/include/asm/elf.h | 13
arch/riscv/include/uapi/asm/auxvec.h | 24
LEVEL2_CACHE_ASSOC 32
LEVEL2_CACHE_LINESIZE 64
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
---
arch/riscv/include/asm/cacheinfo.h | 5 +
arch/riscv/include/asm/elf.h | 13 +++
arch/riscv/include/uapi/asm/auxvec.h | 23 +++-
arch
On Mon, Aug 31, 2020 at 3:00 PM Pekka Enberg wrote:
>
> Hi,
>
> On Mon, Aug 31, 2020 at 9:15 AM Zong Li wrote:
> > If the sets is one, it means that the cache is fully associative, then
> > we don't need to fill the ways number, just keep way number as zero,
> > so
On Sun, Aug 30, 2020 at 4:01 PM Pekka Enberg wrote:
>
> On Fri, Aug 28, 2020 at 10:09 AM Zong Li wrote:
> > +uintptr_t get_cache_geometry(u32 level, enum cache_type type)
> > +{
> > + struct cacheinfo *this_leaf = get_cacheinfo(level, type);
> > +
On Sun, Aug 30, 2020 at 3:54 PM Pekka Enberg wrote:
>
> Hi,
>
> On Fri, Aug 28, 2020 at 10:09 AM Zong Li wrote:
> >
> > Set cacheinfo.{size,sets,line_size} for each cache node, then we can
> > get these information from userland through auxiliary vector.
LEVEL2_CACHE_ASSOC 32
LEVEL2_CACHE_LINESIZE 64
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
---
arch/riscv/include/asm/cacheinfo.h | 5 +
arch/riscv/include/asm/elf.h | 13 +++
arch/riscv/include/uapi/asm/auxvec.h | 23 +++-
arch
AT_VECTOR_SIZE_ARCH should be defined with the maximum number of
NEW_AUX_ENT entries that ARCH_DLINFO can contain, but it wasn't defined
for RISC-V at all even though ARCH_DLINFO will contain one NEW_AUX_ENT
for the VDSO address.
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
---
arch
Set cacheinfo.{size,sets,line_size} for each cache node, then we can
get these information from userland through auxiliary vector.
Signed-off-by: Zong Li
---
arch/riscv/kernel/cacheinfo.c | 59 ++-
1 file changed, 44 insertions(+), 15 deletions(-)
diff --git
32
LEVEL2_CACHE_LINESIZE 64
Changed in v3:
- Fix sparse warning: Use NULL instead of integer 0
Changed in v2:
- Add error checking for parsing cache properties.
Zong Li (3):
riscv: Set more data to cacheinfo
riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO
riscv: Add
AT_VECTOR_SIZE_ARCH should be defined with the maximum number of
NEW_AUX_ENT entries that ARCH_DLINFO can contain, but it wasn't defined
for RISC-V at all even though ARCH_DLINFO will contain one NEW_AUX_ENT
for the VDSO address.
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
---
arch
8
> > LEVEL1_ICACHE_ASSOC8
> > LEVEL1_ICACHE_LINESIZE 64
> > LEVEL1_DCACHE_SIZE 32768
> > LEVEL1_DCACHE_ASSOC8
> > LEVEL1_DCACHE_LINESIZE 64
> > LEVEL2_CACHE_SIZE 2097152
> &
32
LEVEL2_CACHE_LINESIZE 64
Changed in v2:
- Add error checking for parsing cache properties.
Zong Li (3):
riscv: Set more data to cacheinfo
riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO
riscv: Add cache information in AUX vector
arch/riscv/include/asm/cacheinfo.h
Set cacheinfo.{size,sets,line_size} for each cache node, then we can
get these information from userland through auxiliary vector.
Signed-off-by: Zong Li
---
arch/riscv/kernel/cacheinfo.c | 59 ++-
1 file changed, 44 insertions(+), 15 deletions(-)
diff --git
LEVEL2_CACHE_ASSOC 32
LEVEL2_CACHE_LINESIZE 64
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
---
arch/riscv/include/asm/cacheinfo.h | 5 +
arch/riscv/include/asm/elf.h | 13 +++
arch/riscv/include/uapi/asm/auxvec.h | 23 +++-
arch
On Fri, Jul 3, 2020 at 4:57 PM Zong Li wrote:
>
> There are no standard CSR registers to provide cache information, the
> way for RISC-V is to get this information from DT. Currently, AT_L1I_X,
> AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall
> could
/pageattr.c:97:1: warning: 'static' is not at beginning of
declaration [-Wold-style-declaration]
Changed in v2:
- Modify the patch description
Zong Li (2):
riscv: Fix build warning for mm/init
riscv: Fix build warning for mm/pageattr
arch/riscv/mm/init.c | 2 +-
arch/riscv/mm/pageattr.c
of declaration [-Wold-style-declaration]
Signed-off-by: Zong Li
Reviewed-by: Pekka Enberg
---
arch/riscv/mm/pageattr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/mm/pageattr.c b/arch/riscv/mm/pageattr.c
index 289a9a5ea5b5..19fecb362d81 100644
--- a/arch/riscv/mm
Add static keyword for resource_init, this function is only used in this
object file.
The warning message as follow (with W=1 build):
arch/riscv/mm/init.c:520:13:
warning: no previous prototype for 'resource_init' [-Wmissing-prototypes]
Signed-off-by: Zong Li
---
arch/riscv/mm/init.c | 2
On Thu, Jul 16, 2020 at 3:24 PM Andreas Schwab wrote:
>
> On Jul 16 2020, Zong Li wrote:
>
> > Add hearder for missing prototype. Also, static keyword should be at
>
> s/hearder/header/
>
> Andreas.
>
> --
> Andreas Schwab, sch...@linux-m68k.org
> GPG Key
/pageattr.c:97:1: warning: 'static' is not at beginning of
declaration [-Wold-style-declaration]
Zong Li (2):
riscv: Fix build warning for mm/init
riscv: fix build warning of mm/pageattr
arch/riscv/mm/init.c | 2 +-
arch/riscv/mm/pageattr.c | 3 ++-
2 files changed, 3 insertions(+), 2
Add static keyword for resource_init, this function is only used in this
object file.
Signed-off-by: Zong Li
---
arch/riscv/mm/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 92002952c621..66f5952f39c0 100644
Add hearder for missing prototype. Also, static keyword should be at
beginning of declaration.
Signed-off-by: Zong Li
---
arch/riscv/mm/pageattr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/mm/pageattr.c b/arch/riscv/mm/pageattr.c
index 289a9a5ea5b5
gt; $ devmem 0x8020
> > 0x106F
> >
> > - CONFIG_STRICT_DEVMEM is not set
> > $ devmem 0x1001
> > devmem: mmap: Operation not permitted
> > $ devmem 0x8020
> > devmem: mmap: Operation not permitted
> >
&
ure this doesn't happen -- it's just enough
> to
> make sure it doesn't happen very quickily. That's the same boat we're already
> in, though, so it's not like it's worse.
>
> > Signed-off-by: Alexandre Ghiti
> > Reviewed-by: Zong Li
> > ---
> > arch/riscv/boot
On Tue, Jun 23, 2020 at 4:02 PM Zong Li wrote:
>
> AT_VECTOR_SIZE_ARCH should be defined with the maximum number of
> NEW_AUX_ENT entries that ARCH_DLINFO can contain, but it wasn't defined
> for RISC-V at all even though ARCH_DLINFO will contain one NEW_AUX_ENT
> for the VDSO addr
acki.ch/
> > [2]
> > https://lore.kernel.org/linux-csky/20200403044150.20562-9-guo...@kernel.org/
> >
>
> This looks good to me. Thanks for updating !
>
> Acked-by: Masami Hiramatsu
>
> Thank you,
>
It works to me. Thanks!
Tested-by: Zong Li
>
> > Signed
which contains kernel stack pointer.
> + * @n: stack entry number.
> + *
> + * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
> + * is specified by @regs. If the @n th entry is NOT in the kernel stack,
> + * this returns 0.
> + */
> +unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
> +{
> + unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
> +
> + addr += n;
> + if (regs_within_kernel_stack(regs, (unsigned long)addr))
> + return *addr;
> + else
> + return 0;
> +}
> +
> void ptrace_disable(struct task_struct *child)
> {
> clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
> --
> 2.7.4
>
Looks good to me.
Reviewed-by: Zong Li
On Fri, Jul 3, 2020 at 5:51 PM Joe Perches wrote:
>
> On Fri, 2020-07-03 at 11:41 +0200, Miguel Ojeda wrote:
> > On Fri, Jul 3, 2020 at 10:51 AM Joe Perches wrote:
> > > I'd prefer to delete Lindent instead.
> >
> > +1, especially since there is `clang-format` now.
Agree, it is often used.
>
>
On Fri, Jul 3, 2020 at 4:51 PM Joe Perches wrote:
>
> On Fri, 2020-07-03 at 16:08 +0800, Zong Li wrote:
> > As the patch 'bdc48fa11e46 ("checkpatch/coding-style: deprecate
> > 80-column warning")', increase the default limit to 100 characters,
> > we also incre
Set cacheinfo.{size,sets,line_size} for each cache node, then we can
get these information from userland through auxiliary vector.
Signed-off-by: Zong Li
---
arch/riscv/kernel/cacheinfo.c | 59 ++-
1 file changed, 44 insertions(+), 15 deletions(-)
diff --git
AT_VECTOR_SIZE_ARCH should be defined with the maximum number of
NEW_AUX_ENT entries that ARCH_DLINFO can contain, but it wasn't defined
for RISC-V at all even though ARCH_DLINFO will contain one NEW_AUX_ENT
for the VDSO address.
Signed-off-by: Zong Li
---
arch/riscv/include/uapi/asm/auxvec.h
32
LEVEL2_CACHE_LINESIZE 64
Zong Li (3):
riscv: Set more data to cacheinfo
riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO
riscv: Add cache information in AUX vector
arch/riscv/include/asm/cacheinfo.h | 14 +
arch/riscv/include/asm/elf.h | 13
arch
LEVEL2_CACHE_ASSOC 32
LEVEL2_CACHE_LINESIZE 64
Signed-off-by: Zong Li
---
arch/riscv/include/asm/cacheinfo.h | 14
arch/riscv/include/asm/elf.h | 13 +++
arch/riscv/include/uapi/asm/auxvec.h | 23 ++-
arch/riscv/kernel
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