[PATCH 2/5] RISC-V: Select GENERIC_UCMPDI2 on RV32I

On 32-bit, it need to use __ucmpdi2, otherwise, it can't find the __ucmpdi2 symbol. Signed-off-by: Zong Li --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6debcc4afc72..3e683be9b7a8 100644 --- a/arch/riscv/Kconfig +++ b

[PATCH 2/5] RISC-V: Select GENERIC_UCMPDI2 on RV32I

On 32-bit, it need to use __ucmpdi2, otherwise, it can't find the __ucmpdi2 symbol. Signed-off-by: Zong Li --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6debcc4afc72..3e683be9b7a8 100644 --- a/arch/riscv/Kconfig +++ b

[PATCH 3/5] RISC-V: Add definiion of extract symbol's index and type for 32-bit

Use generic marco to get the index and type of symbol. Signed-off-by: Zong Li --- arch/riscv/include/uapi/asm/elf.h | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index 5cae4c30cd8e

[PATCH 5/5] RISC-V: Use fixed width integer types for 32-bit compatible

Use fixed width integer types for print format on 32/64 bit to fix warning about format compatible. Like inttypes.h, but more simpler for RISC-V usage. Signed-off-by: Zong Li --- arch/riscv/include/asm/format.h | 20 arch/riscv/kernel/module.c | 13 +++-- 2

[PATCH 3/5] RISC-V: Add definiion of extract symbol's index and type for 32-bit

Use generic marco to get the index and type of symbol. Signed-off-by: Zong Li --- arch/riscv/include/uapi/asm/elf.h | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index 5cae4c30cd8e

[PATCH 5/5] RISC-V: Use fixed width integer types for 32-bit compatible

Use fixed width integer types for print format on 32/64 bit to fix warning about format compatible. Like inttypes.h, but more simpler for RISC-V usage. Signed-off-by: Zong Li --- arch/riscv/include/asm/format.h | 20 arch/riscv/kernel/module.c | 13 +++-- 2

[PATCH 4/5] RISC-V: Change variable type for 32-bit compatible

Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 29d265d0cf45..c88d2ee918a5 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv

[PATCH 4/5] RISC-V: Change variable type for 32-bit compatible

Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 29d265d0cf45..c88d2ee918a5 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv

[PATCH 1/5] RISC-V: Add conditional macro for zone of DMA32

The DMA32 is for 64-bit usage. Signed-off-by: Zong Li --- arch/riscv/mm/init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index c77df8142be2..91a5852e28fd 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -28,8 +28,11

[PATCH] RISC-V: Add the directive for alignment of stvec's value

The stvec's value must be 4 byte alignment by specification definition. This directive avoids to stvec be set the non-alignment value by the following code in head.S /* Point stvec to virtual address of intruction after satp write */ la a0, 1f add a0, a0, a1 csrw stvec, a0 Signed-off-by: Zong

[PATCH 1/5] RISC-V: Add conditional macro for zone of DMA32

The DMA32 is for 64-bit usage. Signed-off-by: Zong Li --- arch/riscv/mm/init.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index c77df8142be2..91a5852e28fd 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -28,8 +28,11

[PATCH] RISC-V: Add the directive for alignment of stvec's value

The stvec's value must be 4 byte alignment by specification definition. This directive avoids to stvec be set the non-alignment value by the following code in head.S /* Point stvec to virtual address of intruction after satp write */ la a0, 1f add a0, a0, a1 csrw stvec, a0 Signed-off-by: Zong

[PATCH] RISC-V: Add conditional marco for boot_sec_cpu

Fix link error when disable support SMP. It causes the undefined reference to `smp_callin'. Signed-off-by: Zong Li --- arch/riscv/kernel/head.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3b6293f10e3e..396ec7b349ce 100644

[PATCH 0/5] Building for 32-bit RISC-V kernel

These patches are for building 32-bit RISC-V kernel. - Fix the compile errors and warnings on RV32I. - Fix some incompatible problem on RV32I. - Add format.h for compatible of print format. Zong Li (5): RISC-V: Add conditional macro for zone of DMA32 RISC-V: Select GENERIC_UCMPDI2

[PATCH] RISC-V: Add conditional marco for boot_sec_cpu

Fix link error when disable support SMP. It causes the undefined reference to `smp_callin'. Signed-off-by: Zong Li --- arch/riscv/kernel/head.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3b6293f10e3e..396ec7b349ce 100644

[PATCH 0/5] Building for 32-bit RISC-V kernel

These patches are for building 32-bit RISC-V kernel. - Fix the compile errors and warnings on RV32I. - Fix some incompatible problem on RV32I. - Add format.h for compatible of print format. Zong Li (5): RISC-V: Add conditional macro for zone of DMA32 RISC-V: Select GENERIC_UCMPDI2

[PATCH] RISC-V: Add conditional macro for boot_sec_cpu

Fix link error when disable support SMP. It causes the undefined reference to `smp_callin'. Signed-off-by: Zong Li --- arch/riscv/kernel/head.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3b6293f10e3e..396ec7b349ce 100644

[PATCH] RISC-V: Add conditional macro for boot_sec_cpu

Fix link error when disable support SMP. It causes the undefined reference to `smp_callin'. Signed-off-by: Zong Li --- arch/riscv/kernel/head.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3b6293f10e3e..396ec7b349ce 100644

Re: [PATCH v2 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

eys 19606 0 - Live 0xffd003717000 >>> test_static_key_base 7374 1 test_static_keys, Live 0xffd0036dc000 >>> test_printf 7804 0 [permanent], Live 0xffd00369c000 >>> test_module 1557 0 - Live 0xffd003646000 >>> test_kmod 49100 0 - Live 0xffd00

Re: [PATCH v2 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

test_static_key_base 7374 1 test_static_keys, Live 0xffd0036dc000 >>> test_printf 7804 0 [permanent], Live 0xffd00369c000 >>> test_module 1557 0 - Live 0xffd003646000 >>> test_kmod 49100 0 - Live 0xffd0035f2000 >>> test_bpf 1599301 0 - Live 0x

Re: [PATCH v2 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

>> test_kmod 49100 0 - Live 0xffd0035f2000 >> test_bpf 1599301 0 - Live 0xffd00300 >> test_bitmap 4403 0 - Live 0xffd002dd8000 >> reed_solomon 38866 1 ramoops, Live 0xffd002d86000 >> raid6_pq 161872 1 btrfs, Live 0xffd002b9e000 >> netdevsim 654

Re: [PATCH v2 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

0 - Live 0xffd0035f2000 >> test_bpf 1599301 0 - Live 0xffd00300 >> test_bitmap 4403 0 - Live 0xffd002dd8000 >> reed_solomon 38866 1 ramoops, Live 0xffd002d86000 >> raid6_pq 161872 1 btrfs, Live 0xffd002b9e000 >> netdevsim 65401 0 - Live 0xffd0

Re: [PATCH v2 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

2018-03-15 16:50 GMT+08:00 Zong Li <z...@andestech.com>: > These patches resolve the some issues of loadable module. > - symbol out of ranges > - unknown relocation types > > The reference of external variable and function symbols > cannot exceed 32-bit offset

Re: [PATCH v2 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

2018-03-15 16:50 GMT+08:00 Zong Li : > These patches resolve the some issues of loadable module. > - symbol out of ranges > - unknown relocation types > > The reference of external variable and function symbols > cannot exceed 32-bit offset ranges in kernel module. > The

Re: [PATCH 02/11] RISC-V: Add section of GOT.PLT for kernel module

tree, please drop us a note to > help improve the system] > > url: > https://github.com/0day-ci/linux/commits/Zong-Li/RISC-V-Resolve-the-issue-of-loadable-module-on-64-bit/20180314-203750 > config: riscv-defconfig (attached as .config) > compiler: riscv64-linux-gcc (GC

Re: [PATCH 02/11] RISC-V: Add section of GOT.PLT for kernel module

us a note to > help improve the system] > > url: > https://github.com/0day-ci/linux/commits/Zong-Li/RISC-V-Resolve-the-issue-of-loadable-module-on-64-bit/20180314-203750 > config: riscv-defconfig (attached as .config) > compiler: riscv64-linux-gcc (GCC) 7.2

[PATCH v2 01/11] RISC-V: Add sections of PLT and GOT for kernel module

. The GOT entry is just the data symbol address. Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/Kconfig | 5 ++ arch/riscv/Makefile | 5 ++ arch/riscv/include/asm/module.h | 103 ++ arch/riscv/kernel/Makefile

[PATCH v2 01/11] RISC-V: Add sections of PLT and GOT for kernel module

. The GOT entry is just the data symbol address. Signed-off-by: Zong Li --- arch/riscv/Kconfig | 5 ++ arch/riscv/Makefile | 5 ++ arch/riscv/include/asm/module.h | 103 ++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel

[PATCH v2 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

65401 0 - Live 0xffd00291 Signed-off-by: Zong Li <z...@andestech.com> --- Change in v2: - Add compile option 'mno-relax' for build kernel module - Just fail on ALIGN type, this is unexpected type with mno-relax. Zong Li (11): RISC-V: Add sections of PLT and GOT for kernel module

[PATCH v2 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

65401 0 - Live 0xffd00291 Signed-off-by: Zong Li --- Change in v2: - Add compile option 'mno-relax' for build kernel module - Just fail on ALIGN type, this is unexpected type with mno-relax. Zong Li (11): RISC-V: Add sections of PLT and GOT for kernel module RISC-V: Add section

[PATCH v2 05/11] RISC-V: Support HI20/LO12_I/LO12_S relocation type in kernel module

HI20 and LO12_I/LO12_S relocate the absolute address, the range of offset must in 32-bit. Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 42 ++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/kernel/module.c

[PATCH v2 05/11] RISC-V: Support HI20/LO12_I/LO12_S relocation type in kernel module

HI20 and LO12_I/LO12_S relocate the absolute address, the range of offset must in 32-bit. Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 42 ++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c

[PATCH v2 03/11] RISC-V: Support GOT_HI20/CALL_PLT relocation type in kernel module

*ABS* Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 62 ++ 1 file changed, 52 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index e0f05034fc21..be717b

[PATCH v2 03/11] RISC-V: Support GOT_HI20/CALL_PLT relocation type in kernel module

*ABS* Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 62 ++ 1 file changed, 52 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index e0f05034fc21..be717bd7cea7 100644 --- a/arch/riscv

[PATCH v2 07/11] RISC-V: Support ALIGN relocation type in kernel module

Just fail on align type. Kernel modules loader didn't do relax like linker, it is difficult to remove or migrate the code, but the remnant nop instructions harm the performaace of module. We expect the building module with the no-relax option. Signed-off-by: Zong Li <z...@andestech.com> ---

[PATCH v2 07/11] RISC-V: Support ALIGN relocation type in kernel module

Just fail on align type. Kernel modules loader didn't do relax like linker, it is difficult to remove or migrate the code, but the remnant nop instructions harm the performaace of module. We expect the building module with the no-relax option. Signed-off-by: Zong Li --- arch/riscv/kernel

[PATCH v2 08/11] RISC-V: Support ADD32 relocation type in kernel module

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 957933e669b1..73ea36c73d3b 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/mo

[PATCH v2 08/11] RISC-V: Support ADD32 relocation type in kernel module

Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 957933e669b1..73ea36c73d3b 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -249,6 +249,13

[PATCH v2 11/11] RISC-V: Add definition of relocation types

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/include/uapi/asm/elf.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index a510edfa8226..5cae4c30cd8e 100644 --- a/arch/riscv/include/uapi/asm/elf.h

[PATCH v2 09/11] RISC-V: Support SUB32 relocation type in kernel module

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 73ea36c73d3b..5dddba301d0a 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/mo

[PATCH v2 11/11] RISC-V: Add definition of relocation types

Signed-off-by: Zong Li --- arch/riscv/include/uapi/asm/elf.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index a510edfa8226..5cae4c30cd8e 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include

[PATCH v2 09/11] RISC-V: Support SUB32 relocation type in kernel module

Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 73ea36c73d3b..5dddba301d0a 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -256,6 +256,13

[PATCH v2 10/11] RISC-V: Enable module support in defconfig

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 92ff23586c11..07326466871b 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/c

[PATCH v2 10/11] RISC-V: Enable module support in defconfig

Signed-off-by: Zong Li --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 92ff23586c11..07326466871b 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -74,3 +74,5

[PATCH v2 06/11] RISC-V: Support RVC_BRANCH/JUMP relocation type in kernel modulewq

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index f1bd6b1a4520..7ab6a9b72384 100644 --- a/arch/riscv/kernel/mo

[PATCH v2 06/11] RISC-V: Support RVC_BRANCH/JUMP relocation type in kernel modulewq

Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index f1bd6b1a4520..7ab6a9b72384 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel

[PATCH v2 04/11] RISC-V: Support CALL relocation type in kernel module

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index be717bd7cea7..3f2730840c25 100644 --- a/arch/riscv/kernel/module.c +++ b/arch

[PATCH v2 04/11] RISC-V: Support CALL relocation type in kernel module

Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index be717bd7cea7..3f2730840c25 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c

[PATCH v2 02/11] RISC-V: Add section of GOT.PLT for kernel module

Separate the function symbol address from .plt to .got.plt section. The original plt entry has trampoline code with symbol address, there is a 32-bit padding bwtween jar instruction and symbol address. Extract the symbol address to .got.plt to reduce the module size. Signed-off-by: Zong Li &l

[PATCH v2 02/11] RISC-V: Add section of GOT.PLT for kernel module

Separate the function symbol address from .plt to .got.plt section. The original plt entry has trampoline code with symbol address, there is a 32-bit padding bwtween jar instruction and symbol address. Extract the symbol address to .got.plt to reduce the module size. Signed-off-by: Zong Li

Re: [PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

2018-03-14 19:56 GMT+08:00 Shea Levy <s...@shealevy.com>: > Zong Li <zong...@gmail.com> writes: > >> 2018-03-14 11:07 GMT+08:00 Palmer Dabbelt <pal...@sifive.com>: >>> On Tue, 13 Mar 2018 18:34:19 PDT (-0700), zong...@gmail.com wrote: >>&

Re: [PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

2018-03-14 19:56 GMT+08:00 Shea Levy : > Zong Li writes: > >> 2018-03-14 11:07 GMT+08:00 Palmer Dabbelt : >>> On Tue, 13 Mar 2018 18:34:19 PDT (-0700), zong...@gmail.com wrote: >>>> >>>> 2018-03-14 5:30 GMT+08:00 Shea Levy : >>>

Re: [PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

sections depend on the relocation types: >>>>> - R_RISCV_GOT_HI20 >>>>> - R_RISCV_CALL_PLT >>>>> >>>>> These patches also support more relocation types >>>>> - R_RISCV_CALL >>>>> - R_RISCV_HI20

Re: [PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

- R_RISCV_GOT_HI20 >>>>> - R_RISCV_CALL_PLT >>>>> >>>>> These patches also support more relocation types >>>>> - R_RISCV_CALL >>>>> - R_RISCV_HI20 >>>>> - R_RISCV_LO12_I >>>>> - R_RISCV_LO12_S &g

Re: [PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

the relocation types: >>> - R_RISCV_GOT_HI20 >>> - R_RISCV_CALL_PLT >>> >>> These patches also support more relocation types >>> - R_RISCV_CALL >>> - R_RISCV_HI20 >>> - R_RISCV_LO12_I >>> - R_RISCV_LO12_S >>> - R_RISCV_RVC_BR

Re: [PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

0 >>> - R_RISCV_CALL_PLT >>> >>> These patches also support more relocation types >>> - R_RISCV_CALL >>> - R_RISCV_HI20 >>> - R_RISCV_LO12_I >>> - R_RISCV_LO12_S >>> - R_RISCV_RVC_BRANCH >>> - R_RISCV_RVC_JUMP >>>

Re: [PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

2018-03-13 16:35 GMT+08:00 Zong Li <z...@andestech.com>: > > These patches resolve the some issues of loadable module. > - symbol out of ranges > - unknown relocation types > > The reference of external variable and function symbols > cannot exceed 32-bit off

Re: [PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

2018-03-13 16:35 GMT+08:00 Zong Li : > > These patches resolve the some issues of loadable module. > - symbol out of ranges > - unknown relocation types > > The reference of external variable and function symbols > cannot exceed 32-bit offset ranges in kernel module. >

[PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

relocation types - R_RISCV_CALL - R_RISCV_HI20 - R_RISCV_LO12_I - R_RISCV_LO12_S - R_RISCV_RVC_BRANCH - R_RISCV_RVC_JUMP - R_RISCV_ALIGN - R_RISCV_ADD32 - R_RISCV_SUB32 Zong Li (11): RISC-V: Add sections of PLT and GOT for kernel module RISC-V: Add section of GOT.PLT for kernel module RISC-V

[PATCH 00/11] RISC-V: Resolve the issue of loadable module on 64-bit

relocation types - R_RISCV_CALL - R_RISCV_HI20 - R_RISCV_LO12_I - R_RISCV_LO12_S - R_RISCV_RVC_BRANCH - R_RISCV_RVC_JUMP - R_RISCV_ALIGN - R_RISCV_ADD32 - R_RISCV_SUB32 Zong Li (11): RISC-V: Add sections of PLT and GOT for kernel module RISC-V: Add section of GOT.PLT for kernel module RISC-V

[PATCH 04/11] RISC-V: Support CALL relocation type in kernel module

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 242d3a14c210..7e85e5840b4d 100644 --- a/arch/riscv/kernel/module.c +++ b/arch

[PATCH 04/11] RISC-V: Support CALL relocation type in kernel module

Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 242d3a14c210..7e85e5840b4d 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c

[PATCH 02/11] RISC-V: Add section of GOT.PLT for kernel module

Separate the function symbol address from .plt to .got.plt section. The original plt entry has trampoline code with symbol address, there is a 32-bit padding bwtween jar instruction and symbol address. Extract the symbol address to .got.plt to reduce the module size. Signed-off-by: Zong Li &l

[PATCH 02/11] RISC-V: Add section of GOT.PLT for kernel module

Separate the function symbol address from .plt to .got.plt section. The original plt entry has trampoline code with symbol address, there is a 32-bit padding bwtween jar instruction and symbol address. Extract the symbol address to .got.plt to reduce the module size. Signed-off-by: Zong Li

[PATCH 03/11] RISC-V: Support GOT_HI20/CALL_PLT relocation type in kernel module

*ABS* Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 61 ++ 1 file changed, 51 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index e0f05034fc21..242d3a

[PATCH 06/11] RISC-V: Support RVC_BRANCH/JUMP relocation type in kernel modulewq

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 654fe7dcd38d..e23c051dfc62 100644 --- a/arch/riscv/kernel/mo

[PATCH 03/11] RISC-V: Support GOT_HI20/CALL_PLT relocation type in kernel module

*ABS* Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 61 ++ 1 file changed, 51 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index e0f05034fc21..242d3a14c210 100644 --- a/arch/riscv

[PATCH 06/11] RISC-V: Support RVC_BRANCH/JUMP relocation type in kernel modulewq

Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 654fe7dcd38d..e23c051dfc62 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel

[PATCH 07/11] RISC-V: Support ALIGN relocation type in kernel module

Just ignore align type. The nop instructions cannot be removed in kernel module. Kernel modules is not doing relax. Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/

[PATCH 05/11] RISC-V: Support HI20/LO12_I/LO12_S relocation type in kernel module

HI20 and LO12_I/LO12_S relocate the absolute address, the range of offset must in 32-bit. Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 42 ++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/kernel/module.c

[PATCH 07/11] RISC-V: Support ALIGN relocation type in kernel module

Just ignore align type. The nop instructions cannot be removed in kernel module. Kernel modules is not doing relax. Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index

[PATCH 05/11] RISC-V: Support HI20/LO12_I/LO12_S relocation type in kernel module

HI20 and LO12_I/LO12_S relocate the absolute address, the range of offset must in 32-bit. Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 42 ++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c

[PATCH 10/11] RISC-V: Enable module support in defconfig

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 92ff23586c11..07326466871b 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/c

[PATCH 10/11] RISC-V: Enable module support in defconfig

Signed-off-by: Zong Li --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 92ff23586c11..07326466871b 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -74,3 +74,5

[PATCH 09/11] RISC-V: Support SUB32 relocation type in kernel module

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 2d14dff22861..4228270efe93 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/mo

[PATCH 09/11] RISC-V: Support SUB32 relocation type in kernel module

Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 2d14dff22861..4228270efe93 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -253,6 +253,13

[PATCH 08/11] RISC-V: Support ADD32 relocation type in kernel module

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/module.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 351bf2a518ee..2d14dff22861 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/mo

[PATCH 08/11] RISC-V: Support ADD32 relocation type in kernel module

Signed-off-by: Zong Li --- arch/riscv/kernel/module.c | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 351bf2a518ee..2d14dff22861 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -246,6 +246,13

[PATCH 01/11] RISC-V: Add sections of PLT and GOT for kernel module

. The GOT entry is just the data symbol address. Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/Kconfig | 5 ++ arch/riscv/Makefile | 3 + arch/riscv/include/asm/module.h | 102 ++ arch/riscv/kernel/Makefile

[PATCH 01/11] RISC-V: Add sections of PLT and GOT for kernel module

. The GOT entry is just the data symbol address. Signed-off-by: Zong Li --- arch/riscv/Kconfig | 5 ++ arch/riscv/Makefile | 3 + arch/riscv/include/asm/module.h | 102 ++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel

[PATCH 11/11] RISC-V: Add definition of relocation types

Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/include/uapi/asm/elf.h | 24 1 file changed, 24 insertions(+) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index a510edfa8226..5111c7c35e8b 100644 --- a/arch/riscv/i

[PATCH 11/11] RISC-V: Add definition of relocation types

Signed-off-by: Zong Li --- arch/riscv/include/uapi/asm/elf.h | 24 1 file changed, 24 insertions(+) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index a510edfa8226..5111c7c35e8b 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b

Re: [PATCH] selftest: fix kselftest-merge depend on 'RUNTIME_TESTING_MENU'

2018-02-28 6:32 GMT+08:00 Anders Roxell <anders.rox...@linaro.org>: > > On 23 February 2018 at 08:05, Zong Li <zong...@gmail.com> wrote: > > 2018-02-23 3:57 GMT+08:00 Anders Roxell <anders.rox...@linaro.org>: > >> On 22 February 2018 at 12:53, Zong Li

Re: [PATCH] selftest: fix kselftest-merge depend on 'RUNTIME_TESTING_MENU'

2018-02-28 6:32 GMT+08:00 Anders Roxell : > > On 23 February 2018 at 08:05, Zong Li wrote: > > 2018-02-23 3:57 GMT+08:00 Anders Roxell : > >> On 22 February 2018 at 12:53, Zong Li wrote: > >>> Since the 'commit d3deafaa8b5c ("lib/: make RUNTIME_TESTS a men

Re: [PATCH] selftest: fix kselftest-merge depend on 'RUNTIME_TESTING_MENU'

2018-02-23 3:57 GMT+08:00 Anders Roxell <anders.rox...@linaro.org>: > On 22 February 2018 at 12:53, Zong Li <zong...@gmail.com> wrote: >> Since the 'commit d3deafaa8b5c ("lib/: make RUNTIME_TESTS a menuconfig >> to ease disabling it all")', the make kself

Re: [PATCH] selftest: fix kselftest-merge depend on 'RUNTIME_TESTING_MENU'

2018-02-23 3:57 GMT+08:00 Anders Roxell : > On 22 February 2018 at 12:53, Zong Li wrote: >> Since the 'commit d3deafaa8b5c ("lib/: make RUNTIME_TESTS a menuconfig >> to ease disabling it all")', the make kselftest-merge cannot merge the >> config dependencies of ks

[PATCH] selftest: support running subset of selftests for run_kselftest.sh

underline as prefix to avoid confilct with built-in command of shell. (e.g. The exec is built-in command of shell) The hyhpen of function name be replace to the underline because not all shells can use hyphen in function name, like sh, ash and so on. Signed-off-by: Zong Li <z...@andestech.com&

[PATCH] selftest: support running subset of selftests for run_kselftest.sh

underline as prefix to avoid confilct with built-in command of shell. (e.g. The exec is built-in command of shell) The hyhpen of function name be replace to the underline because not all shells can use hyphen in function name, like sh, ash and so on. Signed-off-by: Zong Li Cc: Greentime Hu Cc: Shuah

[PATCH] selftest: fix kselftest-merge depend on 'RUNTIME_TESTING_MENU'

ING_MENU=y' at the same time. Signed-off-by: Zong Li <z...@andestech.com> Cc: Greentime Hu <greent...@andestech.com> --- tools/testing/selftests/bpf/config | 1 + tools/testing/selftests/firmware/config| 1 + tools/testing/selftests/kmod/config| 1 + tools/testin

[PATCH] selftest: fix kselftest-merge depend on 'RUNTIME_TESTING_MENU'

ING_MENU=y' at the same time. Signed-off-by: Zong Li Cc: Greentime Hu --- tools/testing/selftests/bpf/config | 1 + tools/testing/selftests/firmware/config| 1 + tools/testing/selftests/kmod/config| 1 + tools/testing/selftests/lib/config | 1 + tools/testing/selftests/

[PATCH] RISC-V: Enable IRQ during exception handling

012441f6>] _do_fork+0x1b4/0x1e0 [<f46c3e3b>] ret_from_syscall+0xa/0xe Signed-off-by: Zong Li <z...@andestech.com> --- arch/riscv/kernel/entry.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.

[PATCH] RISC-V: Enable IRQ during exception handling

012441f6>] _do_fork+0x1b4/0x1e0 [<f46c3e3b>] ret_from_syscall+0xa/0xe Signed-off-by: Zong Li --- arch/riscv/kernel/entry.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 7404ec2..61f063e 10

[PATCH v2] selftest: support run subset of selftests when running installed selftests

has underline as prefix to avoid confilct with built-in command of shell. (e.g. The exec is built-in command of shell) Replace the hyphen with underline for cpu-hotplug and memory-hotplug. Not all shell can use hyphen in function name, like sh, ash and so on. Signed-off-by: Zong Li &l

[PATCH v2] selftest: support run subset of selftests when running installed selftests

has underline as prefix to avoid confilct with built-in command of shell. (e.g. The exec is built-in command of shell) Replace the hyphen with underline for cpu-hotplug and memory-hotplug. Not all shell can use hyphen in function name, like sh, ash and so on. Signed-off-by: Zong Li --- tools

[PATCH] selftest: support run subset of selftests when running installed selftests

-in command of shell. (e.g. The exec is built-in command of shell) Replace the hyphen with underline for cpu-hotplug and memory-hotplug. Not all shell can use hyphen in function name, like sh, ash and so on. Signed-off-by: Zong Li <z...@andestech.com> --- tools/testing/selftests/Ma

[PATCH] selftest: support run subset of selftests when running installed selftests

-in command of shell. (e.g. The exec is built-in command of shell) Replace the hyphen with underline for cpu-hotplug and memory-hotplug. Not all shell can use hyphen in function name, like sh, ash and so on. Signed-off-by: Zong Li --- tools/testing/selftests/Makefile| 17

[PATCH] RISC-V: Support built-in dtb

Build the dtb into the kernel image. If the DTB is given via bootloader, the external DTB is adopted first. Signed-off-by: Zong Li <zong...@gmail.com> --- arch/riscv/Kconfig | 4 arch/riscv/Makefile | 9 + arch/riscv/boot/Makefile

[PATCH] RISC-V: Support built-in dtb

Build the dtb into the kernel image. If the DTB is given via bootloader, the external DTB is adopted first. Signed-off-by: Zong Li --- arch/riscv/Kconfig | 4 arch/riscv/Makefile | 9 + arch/riscv/boot/Makefile | 17 + arch/riscv/boot/dts

[PATCH] RISC-V: Support built-in dtb

Build the dtb into the kernel image. If the DTB is given via bootloader, the external DTB is adopted first. Signed-off-by: Zong Li <zong...@gmail.com> --- arch/riscv/Kconfig | 4 arch/riscv/Makefile | 9 + arch/riscv/boot/Makefile

[PATCH] RISC-V: Support built-in dtb

Build the dtb into the kernel image. If the DTB is given via bootloader, the external DTB is adopted first. Signed-off-by: Zong Li --- arch/riscv/Kconfig | 4 arch/riscv/Makefile | 9 + arch/riscv/boot/Makefile | 17 + arch/riscv/boot/dts

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