>First of all, can you fix your mail so that you have a proper 'From'?
>That should be your real name (not bpqw), so that it gives a proper patch
>author.
>If you can't get your mail header to have the right 'From:' line, then it also
>works to begin your mail with:
Sorry for
>You probably aren't based on l2-mtd.git. Your patch still doesn't build.
>I can fix it up if it's easy, but FYI. Still reviewing...
>Brian
Hi, Brian
Thanks for your hard work. Finally received your response, I am very happy.
How about this patch? Whether or not rebuild it based on lastest
You probably aren't based on l2-mtd.git. Your patch still doesn't build.
I can fix it up if it's easy, but FYI. Still reviewing...
Brian
Hi, Brian
Thanks for your hard work. Finally received your response, I am very happy.
How about this patch? Whether or not rebuild it based on lastest l2-mtd?
First of all, can you fix your mail so that you have a proper 'From'?
That should be your real name (not bpqw), so that it gives a proper patch
author.
If you can't get your mail header to have the right 'From:' line, then it also
works to begin your mail with:
Sorry for this confusion
>> This maybe your spi controller is still extended mode, Once EVCR bit 7
>> is set to 0, the spi nor device will operate in quad
>> I/O.Command-address-data line is 4-x-4.
>> So after send WRITE EVCR command , spi controller also must transfer
>> to quad I/O Mode,and set its
This maybe your spi controller is still extended mode, Once EVCR bit 7
is set to 0, the spi nor device will operate in quad
I/O.Command-address-data line is 4-x-4.
So after send WRITE EVCR command , spi controller also must transfer
to quad I/O Mode,and set its Command-address-data line
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology,Inc.is an American multinational corporation based in Boise,
Idaho,best known for producing many forms of semiconductor devices.This includes
DRAM,SDRAM,flash memory,eMMC and SSDs.
>Patch looks okay to me content-wise, but you might want to use proper names
>and
>capitalization for the From: and Signed-off-by: lines. bpqw doesn't look like
>a real name to me, and "bean huo" should probably be "Bean Huo".
>Thierry
Thanks,will modify
Patch looks okay to me content-wise, but you might want to use proper names
and
capitalization for the From: and Signed-off-by: lines. bpqw doesn't look like
a real name to me, and bean huo should probably be Bean Huo.
Thierry
Thanks,will modify it and submit V3.
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To unsubscribe from
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology,Inc.is an American multinational corporation based in Boise,
Idaho,best known for producing many forms of semiconductor devices.This includes
DRAM,SDRAM,flash memory,eMMC and SSDs.
>I have almost verified all the micros parts for operating quad mode and the
>quad enable bit is
>volatile by default and no need to set it on software.
>Why this code is meant for - does micron has changed this bit operation on
>newly added parts?
>thanks!
>--
>Jagan.
For Micron Spi
>Signed-off-by: bean huo
>Signed-off-by: bpqw
>---
>V2:
> - Add signed-off-by
> - Modify commit logs that wrapped to less than 80 columns
Dear maintainers:
Please give some tips,if this patch is OK?thanks!
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>Hi, I'm having trouble with this patch using a Cadence QSPI controller and
>Micron n25q00 part.
>I can use quad commands in Extended SPI mode, but I can't make this EVCR Quad
>mode work.
Yes,but if you use quad commands in Extended spi mode,only for Quad
commands,the command line is DQ0,
Hi, I'm having trouble with this patch using a Cadence QSPI controller and
Micron n25q00 part.
I can use quad commands in Extended SPI mode, but I can't make this EVCR Quad
mode work.
Yes,but if you use quad commands in Extended spi mode,only for Quad
commands,the command line is DQ0,
Signed-off-by: bean huo bean...@micron.com
Signed-off-by: bpqw b...@micron.com
---
V2:
- Add signed-off-by
- Modify commit logs that wrapped to less than 80 columns
Dear maintainers:
Please give some tips,if this patch is OK?thanks!
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I have almost verified all the micros parts for operating quad mode and the
quad enable bit is
volatile by default and no need to set it on software.
Why this code is meant for - does micron has changed this bit operation on
newly added parts?
thanks!
--
Jagan.
For Micron Spi norflash,if you
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash,enabling or disabling quad I/O protocol is controlled
by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0,the SPI NOR flash will operate in
>> This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
>Also, your patch is still corrupt and cannot be applied as-is.
>Please double-check your mailer settings and resend once you have something I
>can apply.
>Brian
Hi,Brian
Thanks your patience.this maybe linux
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
Also, your patch is still corrupt and cannot be applied as-is.
Please double-check your mailer settings and resend once you have something I
can apply.
Brian
Hi,Brian
Thanks your patience.this maybe linux kernel has
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash,enabling or disabling quad I/O protocol is controlled
by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0,the SPI NOR flash will operate in
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash,enabling or disabling quad I/O protocol is controlled
by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0,the SPI NOR flash will operate in
.
Signed-off-by: bean huo
Signed-off-by: bpqw
---
V2:
- Add signed-off-by
- Modify commit logs that wrapped to less than 80 columns
.../devicetree/bindings/vendor-prefixes.txt|1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
.
Signed-off-by: bean huo bean...@micron.com
Signed-off-by: bpqw b...@micron.com
---
V2:
- Add signed-off-by
- Modify commit logs that wrapped to less than 80 columns
.../devicetree/bindings/vendor-prefixes.txt|1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash,enabling or disabling quad I/O protocol is controlled
by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0,the SPI NOR flash will operate in
>This patch is used to add vendor prefix for
>Micron Technology Inc in the vendor-prefixes.txt file.
>Micron Technology, Inc. is an American
>multinational corporation based in Boise,
>Idaho, best known for producing many forms
>of semiconductor devices. This includes DRAM,
>SDRAM, flash
This patch is used to add vendor prefix
for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American
multinational corporation based in Boise,
Idaho, best known for producing many forms
of semiconductor devices. This includes DRAM,
SDRAM, flash memory,
This patch is used to add vendor prefix
for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American
multinational corporation based in Boise,
Idaho, best known for producing many forms
of semiconductor devices. This includes DRAM,
SDRAM, flash memory,
This patch is used to add vendor prefix for
Micron Technology Inc in the vendor-prefixes.txt file.
Micron Technology, Inc. is an American
multinational corporation based in Boise,
Idaho, best known for producing many forms
of semiconductor devices. This includes DRAM,
SDRAM, flash memory, eMMC
>This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
>For Micron SPI NOR flash, enabling or disabling quad I/O
>protocol is controlled by EVCR (Enhanced Volatile Configuration
>Register), Quad I/O protocol bit 7.When EVCR bit 7 is reset to 0,
>the SPI NOR flash will
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash, enabling or disabling quad I/O
protocol is controlled by EVCR (Enhanced Volatile Configuration
Register), Quad I/O protocol bit 7.When EVCR bit 7 is reset to 0,
the SPI NOR flash will operate in
Hi,rafal
Maybe this patch is not very reasonable.But for fix this case,I will develop a
new patch that
is just used to add extended ID for micron spi nor in the spi_nor_ids[].
Thanks for your review my patch.
Hi,Mark
>This is the *third* time you've sent this patch this week, please stop and
>allow a reasonable time for the maintainers to respond, a few weeks would be
>normal.
I'm sorry,I'm new linux patch deveploper and this is my second patch.
Maybe my experience is not rich,there is a little
Hi,Mark
This is the *third* time you've sent this patch this week, please stop and
allow a reasonable time for the maintainers to respond, a few weeks would be
normal.
I'm sorry,I'm new linux patch deveploper and this is my second patch.
Maybe my experience is not rich,there is a little
Hi,rafal
Maybe this patch is not very reasonable.But for fix this case,I will develop a
new patch that
is just used to add extended ID for micron spi nor in the spi_nor_ids[].
Thanks for your review my patch.
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled
by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0, the SPI NOR flash will operate in
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American multinational corporation based in Boise,
Idaho, best known for producing many forms of semiconductor devices. This
includes
DRAM, SDRAM, flash memory, eMMC
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American multinational corporation based in Boise,
Idaho, best known for producing many forms of semiconductor devices. This
includes
DRAM, SDRAM, flash memory, eMMC
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled
by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0, the SPI NOR flash will operate in
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American multinational corporation based in
Boise, Idaho,
best known for producing many forms of semiconductor devices. This includes
DRAM, SDRAM,
flash memory,
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American multinational corporation based in
Boise, Idaho,
best known for producing many forms of semiconductor devices. This includes
DRAM, SDRAM,
flash memory,
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American multinational corporation based in
Boise, Idaho,
best known for producing many forms of semiconductor devices. This includes
DRAM, SDRAM,
flash memory,
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American multinational corporation based in
Boise, Idaho,
best known for producing many forms of semiconductor devices. This includes
DRAM, SDRAM,
flash memory,
>This patch is used to add vendor prefix for Micron Technology Inc in the
>vendor-prefixes.txt file.
>Micron Technology, Inc. is an American multinational corporation based in
>Boise, Idaho, best known for producing many forms of semiconductor devices.
>This includes DRAM, SDRAM, flash memory,
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American multinational corporation based in
Boise, Idaho, best known for producing many forms of semiconductor devices.
This includes DRAM, SDRAM, flash memory, eMMC
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American multinational corporation
based in Boise, Idaho, best known for producing many forms of
semiconductor devices. This includes DRAM, SDRAM, flash memory,
eMMC
This patch is used to add vendor prefix for Micron Technology Inc in the
vendor-prefixes.txt file.
Micron Technology, Inc. is an American multinational corporation
based in Boise, Idaho, best known for producing many forms of
semiconductor devices. This includes DRAM, SDRAM, flash memory,
eMMC
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled
by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0, the SPI NOR flash will operate
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled
by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0, the SPI NOR flash will operate
>I really wasn't looking into details yet and I'm aware my patch does something
>else. I just say we should first fix the regression and then base next patches
>on top of that regression fix. I'm not NACKing your changes :)
I will take into account for your patch,and will cover all these isse
I really wasn't looking into details yet and I'm aware my patch does something
else. I just say we should first fix the regression and then base next patches
on top of that regression fix. I'm not NACKing your changes :)
I will take into account for your patch,and will cover all these isse in
>Acked-by: Marek Vasut
Hi,brian
How about this patch? And can be accepted by linux-mtd?
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Please read
>Won't $info contain an undefined value in case the newly added condition isn't
>met ? The old code initialized $info to a certain value always, the new code
>does not do that.
Hi,Marek Vasut
Thanks.the $info has been defined before as below:
info = (void *)id->driver_data;
Unless id has
Won't $info contain an undefined value in case the newly added condition isn't
met ? The old code initialized $info to a certain value always, the new code
does not do that.
Hi,Marek Vasut
Thanks.the $info has been defined before as below:
info = (void *)id-driver_data;
Unless id has not
Acked-by: Marek Vasut ma...@denx.de
Hi,brian
How about this patch? And can be accepted by linux-mtd?
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This patch used to modify the method of spi_nor_scan overwrite platform Id.
If type of platform data match with the name of spi_nor_ids set,
and JEDEC ID also match with INFO ID of spi_nor_ids set,spi device
ID point(this is before probed according to device name) shouldn't be
This patch used to modify the method of spi_nor_scan overwrite platform Id.
If type of platform data match with the name of spi_nor_ids set,
and JEDEC ID also match with INFO ID of spi_nor_ids set,spi device
ID point(this is before probed according to device name) shouldn't be
>> Signed-off-by: bean huo
>I don't see anything obviously wrong.
>Acked-by: Marek Vasut
Hi,Brian
How do you think about this patch?
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Signed-off-by: bean huo bean...@micron.com
I don't see anything obviously wrong.
Acked-by: Marek Vasut ma...@denx.de
Hi,Brian
How do you think about this patch?
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the body of a message to majord...@vger.kernel.org
More
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled
by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0, the SPI NOR flash will operate
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
For Micron SPI NOR flash, enabling or disabling quad I/O protocol is controlled
by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
When EVCR bit 7 is reset to 0, the SPI NOR flash will operate
>> For Micron spi norflash,you can enable Quad spi transfer by clear
>> EVCR(Enhanced Volatile Configuration Register) Quad I/O protocol bit.
>
>OK, this information is nice and all, but what does this patch do? I can't
>learn this information from the commit message as it is, can I ?
>And ,
For Micron spi norflash,you can enable Quad spi transfer by clear
EVCR(Enhanced Volatile Configuration Register) Quad I/O protocol bit.
OK, this information is nice and all, but what does this patch do? I can't
learn this information from the commit message as it is, can I ?
And , the
For Micron spi norflash,you can enable
Quad spi transfer by clear EVCR(Enhanced
Volatile Configuration Register) Quad I/O
protocol bit.
Signed-off-by: bean huo
---
v1-v2:modified to that capture wait_till_ready()
return value,if error,directly return its
the value.
For Micron spi norflash,you can enable
Quad spi transfer by clear EVCR(Enhanced
Volatile Configuration Register) Quad I/O
protocol bit.
Signed-off-by: bean huo bean...@micron.com
---
v1-v2:modified to that capture wait_till_ready()
return value,if error,directly return its
the
>> +/* set EVCR ,enable quad I/O */
>> +nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
>> +ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
>> +if (ret < 0) {
>> +dev_err(nor->dev,
>> +"error while writing EVCR register\n");
>> +
+/* set EVCR ,enable quad I/O */
+nor-cmd_buf[0] = val ~EVCR_QUAD_EN_MICRON;
+ret = nor-write_reg(nor, SPINOR_OP_WD_EVCR, nor-cmd_buf, 1, 0);
+if (ret 0) {
+dev_err(nor-dev,
+error while writing EVCR register\n);
+return -EINVAL;
For Micron spi norflash,you can enable Quad spi transfer
by clear EVCR(Enhanced Volatile Configuration Register)
Quad I/O protocol bit.
Signed-off-by: bean huo
---
drivers/mtd/spi-nor/spi-nor.c | 45 +
include/linux/mtd/spi-nor.h |6 ++
2
For Micron spi norflash,you can enable Quad spi transfer
by clear EVCR(Enhanced Volatile Configuration Register)
Quad I/O protocol bit.
Signed-off-by: bean huo bean...@micron.com
---
drivers/mtd/spi-nor/spi-nor.c | 45 +
include/linux/mtd/spi-nor.h |
For Micron M29EW,20ms delay is needed after erase operation.
Signed-off-by: BeanHuo
---
drivers/mtd/chips/cfi_cmdset_0002.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c
b/drivers/mtd/chips/cfi_cmdset_0002.c
index 5a4bfe3..9b0de91 100644
For Micron M29EW,20ms delay is needed after erase operation.
Signed-off-by: BeanHuo b...@micron.com
---
drivers/mtd/chips/cfi_cmdset_0002.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c
b/drivers/mtd/chips/cfi_cmdset_0002.c
index
nal Message-
From: Brian Norris [mailto:computersforpe...@gmail.com]
Sent: Tuesday, August 05, 2014 6:48 AM
To: bpqw
Cc: dw...@infradead.org; b32...@freescale.com;
artem.bityuts...@linux.intel.com; r...@debian.org;
u.kleine-koe...@pengutronix.de; ezequiel.gar...@free-electrons.com;
linux-..
-
From: Brian Norris [mailto:computersforpe...@gmail.com]
Sent: Tuesday, August 05, 2014 6:48 AM
To: bpqw
Cc: dw...@infradead.org; b32...@freescale.com;
artem.bityuts...@linux.intel.com; r...@debian.org;
u.kleine-koe...@pengutronix.de; ezequiel.gar...@free-electrons.com;
linux
Hi Brain,
How about my patch? Do you have any other doubts?
Br
White Ding
-Original Message-
From: bpqw
Sent: Monday, July 28, 2014 3:47 PM
To: Brian Norris; bpqw
Cc: dw...@infradead.org; b32...@freescale.com;
artem.bityuts...@linux.intel.com; r...@debian.org;
u.kleine-koe
Hi Brain,
How about my patch? Do you have any other doubts?
Br
White Ding
-Original Message-
From: bpqw
Sent: Monday, July 28, 2014 3:47 PM
To: Brian Norris; bpqw
Cc: dw...@infradead.org; b32...@freescale.com;
artem.bityuts...@linux.intel.com; r...@debian.org;
u.kleine-koe
Hi Brain,
How about my patch do you have any other proposal?
Br
White Ding
EBU APAC Application Engineering
Tel:86-21-38997078
Mobile: 86-13761729112
Address: No 601 Fasai Rd, Waigaoqiao Free Trade Zone Pudong, Shanghai, China
-Original Message-
From: bpqw
Hi Brain,
How about my patch do you have any other proposal?
Br
White Ding
EBU APAC Application Engineering
Tel:86-21-38997078
Mobile: 86-13761729112
Address: No 601 Fasai Rd, Waigaoqiao Free Trade Zone Pudong, Shanghai, China
-Original Message-
From: bpqw
on to a locked block.
Br
White Ding
EBU APAC Application Engineering
Tel:86-21-38997078
Mobile: 86-13761729112
Address: No 601 Fasai Rd, Waigaoqiao Free Trade Zone Pudong, Shanghai, China
-Original Message-
From: Brian Norris [mailto:computers
APAC Application Engineering
Tel:86-21-38997078
Mobile: 86-13761729112
Address: No 601 Fasai Rd, Waigaoqiao Free Trade Zone Pudong, Shanghai, China
-Original Message-
From: Brian Norris [mailto:computersforpe...@gmail.com]
Sent: Monday, July 28, 2014 2:10 PM
To: bpqw
Cc: dw
>OK, I won't drop them yet.
>As you note, there's no user-space support. There's actually no one using them
>even in the kernel, which is why I considered dropping them.
>If you want to use them, find a proper way to use them then! (I'm not
>sure: do they match with mtd_lock() / ioctl(MEMLOCK)
OK, I won't drop them yet.
As you note, there's no user-space support. There's actually no one using them
even in the kernel, which is why I considered dropping them.
If you want to use them, find a proper way to use them then! (I'm not
sure: do they match with mtd_lock() / ioctl(MEMLOCK)
Do nand reset before write protect check
If we want to check the WP# low or high through STATUS READ and check bit 7,
we must reset the device, other operation (eg.erase/program a locked block) can
also clear the bit 7 of status register.
Signed-off-by: White Ding
---
Do nand reset before write protect check
If we want to check the WP# low or high through STATUS READ and check bit 7,
we must reset the device, other operation (eg.erase/program a locked block) can
also clear the bit 7 of status register.
Signed-off-by: White Ding b...@micron.com
---
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