[PATCH V3 08/13] perf test: Add test case for PERF_SAMPLE_DATA_PAGE_SIZE

From: Kan Liang Extend sample-parsing test cases to support new sample type PERF_SAMPLE_DATA_PAGE_SIZE. Signed-off-by: Kan Liang --- No changes since V1 tools/perf/tests/sample-parsing.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/sample

[PATCH V3 10/13] perf tools: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

From: Stephane Eranian Adds the infrastructure to sample the code address page size. Introduce a new --code-page-size option for perf record. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- No changes since V1 tools/include/uapi/linux/perf_event.h| 4 +++- tools/perf

[PATCH V3 05/13] perf mem: Factor out a function to generate sort order

From: Kan Liang Now, "--phys-data" is the only option which impacts the sort order. A simple "if else" is enough to handle the option. But there will be more options added, e.g. "--data-page-size", which also impact the sort order. The code will become too com

[PATCH V3 13/13] perf test: Add test case for PERF_SAMPLE_CODE_PAGE_SIZE

From: Stephane Eranian Extend sample-parsing test cases to support new sample type PERF_SAMPLE_CODE_PAGE_SIZE. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- No changes since V1 tools/perf/tests/sample-parsing.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff

[PATCH V3 09/13] perf/core, x86: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

the generic support is covered. The large PEBS will be disabled with this sample type. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- No changes since V1 include/linux/perf_event.h | 1 + include/uapi/linux/perf_event.h | 4 +++- kernel/events/core.c| 11

[PATCH V3 04/13] perf sort: Add sort option for data page size

From: Kan Liang Add a new sort option "data_page_size" for --mem-mode sort. With this option applied, perf can sort and report by sample's data page size. Here is an example. perf report --stdio --mem-mode --sort=comm,symbol,phys_daddr,data_page_size # To display the perf.data h

[PATCH V3 12/13] perf report: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

C Coverage] # ... .. # # 69.56% dtlb [.] GetTickCount 4K - 17.93% dtlb [.] Calibrate 4K - - 11.40% dtlb [.] __gettimeofday4K - - Signed-off-by: Stephane Eranian Signed-off-by:

[PATCH V3 11/13] perf script: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

:401095 4K dtlb mem-loads:uP:4010cc 4K dtlb mem-loads:uP:440b6f 4K Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- No changes since V2 tools/perf/Documentation/perf-script.txt | 2 +- tools/perf/builtin-script.c | 76

[PATCH V3 02/13] perf tools: Support new sample type for data page size

From: Kan Liang Support new sample type PERF_SAMPLE_DATA_PAGE_SIZE for page size. Add new option --data-page-size to record sample data page size. Signed-off-by: Kan Liang --- No changes since V1 tools/include/uapi/linux/perf_event.h| 16 +++- tools/perf/Documentation/perf

[PATCH V3 07/13] perf mem: Support data page size

From: Kan Liang Add option --data-page-size in "perf mem" to record/report data page size. Here are some examples. perf mem --phys-data --data-page-size report -D # PID, TID, IP, ADDR, PHYS ADDR, DATA PAGE SIZE, LOCAL WEIGHT, DSRC, # SYMBOL 20134 20134 0xff

[PATCH V3 03/13] perf script: Support data page size

From: Kan Liang Display the data page size if it is available. Can be configured by the user, for example: perf script --fields comm,event,phys_addr,data_page_size dtlb mem-loads:uP:3fec82ea8 4K dtlb mem-loads:uP:3fec82e90 4K dtlb mem

[tip:x86/urgent] x86/cpu: Add Atom Tremont (Jacobsville)

Commit-ID: 00ae831dfe4474ef6029558f5eb3ef0332d80043 Gitweb: https://git.kernel.org/tip/00ae831dfe4474ef6029558f5eb3ef0332d80043 Author: Kan Liang AuthorDate: Fri, 25 Jan 2019 11:59:01 -0800 Committer: Borislav Petkov CommitDate: Tue, 29 Jan 2019 16:37:35 +0100 x86/cpu: Add Atom

[PATCH] perf/x86/intel/uncore: Add Node ID mask

From: Kan Liang Some PCI uncore PMUs cannot be registered on a 8-socket system (HPE Superdome Flex). To understand which Socket the PCI uncore PMUs belong to, perf retrieves the local Node ID of the uncore device from CPUNODEID(0xC0) of the PCI configuration space, and the mapping between

[PATCH V2 07/12] perf test: Add test case for PERF_SAMPLE_DATA_PAGE_SIZE

From: Kan Liang Extend sample-parsing test cases to support new sample type PERF_SAMPLE_DATA_PAGE_SIZE. Signed-off-by: Kan Liang --- No changes since V1 tools/perf/tests/sample-parsing.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/sample

[PATCH V2 04/12] perf sort: Add sort option for data page size

From: Kan Liang Add a new sort option "data_page_size" for --mem-mode sort. With this option applied, perf can sort and report by sample's data page size. Here is an example. perf report --stdio --mem-mode --sort=comm,symbol,phys_daddr,data_page_size # To display the perf.data h

[PATCH V2 02/12] perf tools: Support new sample type for data page size

From: Kan Liang Support new sample type PERF_SAMPLE_DATA_PAGE_SIZE for page size. Add new option --data-page-size to record sample data page size. Signed-off-by: Kan Liang --- No changes since V1 tools/include/uapi/linux/perf_event.h| 16 +++- tools/perf/Documentation/perf

[PATCH V2 12/12] perf test: Add test case for PERF_SAMPLE_CODE_PAGE_SIZE

From: Stephane Eranian Extend sample-parsing test cases to support new sample type PERF_SAMPLE_CODE_PAGE_SIZE. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- No changes since V1 tools/perf/tests/sample-parsing.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff

[PATCH V2 06/12] perf mem: Support data page size

From: Kan Liang Add option --data-page-size in "perf mem" to record/report data page size. Here are some examples. perf mem --phys-data --data-page-size report -D # PID, TID, IP, ADDR, PHYS ADDR, DATA PAGE SIZE, LOCAL WEIGHT, DSRC, # SYMBOL 20134 20134 0xff

[PATCH V2 10/12] perf script: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

:401095 4K dtlb mem-loads:uP:4010cc 4K dtlb mem-loads:uP:440b6f 4K Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- Changes since V1: - Use ULL to replace UL for 32bit. tools/perf/Documentation/perf-script.txt | 2 +- tools/perf

[PATCH V2 09/12] perf tools: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

From: Stephane Eranian Adds the infrastructure to sample the code address page size. Introduce a new --code-page-size option for perf record. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- No changes since V1 tools/include/uapi/linux/perf_event.h| 4 +++- tools/perf

[PATCH V2 11/12] perf report: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

C Coverage] # ... .. # # 69.56% dtlb [.] GetTickCount 4K - 17.93% dtlb [.] Calibrate 4K - - 11.40% dtlb [.] __gettimeofday4K - - Signed-off-by: Stephane Eranian Signed-off-by:

[PATCH V2 01/12] perf/core, x86: Add PERF_SAMPLE_DATA_PAGE_SIZE

From: Kan Liang Current perf can report both virtual address and physical address, but it doesn't report page size. Users have no idea how large the utilized page is. They cannot promote/demote large pages to optimize memory use. Add a new sample type for data page size. Current perf already

[PATCH V2 05/12] perf mem: Clean up output format and sort order string

From: Kan Liang Now, "--phys-data" is the only option which impacts the output format and sort order. A simple "if else" is enough to handle the option. But there will be more options added, e.g. "--data-page-size", which also impact the output format and sort o

[PATCH V2 03/12] perf script: Support data page size

From: Kan Liang Display the data page size if it is available. Can be configured by the user, for example: perf script --fields comm,event,phys_addr,data_page_size dtlb mem-loads:uP:3fec82ea8 4K dtlb mem-loads:uP:3fec82e90 4K dtlb mem

[PATCH V2 08/12] perf/core, x86: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

the generic support is covered. The large PEBS will be disabled with this sample type. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- No changes since V1 include/linux/perf_event.h | 1 + include/uapi/linux/perf_event.h | 4 +++- kernel/events/core.c| 11

[PATCH V6 5/5] perf/x86/intel: Add counter freezing quirk for Goldmont

From: Kan Liang A microcode patch is also needed for Goldmont while counter freezing feature is enabled. Otherwise, there will be some issues, e.g. PMI lost. Signed-off-by: Kan Liang --- Changes since V5: - Apply the new name arch/x86/events/intel/core.c | 9 +++-- 1 file changed, 7

[PATCH V6 4/5] perf/x86/intel: Clean up counter freezing quirk

From: Kan Liang Clean up counter freezing quirk to use the new facility to check for min microcode revisions. Rename the counter freezing quirk related functions. Because other platforms, e.g. Goldmont, also needs to call the quirk. Only check the boot CPU, assuming models and features

[PATCH V6 3/5] perf/x86/intel: Clean up SNB pebs quirk

From: Kan Liang Clean up SNB pebs quirk to use the new facility to check for min microcode revisions. Only check the boot CPU, assuming models and features are consistent over all CPUs. Signed-off-by: Kan Liang --- Changes since V5: - New patch to address Peter's comments. arch/x86/events

[PATCH V6 2/5] perf/x86/kvm: Avoid unnecessary work in guest filtering

Signed-off-by: Andi Kleen Signed-off-by: Kan Liang --- Changes since V5: - The microcode patch has already been merged into future platforms. So this patch is actually one-off things. The quirks is still used in the patch. Rename pebs_isolated to pebs_no_isolation. The default value is

[PATCH V6 1/5] x86/cpufeature: Add facility to check for min microcode revisions

From: Kan Liang For bug workarounds or checks, it is useful to check for specific microcode revisions. Add a new generic function to match the CPU with stepping. Add the other function to check the min microcode revisions for the matched CPU. A new table format is introduced to facilitate

[PATCH 04/12] perf sort: Add sort option for data page size

From: Kan Liang Add a new sort option "data_page_size" for --mem-mode sort. With this option applied, perf can sort and report by sample's data page size. Here is an example. perf report --stdio --mem-mode --sort=comm,symbol,phys_daddr,data_page_size # To display the perf.data h

[PATCH 08/12] perf/core, x86: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

the generic support is covered. The large PEBS will be disabled with this sample type. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- include/linux/perf_event.h | 1 + include/uapi/linux/perf_event.h | 4 +++- kernel/events/core.c| 11 ++- 3 files changed, 14

[PATCH 01/12] perf/core, x86: Add PERF_SAMPLE_DATA_PAGE_SIZE

From: Kan Liang Current perf can report both virtual address and physical address, but it doesn't report page size. Users have no idea how large the utilized page is. They cannot promote/demote large pages to optimize memory use. Add a new sample type for data page size. Current perf already

[PATCH 09/12] perf tools: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

From: Stephane Eranian Adds the infrastructure to sample the code address page size. Introduce a new --code-page-size option for perf record. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- tools/include/uapi/linux/perf_event.h| 4 +++- tools/perf/Documentation/perf

[PATCH 07/12] perf test: Add test case for PERF_SAMPLE_DATA_PAGE_SIZE

From: Kan Liang Extend sample-parsing test cases to support new sample type PERF_SAMPLE_DATA_PAGE_SIZE. Signed-off-by: Kan Liang --- tools/perf/tests/sample-parsing.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/sample-parsing.c b/tools/perf

[PATCH 03/12] perf script: Support data page size

From: Kan Liang Display the data page size if it is available. Can be configured by the user, for example: perf script --fields comm,event,phys_addr,data_page_size dtlb mem-loads:uP:3fec82ea8 4K dtlb mem-loads:uP:3fec82e90 4K dtlb mem

[PATCH 11/12] perf report: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

C Coverage] # ... .. # # 69.56% dtlb [.] GetTickCount 4K - 17.93% dtlb [.] Calibrate 4K - - 11.40% dtlb [.] __gettimeofday4K - - Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang

[PATCH 10/12] perf script: Add support for PERF_SAMPLE_CODE_PAGE_SIZE

:401095 4K dtlb mem-loads:uP:4010cc 4K dtlb mem-loads:uP:440b6f 4K Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- tools/perf/Documentation/perf-script.txt | 2 +- tools/perf/builtin-script.c | 76

[PATCH 12/12] perf test: Add test case for PERF_SAMPLE_CODE_PAGE_SIZE

From: Stephane Eranian Extend sample-parsing test cases to support new sample type PERF_SAMPLE_CODE_PAGE_SIZE. Signed-off-by: Stephane Eranian Signed-off-by: Kan Liang --- tools/perf/tests/sample-parsing.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tools/perf

[PATCH 06/12] perf mem: Support data page size

From: Kan Liang Add option --data-page-size in "perf mem" to record/report data page size. Here are some examples. perf mem --phys-data --data-page-size report -D # PID, TID, IP, ADDR, PHYS ADDR, DATA PAGE SIZE, LOCAL WEIGHT, DSRC, # SYMBOL 20134 20134 0xff

[PATCH 02/12] perf tools: Support new sample type for data page size

From: Kan Liang Support new sample type PERF_SAMPLE_DATA_PAGE_SIZE for page size. Add new option --data-page-size to record sample data page size. Signed-off-by: Kan Liang --- tools/include/uapi/linux/perf_event.h| 16 +++- tools/perf/Documentation/perf-record.txt | 3

[PATCH 05/12] perf mem: Clean up output format and sort order string

From: Kan Liang Now, "--phys-data" is the only option which impacts the output format and sort order. A simple "if else" is enough to handle the option. But there will be more options added, e.g. "--data-page-size", which also impact the output format and sort o

[PATCH V5 4/4] perf/x86/intel: Add counter freezing quirk for Goldmont

From: Kan Liang A ucode patch is also needed for Goldmont while counter freezing feature is enabled. Otherwise, there will be some issues, e.g. PMI lost. Signed-off-by: Kan Liang --- - New patch, merged from https://lkml.org/lkml/2018/10/3/25 arch/x86/events/intel/core.c | 5 + 1 file

[PATCH V5 1/4] x86/cpufeature: Add facility to check for min microcode revisions

From: Kan Liang For bug workarounds or checks it is useful to check for specific microcode revisions. Add a new generic function to match the CPU with stepping. Add the other function to check the min microcode revisions for the matched CPU. A new table format is introduced to facilitate

[PATCH V5 2/4] perf/x86/kvm: Avoid unnecessary work in guest filtering

From: Andi Kleen KVM added a workaround for PEBS events leaking into guests with commit 26a4f3c08de4 ("perf/x86: disable PEBS on a guest entry.") This uses the VT entry/exit list to add an extra disable of the PEBS_ENABLE MSR. Intel also added a fix for this issue to microcode updates on

[PATCH V5 3/4] perf/x86/intel: Clean up counter freezing quirk

From: Kan Liang Clean up counter freezing quirk to use the new facility to check for min microcode revisions. Rename the counter freezing quirk related functions. Because other platforms, e.g. Goldmont, also needs to call the quirk. Signed-off-by: Kan Liang --- - New patch, merged from https

[PATCH] perf/x86/intel: Fix inaccurate period in context switch for auto-reload

From: Kan Liang When a task, which is sampled by a PEBS event with a fixed period, is sched_in, the fixed period will always be used as new period for counter. It's inaccurate, because the left period from last sched_out isn't taken into account. The auto-reload feature is implicitly enabled

[PATCH] perf/x86/intel: Fix inaccurate period in context switch for auto-reload

From: Kan Liang When a task, which is sampled by a PEBS event with a fixed period, is sched_in, the fixed period will always be used as new period for counter. It's inaccurate, because the left period from last sched_out isn't taken into account. The auto-reload feature is implicitly enabled

[RFC PATCH] KVM/x86/vPMU: Avoid counter reprogramming in kvm_pmu_handle_event

From: Kan Liang In the process of handling a guest overflow, KVM unconditionally reprograms perf counters before entering guest. The reprogramming brings very high overhead. For common case, (e.g. vCPU still runs on the same CPU), it's unnecessary. Here is current process of handling

[RFC PATCH] KVM/x86/vPMU: Avoid counter reprogramming in kvm_pmu_handle_event

From: Kan Liang In the process of handling a guest overflow, KVM unconditionally reprograms perf counters before entering guest. The reprogramming brings very high overhead. For common case, (e.g. vCPU still runs on the same CPU), it's unnecessary. Here is current process of handling

[tip:perf/core] perf pmu: Move *_cpuid_str() weak functions to header.c

Commit-ID: f4a0742b3cc1d03b2ff448017b8c714a77e5a261 Gitweb: https://git.kernel.org/tip/f4a0742b3cc1d03b2ff448017b8c714a77e5a261 Author: Kan Liang AuthorDate: Wed, 21 Nov 2018 08:49:39 -0800 Committer: Arnaldo Carvalho de Melo CommitDate: Wed, 21 Nov 2018 22:39:59 -0300 perf pmu: Move

[tip:perf/core] perf pmu: Move *_cpuid_str() weak functions to header.c

Commit-ID: f4a0742b3cc1d03b2ff448017b8c714a77e5a261 Gitweb: https://git.kernel.org/tip/f4a0742b3cc1d03b2ff448017b8c714a77e5a261 Author: Kan Liang AuthorDate: Wed, 21 Nov 2018 08:49:39 -0800 Committer: Arnaldo Carvalho de Melo CommitDate: Wed, 21 Nov 2018 22:39:59 -0300 perf pmu: Move

[tip:perf/core] perf vendor events: Add stepping in CPUID string for x86

Commit-ID: 3b54411a4485c9f1d50f003810ecfceca82a09ae Gitweb: https://git.kernel.org/tip/3b54411a4485c9f1d50f003810ecfceca82a09ae Author: Kan Liang AuthorDate: Wed, 14 Nov 2018 13:24:15 -0800 Committer: Arnaldo Carvalho de Melo CommitDate: Wed, 21 Nov 2018 22:39:57 -0300 perf vendor

[tip:perf/core] perf vendor events: Add stepping in CPUID string for x86

Commit-ID: 3b54411a4485c9f1d50f003810ecfceca82a09ae Gitweb: https://git.kernel.org/tip/3b54411a4485c9f1d50f003810ecfceca82a09ae Author: Kan Liang AuthorDate: Wed, 14 Nov 2018 13:24:15 -0800 Committer: Arnaldo Carvalho de Melo CommitDate: Wed, 21 Nov 2018 22:39:57 -0300 perf vendor

[PATCH] perf pmu: Move *_cpuid_str() weak functions to header.c

From: Kan Liang The weak functions, strcmp_cpuid_str() and get_cpuid_str(), are defined in pmu.c. Most of the cpuid related functions, including *_cpuid_str()'s declaration and platform specific definition, are in header.c/h. To make the declaration and definition of all cpuid related functions

[PATCH] perf pmu: Move *_cpuid_str() weak functions to header.c

From: Kan Liang The weak functions, strcmp_cpuid_str() and get_cpuid_str(), are defined in pmu.c. Most of the cpuid related functions, including *_cpuid_str()'s declaration and platform specific definition, are in header.c/h. To make the declaration and definition of all cpuid related functions

[PATCH V3] perf/x86/intel/uncore: Fix client IMC events return huge result

From: Kan Liang The client IMC bandwidth events return very huge result. perf stat -e uncore_imc/data_reads/ -e uncore_imc/data_writes/ -I 1 -a 10.000117222 34,788.76 MiB uncore_imc/data_reads/ 10.000117222 8.26 MiB uncore_imc/data_writes/ 20.000374584 34,842.89 MiB uncore_imc

[PATCH V3] perf/x86/intel/uncore: Fix client IMC events return huge result

From: Kan Liang The client IMC bandwidth events return very huge result. perf stat -e uncore_imc/data_reads/ -e uncore_imc/data_writes/ -I 1 -a 10.000117222 34,788.76 MiB uncore_imc/data_reads/ 10.000117222 8.26 MiB uncore_imc/data_writes/ 20.000374584 34,842.89 MiB uncore_imc

[PATCH V2] perf/x86/intel/uncore: Fix client IMC events return huge result

From: Kan Liang The client IMC bandwidth events return very huge result. perf stat -e uncore_imc/data_reads/ -e uncore_imc/data_writes/ -I 1 -a 10.000117222 34,788.76 MiB uncore_imc/data_reads/ 10.000117222 8.26 MiB uncore_imc/data_writes/ 20.000374584 34,842.89 MiB uncore_imc

[PATCH V2] perf/x86/intel/uncore: Fix client IMC events return huge result

From: Kan Liang The client IMC bandwidth events return very huge result. perf stat -e uncore_imc/data_reads/ -e uncore_imc/data_writes/ -I 1 -a 10.000117222 34,788.76 MiB uncore_imc/data_reads/ 10.000117222 8.26 MiB uncore_imc/data_writes/ 20.000374584 34,842.89 MiB uncore_imc

[PATCH] perf/x86/intel/uncore: Fix client IMC events return huge result

From: Kan Liang The client IMC bandwidth events return very huge result. perf stat -e uncore_imc/data_reads/ -e uncore_imc/data_writes/ -I 1 -a 10.000117222 34,788.76 MiB uncore_imc/data_reads/ 10.000117222 8.26 MiB uncore_imc/data_writes/ 20.000374584 34,842.89 MiB uncore_imc

[PATCH] perf/x86/intel/uncore: Fix client IMC events return huge result

From: Kan Liang The client IMC bandwidth events return very huge result. perf stat -e uncore_imc/data_reads/ -e uncore_imc/data_writes/ -I 1 -a 10.000117222 34,788.76 MiB uncore_imc/data_reads/ 10.000117222 8.26 MiB uncore_imc/data_writes/ 20.000374584 34,842.89 MiB uncore_imc

[PATCH 1/2] perf vendor events: Add stepping in CPUID string for x86

From: Kan Liang Perf tools cannot find the proper event list for Cascadelake server. Because Cascadelake server and Skylake server have the same CPU model number, which are used by perf tools to find the event list. The stepping for Skylake server is up to 4. The stepping for Cascadelake server

[PATCH 1/2] perf vendor events: Add stepping in CPUID string for x86

From: Kan Liang Perf tools cannot find the proper event list for Cascadelake server. Because Cascadelake server and Skylake server have the same CPU model number, which are used by perf tools to find the event list. The stepping for Skylake server is up to 4. The stepping for Cascadelake server

[tip:perf/urgent] perf/x86/intel/uncore: Support CoffeeLake 8th CBOX

Commit-ID: 4d47d6407ac7b4b442a4e717488a3bb137398b6c Gitweb: https://git.kernel.org/tip/4d47d6407ac7b4b442a4e717488a3bb137398b6c Author: Kan Liang AuthorDate: Fri, 19 Oct 2018 10:04:19 -0700 Committer: Ingo Molnar CommitDate: Mon, 12 Nov 2018 05:03:26 +0100 perf/x86/intel/uncore

[tip:perf/urgent] perf/x86/intel/uncore: Support CoffeeLake 8th CBOX

Commit-ID: 4d47d6407ac7b4b442a4e717488a3bb137398b6c Gitweb: https://git.kernel.org/tip/4d47d6407ac7b4b442a4e717488a3bb137398b6c Author: Kan Liang AuthorDate: Fri, 19 Oct 2018 10:04:19 -0700 Committer: Ingo Molnar CommitDate: Mon, 12 Nov 2018 05:03:26 +0100 perf/x86/intel/uncore

[tip:perf/urgent] perf/x86/intel/uncore: Add more IMC PCI IDs for KabyLake and CoffeeLake CPUs

Commit-ID: c10a8de0d32e95b0b8c7c17b6dc09baea5a5a899 Gitweb: https://git.kernel.org/tip/c10a8de0d32e95b0b8c7c17b6dc09baea5a5a899 Author: Kan Liang AuthorDate: Fri, 19 Oct 2018 10:04:18 -0700 Committer: Ingo Molnar CommitDate: Mon, 12 Nov 2018 05:03:24 +0100 perf/x86/intel/uncore: Add

[tip:perf/urgent] perf/x86/intel/uncore: Add more IMC PCI IDs for KabyLake and CoffeeLake CPUs

Commit-ID: c10a8de0d32e95b0b8c7c17b6dc09baea5a5a899 Gitweb: https://git.kernel.org/tip/c10a8de0d32e95b0b8c7c17b6dc09baea5a5a899 Author: Kan Liang AuthorDate: Fri, 19 Oct 2018 10:04:18 -0700 Committer: Ingo Molnar CommitDate: Mon, 12 Nov 2018 05:03:24 +0100 perf/x86/intel/uncore: Add

[RFC PATCH] perf top: Move the timeout warning from event processing thread to display thread

From: Kan Liang The main event processing thread may hang if the ring buffer event processing timeouts. Analysis from David Miller: "It hangs the event thread, because the ui call waits for a keypress but the display thread will eat them up and the event thread thus hangs in s

[RFC PATCH] perf top: Move the timeout warning from event processing thread to display thread

From: Kan Liang The main event processing thread may hang if the ring buffer event processing timeouts. Analysis from David Miller: "It hangs the event thread, because the ui call waits for a keypress but the display thread will eat them up and the event thread thus hangs in s

[PATCH 2/2] perf/x86/intel: Fix missing physical address in large PEBS

From: Kan Liang The physical addresses for the last several samples are always lost in large PEBS. For example, #perf record -e mem-loads:uP --phys-data -c1 -- ./dtlb [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.103 MB perf.data (2661 samples

[PATCH 1/2] perf: Add munmap callback

From: Kan Liang To calculate the physical address, perf needs to walk the pages tables. The related mapping may has already been removed from pages table in some cases (e.g. large PEBS). The virtual address recorded in the first PEBS records may already be unmapped before draining PEBS buffers

[PATCH 2/2] perf/x86/intel: Fix missing physical address in large PEBS

From: Kan Liang The physical addresses for the last several samples are always lost in large PEBS. For example, #perf record -e mem-loads:uP --phys-data -c1 -- ./dtlb [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.103 MB perf.data (2661 samples

[PATCH 1/2] perf: Add munmap callback

From: Kan Liang To calculate the physical address, perf needs to walk the pages tables. The related mapping may has already been removed from pages table in some cases (e.g. large PEBS). The virtual address recorded in the first PEBS records may already be unmapped before draining PEBS buffers

[PATCH 2/2] perf/x86/intel/uncore: Support CoffeeLake 8th CBOX

From: Kan Liang Coffee Lake has 8 core product which has 8 Cboxes. The 8th CBOX is mapped into different MSR space. Increase the num_boxes to 8 to handle the new products. It will not impact the previous platforms, SkyLake, KabyLake and earlier CoffeeLake. Because the num_boxes

[PATCH 2/2] perf/x86/intel/uncore: Support CoffeeLake 8th CBOX

From: Kan Liang Coffee Lake has 8 core product which has 8 Cboxes. The 8th CBOX is mapped into different MSR space. Increase the num_boxes to 8 to handle the new products. It will not impact the previous platforms, SkyLake, KabyLake and earlier CoffeeLake. Because the num_boxes

[PATCH 1/2] perf/x86/intel/uncore: Add more IMC PCI IDs for KabyLake and CoffeeLake

From: Kan Liang KabyLake and CoffeeLake has the same client uncore events as SkyLake. Add the PCI IDs for KabyLake Y, U, S processor line and CoffeeLake U, H, S processor line. Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_snb.c | 115 - 1 file changed

[PATCH 1/2] perf/x86/intel/uncore: Add more IMC PCI IDs for KabyLake and CoffeeLake

From: Kan Liang KabyLake and CoffeeLake has the same client uncore events as SkyLake. Add the PCI IDs for KabyLake Y, U, S processor line and CoffeeLake U, H, S processor line. Signed-off-by: Kan Liang --- arch/x86/events/intel/uncore_snb.c | 115 - 1 file changed

[PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont

From: Kan Liang A ucode patch is also needed for Goldmont while counter freezing feature is enabled. Otherwise, there will be some issues, e.g. PMI lost. Add a quirk to check microcode version. If the system starts with the wrong ucode, leave the counter-freezing feature permanently disabled

[PATCH] perf/x86/intel: Add counter freezing quirk for Goldmont

From: Kan Liang A ucode patch is also needed for Goldmont while counter freezing feature is enabled. Otherwise, there will be some issues, e.g. PMI lost. Add a quirk to check microcode version. If the system starts with the wrong ucode, leave the counter-freezing feature permanently disabled

[tip:perf/core] perf/x86/intel: Add quirk for Goldmont Plus

Commit-ID: 7c5314b88da6d5af98239786772a1c44cc5eb67d Gitweb: https://git.kernel.org/tip/7c5314b88da6d5af98239786772a1c44cc5eb67d Author: Kan Liang AuthorDate: Wed, 8 Aug 2018 00:12:08 -0700 Committer: Ingo Molnar CommitDate: Tue, 2 Oct 2018 10:14:33 +0200 perf/x86/intel: Add quirk

[tip:perf/core] perf/x86/intel: Add quirk for Goldmont Plus

Commit-ID: 7c5314b88da6d5af98239786772a1c44cc5eb67d Gitweb: https://git.kernel.org/tip/7c5314b88da6d5af98239786772a1c44cc5eb67d Author: Kan Liang AuthorDate: Wed, 8 Aug 2018 00:12:08 -0700 Committer: Ingo Molnar CommitDate: Tue, 2 Oct 2018 10:14:33 +0200 perf/x86/intel: Add quirk

[tip:perf/core] perf/x86/intel: Factor out common code of PMI handler

Commit-ID: ba12d20edc5caf9835006d8f3efd4ed18465c75b Gitweb: https://git.kernel.org/tip/ba12d20edc5caf9835006d8f3efd4ed18465c75b Author: Kan Liang AuthorDate: Wed, 8 Aug 2018 00:12:06 -0700 Committer: Ingo Molnar CommitDate: Tue, 2 Oct 2018 10:14:30 +0200 perf/x86/intel: Factor out

[tip:perf/core] perf/x86/intel: Factor out common code of PMI handler

Commit-ID: ba12d20edc5caf9835006d8f3efd4ed18465c75b Gitweb: https://git.kernel.org/tip/ba12d20edc5caf9835006d8f3efd4ed18465c75b Author: Kan Liang AuthorDate: Wed, 8 Aug 2018 00:12:06 -0700 Committer: Ingo Molnar CommitDate: Tue, 2 Oct 2018 10:14:30 +0200 perf/x86/intel: Factor out

[tip:perf/core] perf/x86/intel/uncore: Fix PCI BDF address of M3UPI on SKX

Commit-ID: 9d92cfeaf5215158d26d2991be7f7ff865cb98f3 Gitweb: https://git.kernel.org/tip/9d92cfeaf5215158d26d2991be7f7ff865cb98f3 Author: Kan Liang AuthorDate: Fri, 21 Sep 2018 07:07:06 -0700 Committer: Ingo Molnar CommitDate: Tue, 2 Oct 2018 09:38:02 +0200 perf/x86/intel/uncore: Fix

[tip:perf/core] perf/x86/intel/uncore: Fix PCI BDF address of M3UPI on SKX

Commit-ID: 9d92cfeaf5215158d26d2991be7f7ff865cb98f3 Gitweb: https://git.kernel.org/tip/9d92cfeaf5215158d26d2991be7f7ff865cb98f3 Author: Kan Liang AuthorDate: Fri, 21 Sep 2018 07:07:06 -0700 Committer: Ingo Molnar CommitDate: Tue, 2 Oct 2018 09:38:02 +0200 perf/x86/intel/uncore: Fix

[PATCH] perf/x86/intel/uncore: Fix PCI BDF address of M3UPI on SKX

From: Kan Liang The counters on M3UPI Link 0 and Link 3 don't count. Writing 0 to these counters may causes system crash on some machines. The PCI BDF addresses of M3UPI in current code are incorrect. The correct addresses should be D18:F1 0x204D D18:F2 0x204E D18:F5 0x204D Signed-off

[PATCH] perf/x86/intel/uncore: Fix PCI BDF address of M3UPI on SKX

From: Kan Liang The counters on M3UPI Link 0 and Link 3 don't count. Writing 0 to these counters may causes system crash on some machines. The PCI BDF addresses of M3UPI in current code are incorrect. The correct addresses should be D18:F1 0x204D D18:F2 0x204E D18:F5 0x204D Signed-off

[PATCH] perf/x86/intel/lbr: Optimize context switches for LBR

From: Kan Liang LBR can bring big overhead when the benchmark has high context switches. For example, a sub benchmark of Dacapo, avrora. Baseline: java -jar dacapo-9.12-MR1-bach.jar avrora -n 20 With LBR: perf record --branch-filter any,u -- java -jar dacapo-9.12-MR1-bach.jar avrora -n 20

[PATCH] perf/x86/intel/lbr: Optimize context switches for LBR

From: Kan Liang LBR can bring big overhead when the benchmark has high context switches. For example, a sub benchmark of Dacapo, avrora. Baseline: java -jar dacapo-9.12-MR1-bach.jar avrora -n 20 With LBR: perf record --branch-filter any,u -- java -jar dacapo-9.12-MR1-bach.jar avrora -n 20

[PATCH RFC 3/7] perf script: Support page size

From: Kan Liang Display the page size if it is available. Can be configured by the user, for example: perf script --fields comm,event,phys_addr,page_size dtlb mem-loads:uP:3fec82ea8 4K dtlb mem-loads:uP:3fec82e90 4K dtlb mem-loads:uP

[PATCH RFC 3/7] perf script: Support page size

From: Kan Liang Display the page size if it is available. Can be configured by the user, for example: perf script --fields comm,event,phys_addr,page_size dtlb mem-loads:uP:3fec82ea8 4K dtlb mem-loads:uP:3fec82e90 4K dtlb mem-loads:uP

[PATCH RFC 4/7] perf sort: Add sort option for page size

From: Kan Liang Add a new sort option "page_size" for --mem-mode sort. With this option applied, perf can sort and report by sample's page size. Here is an example. perf report --stdio --mem-mode --sort=comm,symbol,phys_daddr,page_size # To display the perf.data header info,

[PATCH RFC 2/7] perf tools: Support new sample type for page size

From: Kan Liang Support new sample type PERF_SAMPLE_PAGE_SIZE for page size. Add new option --page-size to record sample page size. Signed-off-by: Kan Liang --- tools/include/uapi/linux/perf_event.h| 13 - tools/perf/Documentation/perf-record.txt | 3 +++ tools/perf/builtin

[PATCH RFC 4/7] perf sort: Add sort option for page size

From: Kan Liang Add a new sort option "page_size" for --mem-mode sort. With this option applied, perf can sort and report by sample's page size. Here is an example. perf report --stdio --mem-mode --sort=comm,symbol,phys_daddr,page_size # To display the perf.data header info,

[PATCH RFC 2/7] perf tools: Support new sample type for page size

From: Kan Liang Support new sample type PERF_SAMPLE_PAGE_SIZE for page size. Add new option --page-size to record sample page size. Signed-off-by: Kan Liang --- tools/include/uapi/linux/perf_event.h| 13 - tools/perf/Documentation/perf-record.txt | 3 +++ tools/perf/builtin

[PATCH RFC 5/7] perf mem: Clean up output format and sort order string

From: Kan Liang Now, "--phys-data" is the only option which impacts the output format and sort order. A simple "if else" is enough to handle the option. But there will be more options added, e.g. "--page-size", which also impact the output format and sort order. Th

[PATCH RFC 5/7] perf mem: Clean up output format and sort order string

From: Kan Liang Now, "--phys-data" is the only option which impacts the output format and sort order. A simple "if else" is enough to handle the option. But there will be more options added, e.g. "--page-size", which also impact the output format and sort order. Th

[PATCH RFC 6/7] perf mem: Support page size

From: Kan Liang Add option --page-size in "perf mem" to record/report page size. Here are some examples. perf mem --phys-data --page-size report -D # PID, TID, IP, ADDR, PHYS ADDR, PAGE SIZE, LOCAL WEIGHT, DSRC, SYMBOL 20134 20134 0xb5bd2fd0 0x0169a274e96a308 0x00044

[PATCH RFC 6/7] perf mem: Support page size

From: Kan Liang Add option --page-size in "perf mem" to record/report page size. Here are some examples. perf mem --phys-data --page-size report -D # PID, TID, IP, ADDR, PHYS ADDR, PAGE SIZE, LOCAL WEIGHT, DSRC, SYMBOL 20134 20134 0xb5bd2fd0 0x0169a274e96a308 0x00044

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