Added EDAC support for reporting the ecc errors of synopsys ddr controller.
The ddr ecc controller corrects single bit errors and detects double bit
errors.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes for v3:
- Updated maintainer information
- Driver cleanup as per the review comments
Added EDAC support for reporting the ecc errors of synopsys ddr controller.
The ddr ecc controller corrects single bit errors and detects double bit
errors.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes for v3:
- Updated maintainer information
- Driver cleanup as per
ernel.org; Andreas
>Färber; Punnaiah Choudary Kalluri; Lars-Peter Clausen
>Subject: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella
>
>Hello,
>
>This patch series adds an initial device tree for the Parallella board.
>UART, SD card, Ethernet are enabled.
>Not yet enabled a
; Punnaiah Choudary Kalluri; Lars-Peter Clausen
Subject: [PATCH v2 00/11] ARM: dts: zynq: Prepare Parallella
Hello,
This patch series adds an initial device tree for the Parallella board.
UART, SD card, Ethernet are enabled.
Not yet enabled are HDMI, QSPI flash and 2x USB.
v2 adds some SPI
el@vger.kernel.org;
>devicet...@vger.kernel.org; linux-...@vger.kernel.org; David Woodhouse;
>Brian Norris; Marek Vašut; Artem Bityutskiy; Geert Uytterhoeven; Sascha
>Hauer; Jingoo Han; Sourav Poddar; Michal Simek; Punnaiah Choudary Kalluri
>Subject: Re: [RFC PATCH 1/2] spi: Add support
;
devicet...@vger.kernel.org; linux-...@vger.kernel.org; David Woodhouse;
Brian Norris; Marek Vašut; Artem Bityutskiy; Geert Uytterhoeven; Sascha
Hauer; Jingoo Han; Sourav Poddar; Michal Simek; Punnaiah Choudary Kalluri
Subject: Re: [RFC PATCH 1/2] spi: Add support for Zynq QSPI controller
Hi Geert
Since its a generic driver, support for configuring the dma_mask using
dma_coerce_mask_and_coherent would be good.
Regards,
Punnaiah
On Tue, Jun 24, 2014 at 4:05 PM, Antoine Ténart
wrote:
> Add a generic ChipIdea driver, with optional PHY and clock, to support
> ChipIdea controllers that
Since its a generic driver, support for configuring the dma_mask using
dma_coerce_mask_and_coherent would be good.
Regards,
Punnaiah
On Tue, Jun 24, 2014 at 4:05 PM, Antoine Ténart
antoine.ten...@free-electrons.com wrote:
Add a generic ChipIdea driver, with optional PHY and clock, to support
On Sat, Jun 28, 2014 at 11:16 AM, Peter Chen wrote:
> On Fri, Jun 27, 2014 at 02:55:15PM +0200, Michael Grzeschik wrote:
>> Hi,
>>
>> On Fri, Jun 27, 2014 at 04:53:53PM +0530, Punnaiah Choudary Kalluri wrote:
>> > Zynq soc uses Chipidea/Synopsys usb IP
On Fri, Jun 27, 2014 at 6:25 PM, Michael Grzeschik wrote:
> Hi,
>
> On Fri, Jun 27, 2014 at 04:53:53PM +0530, Punnaiah Choudary Kalluri wrote:
>> Zynq soc uses Chipidea/Synopsys usb IP core(CI13612). This patch adds
>> necessary glue to allow the chipidea driver to work on
On Fri, Jun 27, 2014 at 5:53 PM, Sergei Shtylyov
wrote:
> Hello.
>
>
> On 06/27/2014 03:23 PM, Punnaiah Choudary Kalluri wrote:
>
>> Document device tree binding information as required by
>> the ZYNQ USB controller.
>
>
>> Signed-off-by: Punnaiah Chouda
On Fri, Jun 27, 2014 at 5:53 PM, Sergei Shtylyov
sergei.shtyl...@cogentembedded.com wrote:
Hello.
On 06/27/2014 03:23 PM, Punnaiah Choudary Kalluri wrote:
Document device tree binding information as required by
the ZYNQ USB controller.
Signed-off-by: Punnaiah Choudary Kalluri punn
On Fri, Jun 27, 2014 at 6:25 PM, Michael Grzeschik m...@pengutronix.de wrote:
Hi,
On Fri, Jun 27, 2014 at 04:53:53PM +0530, Punnaiah Choudary Kalluri wrote:
Zynq soc uses Chipidea/Synopsys usb IP core(CI13612). This patch adds
necessary glue to allow the chipidea driver to work on zynq soc
On Sat, Jun 28, 2014 at 11:16 AM, Peter Chen peter.c...@freescale.com wrote:
On Fri, Jun 27, 2014 at 02:55:15PM +0200, Michael Grzeschik wrote:
Hi,
On Fri, Jun 27, 2014 at 04:53:53PM +0530, Punnaiah Choudary Kalluri wrote:
Zynq soc uses Chipidea/Synopsys usb IP core(CI13612). This patch adds
Zynq soc uses Chipidea/Synopsys usb IP core(CI13612). This patch adds
necessary glue to allow the chipidea driver to work on zynq soc.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v2:
- modified the commit message for better readability
- fixed the dev_err message
---
drivers/usb
Document device tree binding information as required by
the ZYNQ USB controller.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v2:
- none
---
.../devicetree/bindings/usb/ci-hdrc-zynq.txt | 23
1 files changed, 23 insertions(+), 0 deletions(-)
create mode
Document device tree binding information as required by
the ZYNQ USB controller.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v2:
- none
---
.../devicetree/bindings/usb/ci-hdrc-zynq.txt | 23
1 files changed, 23 insertions(+), 0
Zynq soc uses Chipidea/Synopsys usb IP core(CI13612). This patch adds
necessary glue to allow the chipidea driver to work on zynq soc.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v2:
- modified the commit message for better readability
- fixed the dev_err message
On Fri, Jun 27, 2014 at 9:09 AM, Peter Chen wrote:
> On Fri, Jun 27, 2014 at 09:10:09AM +0530, Punnaiah Choudary Kalluri wrote:
>> Zynq soc usb controller is a synopsys IP and it is compatible
>> with the chipidea spec. So, reusing chipidea drivers for zynq usb
>> contr
Document device tree binding information as required by
the ZYNQ USB controller.
Signed-off-by: Punnaiah Choudary Kalluri
---
.../devicetree/bindings/usb/ci-hdrc-zynq.txt | 23
1 files changed, 23 insertions(+), 0 deletions(-)
create mode 100644 Documentation
Zynq soc usb controller is a synopsys IP and it is compatible
with the chipidea spec. So, reusing chipidea drivers for zynq usb
controller.
Signed-off-by: Punnaiah Choudary Kalluri
---
drivers/usb/chipidea/Makefile |1 +
drivers/usb/chipidea/ci_hdrc_zynq.c | 115
Add driver for arm pl353 static memory controller nand interface with
HW ECC support. This controller is used in xilinx zynq soc for interfacing
the nand flash memory.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v3:
- implemented the proper error codes
- further breakdown
Added ONDIE ECC support. Currently this ecc mode is supported for
specific micron parts with oob size 64 bytes.
Signed-off-by: Punnaiah Choudary Kalluri
---
drivers/mtd/nand/pl353_nand.c | 131 +++-
1 files changed, 127 insertions(+), 4 deletions(-)
diff
Added software ecc support.
Signed-off-by: Punnaiah Choudary Kalluri
---
drivers/mtd/nand/pl353_nand.c | 163 +
1 files changed, 163 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/pl353_nand.c b/drivers/mtd/nand/pl353_nand.c
index 0be8ca2
Added notes about the controller and driver
Signed-off-by: Punnaiah Choudary Kalluri
---
Documentation/mtd/nand/pl353-nand.txt | 92 +
1 files changed, 92 insertions(+), 0 deletions(-)
create mode 100644 Documentation/mtd/nand/pl353-nand.txt
diff --git
://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
ARM pl353 smc TRM link:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
DDI0380G_smc_pl350_series_r2p1_trm.pdf
Punnaiah Choudary Kalluri (4):
nand: pl353: Add basic driver for arm pl353 smc nand interface
nand
://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
ARM pl353 smc TRM link:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
DDI0380G_smc_pl350_series_r2p1_trm.pdf
Punnaiah Choudary Kalluri (2):
Devicetree: Add pl353 smc controller devicetree binding information
Add driver for arm pl353 static memory controller. This controller is
used in xilinx zynq soc for interfacing the nand and nor/sram memory
devices.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v2:
- Since now the timing parameters are in nano seconds, added logic to convert
them
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v2:
- modified timing binding info as per onfi timing parameters
- add suffix nano second as timing unit
- modified the clock names as per the IP spec
---
.../bindings
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v2:
- modified timing binding info as per onfi timing parameters
- add suffix nano second as timing unit
- modified the clock names as per the IP spec
Add driver for arm pl353 static memory controller. This controller is
used in xilinx zynq soc for interfacing the nand and nor/sram memory
devices.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v2:
- Since now the timing parameters are in nano seconds, added logic
://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
ARM pl353 smc TRM link:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
DDI0380G_smc_pl350_series_r2p1_trm.pdf
Punnaiah Choudary Kalluri (2):
Devicetree: Add pl353 smc controller devicetree binding information
Added notes about the controller and driver
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Documentation/mtd/nand/pl353-nand.txt | 92 +
1 files changed, 92 insertions(+), 0 deletions(-)
create mode 100644 Documentation/mtd/nand/pl353-nand.txt
://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
ARM pl353 smc TRM link:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
DDI0380G_smc_pl350_series_r2p1_trm.pdf
Punnaiah Choudary Kalluri (4):
nand: pl353: Add basic driver for arm pl353 smc nand interface
nand
Added software ecc support.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
drivers/mtd/nand/pl353_nand.c | 163 +
1 files changed, 163 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/pl353_nand.c b/drivers/mtd/nand
Added ONDIE ECC support. Currently this ecc mode is supported for
specific micron parts with oob size 64 bytes.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
drivers/mtd/nand/pl353_nand.c | 131 +++-
1 files changed, 127 insertions(+), 4
Add driver for arm pl353 static memory controller nand interface with
HW ECC support. This controller is used in xilinx zynq soc for interfacing
the nand flash memory.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v3:
- implemented the proper error codes
- further
Zynq soc usb controller is a synopsys IP and it is compatible
with the chipidea spec. So, reusing chipidea drivers for zynq usb
controller.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
drivers/usb/chipidea/Makefile |1 +
drivers/usb/chipidea/ci_hdrc_zynq.c | 115
Document device tree binding information as required by
the ZYNQ USB controller.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
.../devicetree/bindings/usb/ci-hdrc-zynq.txt | 23
1 files changed, 23 insertions(+), 0 deletions(-)
create mode 100644
On Fri, Jun 27, 2014 at 9:09 AM, Peter Chen peter.c...@freescale.com wrote:
On Fri, Jun 27, 2014 at 09:10:09AM +0530, Punnaiah Choudary Kalluri wrote:
Zynq soc usb controller is a synopsys IP and it is compatible
with the chipidea spec. So, reusing chipidea drivers for zynq usb
controller
On Mon, Apr 21, 2014 at 12:22 AM, Marc Kleine-Budde wrote:
> On 04/20/2014 06:27 PM, Punnaiah Choudary Kalluri wrote:
>> Zynq soc contains a dual role usb controller and this IP is from synopsys. We
>> observed that there is driver available for this controller from freescale
&g
which is specifc to freescale with CONFIG_FSL_SOC. Please
suggest if there is a better way of doing this?
Punnaiah Choudary Kalluri (2):
usb: gadget: fsl_udc: Add support for zynq usb device controller
usb: ehci-fsl: Add support for zynq usb host controller
drivers/usb/gadget/Kconfig
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri
---
drivers/usb/gadget/Kconfig|2 +-
drivers/usb/gadget/Makefile |1
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri
---
drivers/usb/host/Kconfig|2 +-
drivers/usb/host/ehci-fsl.c | 63
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri
---
drivers/usb/gadget/Kconfig|2 +-
drivers/usb/gadget/Makefile |1
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri
---
drivers/usb/host/Kconfig|2 +-
drivers/usb/host/ehci-fsl.c | 63
which is specifc to freescale with CONFIG_FSL_SOC. Please
suggest if there is a better way of doing this?
Punnaiah Choudary Kalluri (2):
usb: gadget: fsl_udc: Add support for zynq usb device controller
usb: ehci-fsl: Add support for zynq usb host controller
drivers/usb/gadget/Kconfig
which is specifc to freescale with CONFIG_FSL_SOC. Please
suggest if there is a better way of doing this?
Punnaiah Choudary Kalluri (2):
usb: gadget: fsl_udc: Add support for zynq usb device controller
usb: ehci-fsl: Add support for zynq usb host controller
drivers/usb/gadget/Kconfig
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
drivers/usb/gadget/Kconfig|2 +-
drivers/usb/gadget
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
drivers/usb/host/Kconfig|2 +-
drivers/usb/host/ehci-fsl.c
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
drivers/usb/gadget/Kconfig|2 +-
drivers/usb/gadget
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
drivers/usb/host/Kconfig|2 +-
drivers/usb/host/ehci-fsl.c
which is specifc to freescale with CONFIG_FSL_SOC. Please
suggest if there is a better way of doing this?
Punnaiah Choudary Kalluri (2):
usb: gadget: fsl_udc: Add support for zynq usb device controller
usb: ehci-fsl: Add support for zynq usb host controller
drivers/usb/gadget/Kconfig
On Mon, Apr 21, 2014 at 12:22 AM, Marc Kleine-Budde m...@pengutronix.de wrote:
On 04/20/2014 06:27 PM, Punnaiah Choudary Kalluri wrote:
Zynq soc contains a dual role usb controller and this IP is from synopsys. We
observed that there is driver available for this controller from freescale
://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
ARM pl353 smc TRM link:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
DDI0380G_smc_pl350_series_r2p1_trm.pdf
Punnaiah Choudary Kalluri (4):
Devicetree: Add pl353 smc controller devicetree binding information
Add driver for arm pl353 static memory controller nand interface.
This controller is used in xilinx zynq soc for interfacing the nand
flash memory.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v2:
- use "depends on" rather than "select" option in kconfig
- re
Add driver for arm pl353 static memory controller. This controller is
used in xilinx zynq soc for interfacing the nand and nor/sram memory
devices.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v2:
- Since now the timing parameters are in nano seconds, added logic to convert
them
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v2:
- modified timing binding info as per onfi timing parameters
- add suffix nano second as timing unit
- modified the clock names as per the IP spec
---
.../bindings
Added binding information for onfi timing parameters as per the
onfi 1.0 specification. So, nand controllers that have support for
configuring any of these timing parameters can use this binding
information.
Signed-off-by: Punnaiah Choudary Kalluri
---
Documentation/devicetree/bindings/mtd
Added binding information for onfi timing parameters as per the
onfi 1.0 specification. So, nand controllers that have support for
configuring any of these timing parameters can use this binding
information.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Documentation/devicetree
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v2:
- modified timing binding info as per onfi timing parameters
- add suffix nano second as timing unit
- modified the clock names as per the IP spec
Add driver for arm pl353 static memory controller. This controller is
used in xilinx zynq soc for interfacing the nand and nor/sram memory
devices.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v2:
- Since now the timing parameters are in nano seconds, added logic
Add driver for arm pl353 static memory controller nand interface.
This controller is used in xilinx zynq soc for interfacing the nand
flash memory.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v2:
- use depends on rather than select option in kconfig
- remove
://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
ARM pl353 smc TRM link:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
DDI0380G_smc_pl350_series_r2p1_trm.pdf
Punnaiah Choudary Kalluri (4):
Devicetree: Add pl353 smc controller devicetree binding information
On Wed, Apr 9, 2014 at 4:33 PM, Borislav Petkov wrote:
> On Wed, Apr 09, 2014 at 11:34:31AM +0530, punnaiah choudary kalluri wrote:
>> Since it is recommended in Documentation/kernel-doc-nano-HOWTO.txt
>> but also said it is low priority and at the discretion of the MAINTAINER of
On Wed, Apr 9, 2014 at 2:10 AM, Borislav Petkov wrote:
> On Mon, Mar 17, 2014 at 10:53:44AM +0530, Punnaiah Choudary Kalluri wrote:
>> Added EDAC support for reporting the ecc errors of synopsys ddr controller.
>> The ddr ecc controller corrects single bit errors and detects doubl
On Wed, Apr 9, 2014 at 2:10 AM, Borislav Petkov b...@alien8.de wrote:
On Mon, Mar 17, 2014 at 10:53:44AM +0530, Punnaiah Choudary Kalluri wrote:
Added EDAC support for reporting the ecc errors of synopsys ddr controller.
The ddr ecc controller corrects single bit errors and detects double bit
On Wed, Apr 9, 2014 at 4:33 PM, Borislav Petkov b...@alien8.de wrote:
On Wed, Apr 09, 2014 at 11:34:31AM +0530, punnaiah choudary kalluri wrote:
Since it is recommended in Documentation/kernel-doc-nano-HOWTO.txt
but also said it is low priority and at the discretion of the MAINTAINER
Add bindings documentation for Zynq Quad SPI driver.
Signed-off-by: Punnaiah Choudary Kalluri
---
.../devicetree/bindings/spi/spi-zynq-qspi.txt | 26
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
diff
devices connected with two separate CS line and one
common set of 4 IO lines.
This series adds support for the first configuration (single).
Signed-off-by: Punnaiah Choudary Kalluri
---
drivers/spi/Kconfig |6 +
drivers/spi/Makefile|1 +
drivers/spi/spi-zynq-qspi.c
devices connected with two separate CS line and one
common set of 4 IO lines.
This series adds support for the first configuration (single).
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
drivers/spi/Kconfig |6 +
drivers/spi/Makefile|1 +
drivers/spi
Add bindings documentation for Zynq Quad SPI driver.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
.../devicetree/bindings/spi/spi-zynq-qspi.txt | 26
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-zynq
://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
ARM pl353 smc TRM link:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
DDI0380G_smc_pl350_series_r2p1_trm.pdf
Punnaiah Choudary Kalluri (3):
Devicetree: Add pl353 smc controller devicetree binding information
Add driver for arm pl353 static memory controller nand interface.
This controller is used in xilinx zynq soc for interfacing the nand
flash memory.
Signed-off-by: Punnaiah Choudary Kalluri
---
drivers/mtd/nand/Kconfig |8 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand
Add driver for arm pl353 static memory controller. This controller is
used in xilinx zynq soc for interfacing the nand and nor/sram memory
devices.
Signed-off-by: Punnaiah Choudary Kalluri
---
drivers/memory/Kconfig |8 +
drivers/memory/Makefile |1 +
drivers/memory
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Punnaiah Choudary Kalluri
---
.../bindings/memory-controllers/pl353-smc.txt | 53
1 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
.../bindings/memory-controllers/pl353-smc.txt | 53
1 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644
Documentation
://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
ARM pl353 smc TRM link:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0380g/
DDI0380G_smc_pl350_series_r2p1_trm.pdf
Punnaiah Choudary Kalluri (3):
Devicetree: Add pl353 smc controller devicetree binding information
Add driver for arm pl353 static memory controller nand interface.
This controller is used in xilinx zynq soc for interfacing the nand
flash memory.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
drivers/mtd/nand/Kconfig |8 +
drivers/mtd/nand/Makefile |1
Add driver for arm pl353 static memory controller. This controller is
used in xilinx zynq soc for interfacing the nand and nor/sram memory
devices.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
drivers/memory/Kconfig |8 +
drivers/memory/Makefile |1
Added EDAC support for reporting the ecc errors of synopsys ddr controller.
The ddr ecc controller corrects single bit errors and detects double bit
errors
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes for v2:
- Updated the commit header and message
- Renamed the filenames
Added EDAC support for reporting the ecc errors of synopsys ddr controller.
The ddr ecc controller corrects single bit errors and detects double bit
errors
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes for v2:
- Updated the commit header and message
- Renamed
>-Original Message-
>From: Michal Simek [mailto:michal.si...@xilinx.com]
>Sent: Wednesday, March 12, 2014 10:20 PM
>To: Soren Brinkmann
>Cc: Michal Simek; mon...@monstr.eu; Mark Rutland; Punnaiah Choudary
>Kalluri; dougthomp...@xmission.com; devicet...@vger.ker
-Original Message-
From: Michal Simek [mailto:michal.si...@xilinx.com]
Sent: Wednesday, March 12, 2014 10:20 PM
To: Soren Brinkmann
Cc: Michal Simek; mon...@monstr.eu; Mark Rutland; Punnaiah Choudary
Kalluri; dougthomp...@xmission.com; devicet...@vger.kernel.org; linux-
d
>-Original Message-
>From: Michal Simek [mailto:mon...@monstr.eu]
>Sent: Monday, March 10, 2014 5:29 PM
>To: Mark Rutland
>Cc: Punnaiah Choudary Kalluri; dougthomp...@xmission.com;
>devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-arm-
>ker...@lists
-Original Message-
From: Michal Simek [mailto:mon...@monstr.eu]
Sent: Monday, March 10, 2014 5:29 PM
To: Mark Rutland
Cc: Punnaiah Choudary Kalluri; dougthomp...@xmission.com;
devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-arm-
ker...@lists.infradead.org; linux-kernel
Added EDAC support for reporting the ecc errors of zynq ddr controller.
The ddr ecc controller corrects single bit errors and detects double bit
errors
Signed-off-by: Punnaiah Choudary Kalluri
---
.../devicetree/bindings/edac/zynq_edac.txt | 18 +
drivers/edac/Kconfig
Added EDAC support for reporting the ecc errors of zynq ddr controller.
The ddr ecc controller corrects single bit errors and detects double bit
errors
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
.../devicetree/bindings/edac/zynq_edac.txt | 18 +
drivers/edac
the edac driver need
modifications
for implementing shared irq mechanism.
So, i request your commnets on this patch and please suggest if there is a
better implemenattion than above.
Punnaiah Choudary Kalluri (1):
edac: add support for PL310 L2 cache parity
.../devicetree/bindings/edac
Add support for ARM Pl310 L2 cache controller parity error
Signed-off-by: Punnaiah Choudary Kalluri
---
.../devicetree/bindings/edac/pl310_edac_l2.txt | 19 ++
drivers/edac/Kconfig |7 +
drivers/edac/Makefile |1 +
drivers
Add support for ARM Pl310 L2 cache controller parity error
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
.../devicetree/bindings/edac/pl310_edac_l2.txt | 19 ++
drivers/edac/Kconfig |7 +
drivers/edac/Makefile
the edac driver need
modifications
for implementing shared irq mechanism.
So, i request your commnets on this patch and please suggest if there is a
better implemenattion than above.
Punnaiah Choudary Kalluri (1):
edac: add support for PL310 L2 cache parity
.../devicetree/bindings/edac
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