From: Stefan Chulski
Add parser entries for different IPv4 IHL values.
Each entry will set the L4 header offset according to the IPv4 IHL field.
L3 header offset will set during the parsing of the IPv4 protocol.
Because of missed parser support for IP header length > 20, RX IPv4 checksum HW
From: Stefan Chulski
Add parser entries for different IPv4 IHL values.
Each entry will set the L4 header offset according to the IPv4 IHL field.
L3 header offset will set during the parsing of the IPv4 protocol.
Suggested-by: Dana Vardi
Signed-off-by: Stefan Chulski
---
From: Stefan Chulski
According to Armada SoC architecture and design, all the PPv2 ports
which are populated on the same communication processor silicon die
(CP11x) share the same Classifier and Parser engines.
Armada is an embedded platform and therefore there is a need to reserve
some of the
From: Stefan Chulski
According to Armada SoC architecture and design, all the PPv2 ports
which are populated on the same communication processor silicon die
(CP11x) share the same Classifier and Parser engines.
Armada is an embedded platform and therefore there is a need to reserve
some of the
From: Stefan Chulski
PPv2 loopback port doesn't support RSS, so we should
skip RSS configurations for this port.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 25 +++-
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git
From: Stefan Chulski
With MTU less than 1500B on all ports, the driver uses per CPU pool mode.
If one of the ports set to jumbo frame MTU size, all ports move
to shared pools mode.
Here, buffer manager TX Flow Control reconfigured on all ports.
Signed-off-by: Stefan Chulski
---
From: Stefan Chulski
1KB is enough for loopback port, so 2KB can be distributed
between other ports.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 4 ++--
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 10 +-
2 files changed, 7 insertions(+),
From: Stefan Chulski
Use >= MVPP22 instead of != MVPP21.
Non functional change.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git
From: Stefan Chulski
Use PTR_ERR_OR_ZERO instead of IS_ERR and PTR_ERR.
Non functional change.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
From: Stefan Chulski
GENCONF_CTRL0_PORTX naming improved.
Non functional change.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 6 +++---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 8
2 files changed, 7 insertions(+), 7 deletions(-)
diff
From: Stefan Chulski
PPv2.1 contain 0 in Version ID register, priv->hw_version check
can be removed.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
From: Stefan Chulski
The patch series contains minor code improvements and did not change any
functionality.
Stefan Chulski (4):
net: mvpp2: simplify PPv2 version ID read
net: mvpp2: improve Packet Processor version check
net: mvpp2: improve mvpp2_get_sram return
net: mvpp2: improve
From: Stefan Chulski
The condition should be skipped if CPU ID equal to nthreads.
The patch doesn't fix any actual issue since
nthreads = min_t(unsigned int, num_present_cpus(), MVPP2_MAX_THREADS).
On all current Armada platforms, the number of CPU's is
less than MVPP2_MAX_THREADS.
Fixes:
From: Stefan Chulski
Currently we have PP2v1 and PP2v2 hw-versions, with some different
handlers depending upon condition hw_version = MVPP21/MVPP22.
In a future there will be also PP2v3. Let's use now the generic
"if equal/notEqual MVPP21" for all cases instead of "if MVPP22".
This patch does
From: Stefan Chulski
New FIFO flow control feature was added in PPv23.
PPv2 FIFO polled by HW and trigger pause frame if FIFO
fill level is below threshold.
FIFO HW flow control enabled with CM3 RXQ flow
control with ethtool.
Current FIFO thresholds is:
9KB for port with maximum speed 10Gb/s
From: Stefan Chulski
This patch adds RXQ flow control configurations.
Flow control disabled by default.
Minimum ring size limited to 1024 descriptors.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 35 +-
From: Stefan Chulski
The PP2v23 hardware supports a feature allowing to double the
size of BPPI by decreasing number of pools from 16 to 8.
Increasing of BPPI size protect BM drop from BPPI underrun.
Underrun could occurred due to stress on DDR and as result slow buffer
transition from BPPE to
From: Stefan Chulski
Patch check that TX FC firmware is running in CM3.
If not, global TX FC would be disabled.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 39
From: Stefan Chulski
This patch fix GMAC TX flow control autoneg.
Flow control autoneg wrongly were disabled with enabled TX
flow control.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Stefan Chulski
This patch add ethtool flow control configuration support.
Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.
Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.
From: Stefan Chulski
This patch enables global flow control in FW and in the phylink validate mask.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 11 +--
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 30
From: Stefan Chulski
The firmware needs to monitor the RX Non-occupied descriptor
bits for flow control to move to XOFF mode.
These bits need to be unmasked to be functional, but they will
not raise interrupts as we leave the RX exception summary
bit in MVPP2_ISR_RX_TX_MASK_REG clear.
From: Stefan Chulski
Flow Control periodic timer would be used if port in
XOFF to transmit periodic XOFF frames.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 ++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 45
From: Stefan Chulski
BM pool and RXQ size increased to support Firmware Flow Control.
Minimum depletion thresholds to support FC are 1024 buffers.
BM pool size increased to 2048 to have some 1024 buffers
space between depletion thresholds and BM pool size.
Jumbo frames require a 9888B buffer,
From: Stefan Chulski
This patch add PPv23 version definition.
PPv23 is new packet processor in CP115.
Everything that supported by PPv22, also supported by PPv23.
No functional changes in this stage.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
From: Stefan Chulski
This patch adds CM3 memory map.
Signed-off-by: Stefan Chulski
Reviewed-by: Andrew Lunn
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 26
2 files changed, 27
From: Konstantin Porotchkin
CM3 SRAM address space will be used for Flow Control configuration.
Signed-off-by: Stefan Chulski
Signed-off-by: Konstantin Porotchkin
Acked-by: Marcin Wojtas
Acked-by: Rob Herring
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +-
1 file changed, 1
From: Stefan Chulski
Patch adds CM3 address space and PPv2.3 description.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
Documentation/devicetree/bindings/net/marvell-pp2.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
From: Stefan Chulski
Armada hardware has a pause generation mechanism in GOP (MAC).
The GOP generate flow control frames based on an indication programmed in Ports
Control 0 Register. There is a bit per port.
However assertion of the PortX Pause bits in the ports control 0 register only
sends
From: Stefan Chulski
This entry used when skipping the parser needed,
for example, the custom header pretended to ethernet header.
Suggested-by: Liron Himi
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c | 15 +++
From: Stefan Chulski
Patch check that TX FC firmware is running in CM3.
If not, global TX FC would be disabled.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 39
From: Stefan Chulski
This patch fix GMAC TX flow control autoneg.
Flow control autoneg wrongly were disabled with enabled TX
flow control.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Stefan Chulski
The PP2v23 hardware supports a feature allowing to double the
size of BPPI by decreasing number of pools from 16 to 8.
Increasing of BPPI size protect BM drop from BPPI underrun.
Underrun could occurred due to stress on DDR and as result slow buffer
transition from BPPE to
From: Stefan Chulski
New FIFO flow control feature was added in PPv23.
PPv2 FIFO polled by HW and trigger pause frame if FIFO
fill level is below threshold.
FIFO HW flow control enabled with CM3 RXQ flow
control with ethtool.
Current FIFO thresholds is:
9KB for port with maximum speed 10Gb/s
From: Stefan Chulski
This patch add ethtool flow control configuration support.
Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.
Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.
From: Stefan Chulski
This patch adds RXQ flow control configurations.
Flow control disabled by default.
Minimum ring size limited to 1024 descriptors.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 35 +-
From: Stefan Chulski
This patch enables global flow control in FW and in the phylink validate mask.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 11 +--
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 30
From: Stefan Chulski
Flow Control periodic timer would be used if port in
XOFF to transmit periodic XOFF frames.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 ++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 45
From: Stefan Chulski
The firmware needs to monitor the RX Non-occupied descriptor
bits for flow control to move to XOFF mode.
These bits need to be unmasked to be functional, but they will
not raise interrupts as we leave the RX exception summary
bit in MVPP2_ISR_RX_TX_MASK_REG clear.
From: Stefan Chulski
BM pool and RXQ size increased to support Firmware Flow Control.
Minimum depletion thresholds to support FC are 1024 buffers.
BM pool size increased to 2048 to have some 1024 buffers
space between depletion thresholds and BM pool size.
Jumbo frames require a 9888B buffer,
From: Stefan Chulski
This patch add PPv23 version definition.
PPv23 is new packet processor in CP115.
Everything that supported by PPv22, also supported by PPv23.
No functional changes in this stage.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
From: Stefan Chulski
Currently we have PP2v1 and PP2v2 hw-versions, with some different
handlers depending upon condition hw_version = MVPP21/MVPP22.
In a future there will be also PP2v3. Let's use now the generic
"if equal/notEqual MVPP21" for all cases instead of "if MVPP22".
This patch does
From: Stefan Chulski
This patch adds CM3 memory map.
Signed-off-by: Stefan Chulski
Reviewed-by: Andrew Lunn
Acked-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 26
2 files changed, 27
From: Konstantin Porotchkin
CM3 SRAM address space will be used for Flow Control configuration.
Signed-off-by: Stefan Chulski
Signed-off-by: Konstantin Porotchkin
Acked-by: Marcin Wojtas
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Stefan Chulski
Patch adds CM3 address space and PPv2.3 description.
Signed-off-by: Stefan Chulski
Acked-by: Marcin Wojtas
---
Documentation/devicetree/bindings/net/marvell-pp2.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
From: Stefan Chulski
Armada hardware has a pause generation mechanism in GOP (MAC).
The GOP generate flow control frames based on an indication programmed in Ports
Control 0 Register. There is a bit per port.
However assertion of the PortX Pause bits in the ports control 0 register only
sends
From: Stefan Chulski
Patch check that TX FC firmware is running in CM3.
If not, global TX FC would be disabled.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 42
2 files changed,
From: Stefan Chulski
This patch fix GMAC TX flow control autoneg.
Flow control autoneg wrongly were disabled with enabled TX
flow control.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Stefan Chulski
New FIFO flow control feature was added in PPv23.
PPv2 FIFO polled by HW and trigger pause frame if FIFO
fill level is below threshold.
FIFO HW flow control enabled with CM3 RXQ flow
control with ethtool.
Current FIFO thresholds is:
9KB for port with maximum speed 10Gb/s
From: Stefan Chulski
The PP2v23 hardware supports a feature allowing to double the
size of BPPI by decreasing number of pools from 16 to 8.
Increasing of BPPI size protect BM drop from BPPI underrun.
Underrun could occurred due to stress on DDR and as result slow buffer
transition from BPPE to
From: Stefan Chulski
This patch add ethtool flow control configuration support.
Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.
Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.
From: Stefan Chulski
This patch adds RXQ flow control configurations.
Flow control disabled by default.
Minimum ring size limited to 1024 descriptors.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 35 +-
From: Stefan Chulski
This patch enables global flow control in FW and in the phylink validate mask.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 11 +--
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 30 +++-
2 files changed, 37
From: Stefan Chulski
The firmware needs to monitor the RX Non-occupied descriptor
bits for flow control to move to XOFF mode.
These bits need to be unmasked to be functional, but they will
not raise interrupts as we leave the RX exception summary
bit in MVPP2_ISR_RX_TX_MASK_REG clear.
From: Stefan Chulski
Flow Control periodic timer would be used if port in
XOFF to transmit periodic XOFF frames.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 ++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 45
2 files
From: Stefan Chulski
BM pool and RXQ size increased to support Firmware Flow Control.
Minimum depletion thresholds to support FC are 1024 buffers.
BM pool size increased to 2048 to have some 1024 buffers
space between depletion thresholds and BM pool size.
Jumbo frames require a 9888B buffer,
From: Stefan Chulski
This patch add PPv23 version definition.
PPv23 is new packet processor in CP115.
Everything that supported by PPv22, also supported by PPv23.
No functional changes in this stage.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 24
From: Stefan Chulski
Currently we have PP2v1 and PP2v2 hw-versions, with some different
handlers depending upon condition hw_version = MVPP21/MVPP22.
In a future there will be also PP2v3. Let's use now the generic
"if equal/notEqual MVPP21" for all cases instead of "if MVPP22".
This patch does
From: Stefan Chulski
This patch adds CM3 memory map.
Signed-off-by: Stefan Chulski
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 26
2 files changed, 27 insertions(+)
diff --git
From: Konstantin Porotchkin
CM3 SRAM address space would be used for Flow Control configuration.
Signed-off-by: Stefan Chulski
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Stefan Chulski
Patch adds CM3 address space and PPv2.3 description.
Signed-off-by: Stefan Chulski
---
Documentation/devicetree/bindings/net/marvell-pp2.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt
From: Stefan Chulski
Armada hardware has a pause generation mechanism in GOP (MAC).
The GOP generate flow control frames based on an indication programmed in Ports
Control 0 Register. There is a bit per port.
However assertion of the PortX Pause bits in the ports control 0 register only
sends
From: Stefan Chulski
This patch add ethtool flow control configuration support.
Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.
Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.
From: Stefan Chulski
This patch fix GMAC TX flow control autoneg.
Flow control autoneg wrongly were disabled with enabled TX
flow control.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Stefan Chulski
The PP2v23 hardware supports a feature allowing to double the
size of BPPI by decreasing number of pools from 16 to 8.
Increasing of BPPI size protect BM drop from BPPI underrun.
Underrun could occurred due to stress on DDR and as result slow buffer
transition from BPPE to
From: Stefan Chulski
Patch check that TX FC firmware is running in CM3.
If not, global TX FC would be disabled.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 42
2 files changed,
From: Stefan Chulski
New FIFO flow control feature was added in PPv23.
PPv2 FIFO polled by HW and trigger pause frame if FIFO
fill level is below threshold.
FIFO HW flow control enabled with CM3 RXQ flow
control with ethtool.
Current FIFO thresholds is:
9KB for port with maximum speed 10Gb/s
From: Stefan Chulski
This patch adds RXQ flow control configurations.
Flow control disabled by default.
Minimum ring size limited to 1024 descriptors.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 35 +-
From: Stefan Chulski
This patch enables global flow control in FW and in the phylink validate mask.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 11 +--
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 30 +++-
2 files changed, 37
From: Stefan Chulski
Flow Control periodic timer would be used if port in
XOFF to transmit periodic XOFF frames.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 ++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 45
2 files
From: Stefan Chulski
The firmware needs to monitor the RX Non-occupied descriptor
bits for flow control to move to XOFF mode.
These bits need to be unmasked to be functional, but they will
not raise interrupts as we leave the RX exception summary
bit in MVPP2_ISR_RX_TX_MASK_REG clear.
From: Stefan Chulski
BM pool and RXQ size increased to support Firmware Flow Control.
Minimum depletion thresholds to support FC are 1024 buffers.
BM pool size increased to 2048 to have some 1024 buffers
space between depletion thresholds and BM pool size.
Jumbo frames require a 9888B buffer,
From: Stefan Chulski
Currently we have PP2v1 and PP2v2 hw-versions, with some different
handlers depending upon condition hw_version = MVPP21/MVPP22.
In a future there will be also PP2v3. Let's use now the generic
"if equal/notEqual MVPP21" for all cases instead of "if MVPP22".
This patch does
From: Stefan Chulski
This patch add PPv23 version definition.
PPv23 is new packet processor in CP115.
Everything that supported by PPv22, also supported by PPv23.
No functional changes in this stage.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 24
From: Konstantin Porotchkin
CM3 SRAM address space would be used for Flow Control configuration.
Signed-off-by: Stefan Chulski
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Stefan Chulski
This patch adds CM3 memory map and CM3 read/write callbacks.
Signed-off-by: Stefan Chulski
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 26
2 files changed, 27
From: Stefan Chulski
Patch adds CM3 address space and PPv2.3 description.
Signed-off-by: Stefan Chulski
---
Documentation/devicetree/bindings/net/marvell-pp2.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt
From: Stefan Chulski
Armada hardware has a pause generation mechanism in GOP (MAC).
The GOP generate flow control frames based on an indication programmed in Ports
Control 0 Register. There is a bit per port.
However assertion of the PortX Pause bits in the ports control 0 register only
sends
From: Stefan Chulski
Patch check that TX FC firmware is running in CM3.
If not, global TX FC would be disabled.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 42
2 files changed,
From: Stefan Chulski
This patch add PPv23 version definition.
PPv23 is new packet processor in CP115.
Everything that supported by PPv22, also supported by PPv23.
No functional changes in this stage.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 24
From: Stefan Chulski
This patch fix GMAC TX flow control autoneg.
Flow control autoneg wrongly were disabled with enabled TX
flow control.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Stefan Chulski
This patch add ethtool flow control configuration support.
Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.
Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.
From: Stefan Chulski
The firmware needs to monitor the RX Non-occupied descriptor
bits for flow control to move to XOFF mode.
These bits need to be unmasked to be functional, but they will
not raise interrupts as we leave the RX exception summary
bit in MVPP2_ISR_RX_TX_MASK_REG clear.
From: Stefan Chulski
New FIFO flow control feature was added in PPv23.
PPv2 FIFO polled by HW and trigger pause frame if FIFO
fill level is below threshold.
FIFO HW flow control enabled with CM3 RXQ flow
control with ethtool.
Current FIFO thresholds is:
9KB for port with maximum speed 10Gb/s
From: Stefan Chulski
BM pool and RXQ size increased to support Firmware Flow Control.
Minimum depletion thresholds to support FC are 1024 buffers.
BM pool size increased to 2048 to have some 1024 buffers
space between depletion thresholds and BM pool size.
Jumbo frames require a 9888B buffer,
From: Stefan Chulski
The PP2v23 hardware supports a feature allowing to double the
size of BPPI by decreasing number of pools from 16 to 8.
Increasing of BPPI size protect BM drop from BPPI underrun.
Underrun could occurred due to stress on DDR and as result slow buffer
transition from BPPE to
From: Stefan Chulski
This patch adds RXQ flow control configurations.
Flow control disabled by default.
Minimum ring size limited to 1024 descriptors.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 35 +-
From: Stefan Chulski
This patch enables global flow control in FW and in the phylink validate mask.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 11 +--
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 30 +++-
2 files changed, 37
From: Stefan Chulski
Flow Control periodic timer would be used if port in
XOFF to transmit periodic XOFF frames.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 ++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 45
2 files
From: Stefan Chulski
Currently we have PP2v1 and PP2v2 hw-versions, with some different
handlers depending upon condition hw_version = MVPP21/MVPP22.
In a future there will be also PP2v3. Let's use now the generic
"if equal/notEqual MVPP21" for all cases instead of "if MVPP22".
This patch does
From: Stefan Chulski
This patch adds CM3 memory map and CM3 read/write callbacks.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 26
2 files changed, 27 insertions(+)
diff --git
From: Konstantin Porotchkin
CM3 SRAM address space would be used for Flow Control configuration.
Signed-off-by: Stefan Chulski
Signed-off-by: Konstantin Porotchkin
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Stefan Chulski
Patch adds CM3 address space PPv2.3 description.
Signed-off-by: Stefan Chulski
---
Documentation/devicetree/bindings/net/marvell-pp2.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt
From: Stefan Chulski
Armada hardware has a pause generation mechanism in GOP (MAC).
The GOP generate flow control frames based on an indication programmed in Ports
Control 0 Register. There is a bit per port.
However assertion of the PortX Pause bits in the ports control 0 register only
sends
From: Stefan Chulski
Patch check that TX FC firmware is running in CM3.
If not, global TX FC would be disabled.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 42
2 files changed,
From: Stefan Chulski
This patch fix GMAC TX flow control autoneg.
Flow control autoneg wrongly were disabled with enabled TX
flow control.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Stefan Chulski
New FIFO flow control feature was added in PPv23.
PPv2 FIFO polled by HW and trigger pause frame if FIFO
fill level is below threshold.
FIFO HW flow control enabled with CM3 RXQ flow
control with ethtool.
Current FIFO thresholds is:
9KB for port with maximum speed 10Gb/s
From: Stefan Chulski
The PP2v23 hardware supports a feature allowing to double the
size of BPPI by decreasing number of pools from 16 to 8.
Increasing of BPPI size protect BM drop from BPPI underrun.
Underrun could occurred due to stress on DDR and as result slow buffer
transition from BPPE to
From: Stefan Chulski
This patch add ethtool flow control configuration support.
Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.
Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.
From: Stefan Chulski
This patch adds RXQ flow control configurations.
Flow control disabled by default.
Minimum ring size limited to 1024 descriptors.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 35 +-
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