[PATCH V3] AHCI: Workaround for ThunderX Errata#22536

From: Tirumalesh Chalamarla Due to Errata in ThunderX, HOST_IRQ_STAT should be cleared before leaving the interrupt handler. The patch attempts to satisfy the need. Changes from V2: - removed newfile - code is now under CONFIG_ARM64 Changes from V1: - Rebased on top of l

[PATCH V2] AHCI: Workaround for ThunderX Errata#22536

From: Tirumalesh Chalamarla Due to Errata in ThunderX, HOST_IRQ_STAT should be cleared before leaving the interrupt handler. The patch attempts to satisfy the need. Changes from V1: - Rebased on top of libata/for-4.6 - Moved ThunderX intr handler to new file Signed-off-by: Tirum

[PATCH] irqchip-gicv3: Make sure read from ICC_IAR1_EL1 is visible on redestributor

From: Tirumalesh Chalamarla ARM GIC specification mention the need for dsb after ICC_IAR1_EL1 read. 4.1.1 Physical CPU Interface: "The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1 on the state of a returned INTID are not guaranteed to be visible until after the execution of a DSB." The effe

[PATCH] AHCI: Workaround for ThunderX Errata#22536

From: Tirumalesh Chalamarla Due to Errata in some versions of ThunderX, HOST_IRQ_STAT is neither EDGE nor LEVEL, ThunderX needs a special sequence for handling interrupt. The patch attempts to satisfy the need. Signed-off-by: Tirumalesh Chalamarla --- drivers/ata/ahci.c| 3 +++ drivers/at

[PATCH] irqchip-gicv3: wait for ack from redistributer after read_iar

From: Tirumalesh Chalamarla Systems with high number of cores and sufficiently loaded, there exists a small window where it is possible for re-distributor to illegally merge two LPI and cuases missing interrupts. Solution is, wait for ack from the redistributor after read_iar. A "dsb sy" after I