On 02/22/2015 07:05 PM, Boaz Harrosh wrote:
> On 02/22/2015 06:27 PM, Christoph Hellwig wrote:
<>
>> I won't be back to my nvdimm enabled hardware until after LSF/MM,
>> so any work from me in this area will have to wait a bit.
>>
<>
BTW: I have an out-of-tree patch that enables me to just
On 02/22/2015 06:27 PM, Christoph Hellwig wrote:
> On Thu, Feb 19, 2015 at 11:25:37AM +0200, Boaz Harrosh wrote:
>> I do not see why you need the nvdimm_type= kernel option at all.
>>
>> I have here a script that auto detects any NvDIMM. It works with all
>> the chips that I have access to. And
On Thu, Feb 19, 2015 at 11:25:37AM +0200, Boaz Harrosh wrote:
> I do not see why you need the nvdimm_type= kernel option at all.
>
> I have here a script that auto detects any NvDIMM. It works with all
> the chips that I have access to. And Also it has support for if you have
> memmap=sss\$aaa.
>
On 02/22/2015 07:05 PM, Boaz Harrosh wrote:
On 02/22/2015 06:27 PM, Christoph Hellwig wrote:
I won't be back to my nvdimm enabled hardware until after LSF/MM,
so any work from me in this area will have to wait a bit.
BTW: I have an out-of-tree patch that enables me to just emulate
an NvDIMM
On Thu, Feb 19, 2015 at 11:25:37AM +0200, Boaz Harrosh wrote:
I do not see why you need the nvdimm_type= kernel option at all.
I have here a script that auto detects any NvDIMM. It works with all
the chips that I have access to. And Also it has support for if you have
memmap=sss\$aaa.
For
On 02/22/2015 06:27 PM, Christoph Hellwig wrote:
On Thu, Feb 19, 2015 at 11:25:37AM +0200, Boaz Harrosh wrote:
I do not see why you need the nvdimm_type= kernel option at all.
I have here a script that auto detects any NvDIMM. It works with all
the chips that I have access to. And Also it has
On 02/19/2015 12:31 PM, Ingo Molnar wrote:
<>
>> I will submit a new version of my patch-1 with the
>> pr_warn.
>>
>> Or did you already apply my patch-1 and you want one on
>> top? What is the URL of your tree please?
>
> New patch please, and please also Cc: everyone who
> expressed interest
* Boaz Harrosh wrote:
> Do you require another redundant message who's purpose is to scare
> people off, like:
>
> e820: WARN [mem 0x0001-0x00017fff] is unknown type
> 12
>
> Sure I'll add it
That message looks useful (and not very scary), and also
emit a warning
* Boaz Harrosh wrote:
> On 02/19/2015 12:01 PM, Ingo Molnar wrote:
> >
> > * Dan Williams wrote:
> >
> >> On Wed, Feb 18, 2015 at 4:47 PM, Christoph Hellwig
> >> wrote:
> >>> On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
> In fact it was originally "type-6" until ACPI
On 02/19/2015 12:01 PM, Ingo Molnar wrote:
>
> * Dan Williams wrote:
>
>> On Wed, Feb 18, 2015 at 4:47 PM, Christoph Hellwig
>> wrote:
>>> On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
In fact it was originally "type-6" until ACPI 5
claimed that number for official
On 02/18/2015 09:35 PM, Dan Williams wrote:
> On Wed, Feb 18, 2015 at 11:27 AM, Ingo Molnar wrote:
>>
<>
>>>
>>> No, it seems the safe thing to do is prevent the
>>> kernel from accessing any memory that it does not know
>>> the side-effects of accessing.
>>
<>
The Kernel
* Dan Williams wrote:
> On Wed, Feb 18, 2015 at 4:47 PM, Christoph Hellwig wrote:
> > On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
> >> In fact it was originally "type-6" until ACPI 5
> >> claimed that number for official use, so these
> >> platforms, with early
On 02/19/2015 02:47 AM, Christoph Hellwig wrote:
> On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
>> In fact it was originally "type-6" until ACPI 5 claimed that number
>> for official use, so these platforms, with early proof-of-concept
>> nvdimm support, have already gone through
On 02/19/2015 02:47 AM, Christoph Hellwig wrote:
On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
In fact it was originally type-6 until ACPI 5 claimed that number
for official use, so these platforms, with early proof-of-concept
nvdimm support, have already gone through one
* Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Feb 18, 2015 at 4:47 PM, Christoph Hellwig h...@infradead.org wrote:
On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
In fact it was originally type-6 until ACPI 5
claimed that number for official use, so these
On 02/19/2015 12:01 PM, Ingo Molnar wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Feb 18, 2015 at 4:47 PM, Christoph Hellwig h...@infradead.org
wrote:
On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
In fact it was originally type-6 until ACPI 5
claimed
On 02/18/2015 09:35 PM, Dan Williams wrote:
On Wed, Feb 18, 2015 at 11:27 AM, Ingo Molnar mi...@kernel.org wrote:
No, it seems the safe thing to do is prevent the
kernel from accessing any memory that it does not know
the side-effects of accessing.
The Kernel does not do any such access.
* Boaz Harrosh b...@plexistor.com wrote:
Do you require another redundant message who's purpose is to scare
people off, like:
e820: WARN [mem 0x0001-0x00017fff] is unknown type
12
Sure I'll add it
That message looks useful (and not very scary), and also
emit
* Boaz Harrosh b...@plexistor.com wrote:
On 02/19/2015 12:01 PM, Ingo Molnar wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Feb 18, 2015 at 4:47 PM, Christoph Hellwig h...@infradead.org
wrote:
On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
In fact
On 02/19/2015 12:31 PM, Ingo Molnar wrote:
I will submit a new version of my patch-1 with the
pr_warn.
Or did you already apply my patch-1 and you want one on
top? What is the URL of your tree please?
New patch please, and please also Cc: everyone who
expressed interest in the thread
On Wed, Feb 18, 2015 at 4:47 PM, Christoph Hellwig wrote:
> On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
>> In fact it was originally "type-6" until ACPI 5 claimed that number
>> for official use, so these platforms, with early proof-of-concept
>> nvdimm support, have already
On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
> In fact it was originally "type-6" until ACPI 5 claimed that number
> for official use, so these platforms, with early proof-of-concept
> nvdimm support, have already gone through one transition to a new
> number. They need to do the
On Wed, Feb 18, 2015 at 11:27 AM, Ingo Molnar wrote:
>
> * Dan Williams wrote:
>
>> On Wed, Feb 18, 2015 at 10:53 AM, Ingo Molnar wrote:
>> >
>> > * Dan Williams wrote:
>> >
>> >> On Wed, Feb 18, 2015 at 10:30 AM, Ingo Molnar wrote:
>> >> >
>> >> > * Dan Williams wrote:
>> >> >
>> >> >> On
* Dan Williams wrote:
> On Wed, Feb 18, 2015 at 10:53 AM, Ingo Molnar wrote:
> >
> > * Dan Williams wrote:
> >
> >> On Wed, Feb 18, 2015 at 10:30 AM, Ingo Molnar wrote:
> >> >
> >> > * Dan Williams wrote:
> >> >
> >> >> On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh
> >> >> wrote:
> >> >>
On Wed, Feb 18, 2015 at 10:53 AM, Ingo Molnar wrote:
>
> * Dan Williams wrote:
>
>> On Wed, Feb 18, 2015 at 10:30 AM, Ingo Molnar wrote:
>> >
>> > * Dan Williams wrote:
>> >
>> >> On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh wrote:
>> >> > On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
>> >>
* Dan Williams wrote:
> On Wed, Feb 18, 2015 at 10:30 AM, Ingo Molnar wrote:
> >
> > * Dan Williams wrote:
> >
> >> On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh wrote:
> >> > On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
> >> >> On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh wrote:
On Wed, Feb 18, 2015 at 10:30 AM, Ingo Molnar wrote:
>
> * Dan Williams wrote:
>
>> On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh wrote:
>> > On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
>> >> On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh wrote:
>> >>> In any way this is a problem
* Dan Williams wrote:
> On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh wrote:
> > On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
> >> On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh wrote:
> >>> In any way this is a problem for the new type-12 NvDIMM memory chips that
> >>> are
On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh wrote:
> On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
>> On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh wrote:
>>> In any way this is a problem for the new type-12 NvDIMM memory chips that
>>> are circulating around. (It is estimated that
On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh b...@plexistor.com wrote:
On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh wrote:
In any way this is a problem for the new type-12 NvDIMM memory chips that
are circulating around. (It is
* Dan Williams dan.j.willi...@intel.com wrote:
On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh b...@plexistor.com wrote:
On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh wrote:
In any way this is a problem for the new type-12 NvDIMM
* Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Feb 18, 2015 at 10:30 AM, Ingo Molnar mi...@kernel.org wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh b...@plexistor.com wrote:
On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Feb 18, 2015 at 10:53 AM, Ingo Molnar mi...@kernel.org wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Feb 18, 2015 at 10:30 AM, Ingo Molnar mi...@kernel.org wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Feb 18, 2015 at 10:30 AM, Ingo Molnar mi...@kernel.org wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh b...@plexistor.com wrote:
On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh
On Wed, Feb 18, 2015 at 10:53 AM, Ingo Molnar mi...@kernel.org wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Feb 18, 2015 at 10:30 AM, Ingo Molnar mi...@kernel.org wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Tue, Feb 17, 2015 at 12:42 AM, Boaz Harrosh
On Wed, Feb 18, 2015 at 11:27 AM, Ingo Molnar mi...@kernel.org wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Feb 18, 2015 at 10:53 AM, Ingo Molnar mi...@kernel.org wrote:
* Dan Williams dan.j.willi...@intel.com wrote:
On Wed, Feb 18, 2015 at 10:30 AM, Ingo Molnar
On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
In fact it was originally type-6 until ACPI 5 claimed that number
for official use, so these platforms, with early proof-of-concept
nvdimm support, have already gone through one transition to a new
number. They need to do the same
On Wed, Feb 18, 2015 at 4:47 PM, Christoph Hellwig h...@infradead.org wrote:
On Wed, Feb 18, 2015 at 10:15:32AM -0800, Dan Williams wrote:
In fact it was originally type-6 until ACPI 5 claimed that number
for official use, so these platforms, with early proof-of-concept
nvdimm support, have
On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
> On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh wrote:
>> In any way this is a problem for the new type-12 NvDIMM memory chips that
>> are circulating around. (It is estimated that there are already 100ds of
>> thousands NvDIMM chips in active
On 02/17/2015 12:03 AM, Matthew Wilcox wrote:
On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh wrote:
In any way this is a problem for the new type-12 NvDIMM memory chips that
are circulating around. (It is estimated that there are already 100ds of
thousands NvDIMM chips in active use)
On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh wrote:
> In any way this is a problem for the new type-12 NvDIMM memory chips that
> are circulating around. (It is estimated that there are already 100ds of
> thousands NvDIMM chips in active use)
Hang on. NV-DIMM chips don't know anyhing
On Mon, Feb 16, 2015 at 01:07:07PM +0200, Boaz Harrosh wrote:
In any way this is a problem for the new type-12 NvDIMM memory chips that
are circulating around. (It is estimated that there are already 100ds of
thousands NvDIMM chips in active use)
Hang on. NV-DIMM chips don't know anyhing
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