Arjan van de Ven wrote:
On Sat, Jan 22, 2005 at 02:48:52PM +0100, Matthias-Christian Ott wrote:
The Pentium4 models 0&1 have a longer MSR_EBC_FREQUENCY_ID register as
the models 2&3, so the bit shift must be bigger.
I would feel safer if this checked that it was actually a p4 as well...
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On Sat, Jan 22, 2005 at 02:48:52PM +0100, Matthias-Christian Ott wrote:
> The Pentium4 models 0&1 have a longer MSR_EBC_FREQUENCY_ID register as
> the models 2&3, so the bit shift must be bigger.
I would feel safer if this checked that it was actually a p4 as well...
-
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The Pentium4 models 0&1 have a longer MSR_EBC_FREQUENCY_ID register as
the models 2&3, so the bit shift must be bigger.
Signed-off-by: Matthias-Christian Ott <[EMAIL PROTECTED]>
--- linux-bk/arch/i386/kernel/cpu/cpufreq/speedstep-lib.c.orig
2005-01-21 13:55:37.0 +0100
+++
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