Hi
On 10/24/2018 09:11 AM, Clément Péron wrote:
> Hi,
>
> On Wed, 24 Oct 2018 at 08:51, Uwe Kleine-König
> wrote:
>>
>> On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote:
>>>
>>>
>>> On 10/23/2018 09:44 AM, Clément Péron wrote:
HI Dinh,
On Tue, 23 Oct 2018 at 16:04, Dinh
Hi,
On Wed, 24 Oct 2018 at 08:51, Uwe Kleine-König
wrote:
>
> On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote:
> >
> >
> > On 10/23/2018 09:44 AM, Clément Péron wrote:
> > > HI Dinh,
> > >
> > > On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen wrote:
> > >>
> > >> Hi Clément,
> > >>
> > >>
On Tue, Oct 23, 2018 at 03:35:31PM -0500, Dinh Nguyen wrote:
>
>
> On 10/23/2018 09:44 AM, Clément Péron wrote:
> > HI Dinh,
> >
> > On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen wrote:
> >>
> >> Hi Clément,
> >>
> >> On 10/09/2018 06:28 AM, Clément Péron wrote:
> >>> Cyclone5 and Arria10 doesn't h
On 10/23/2018 09:44 AM, Clément Péron wrote:
> HI Dinh,
>
> On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen wrote:
>>
>> Hi Clément,
>>
>> On 10/09/2018 06:28 AM, Clément Péron wrote:
>>> Cyclone5 and Arria10 doesn't have the same memory map for UART1.
>>>
>>> Split the SOCFPGA_UART1 into 2 options
HI Dinh,
On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen wrote:
>
> Hi Clément,
>
> On 10/09/2018 06:28 AM, Clément Péron wrote:
> > Cyclone5 and Arria10 doesn't have the same memory map for UART1.
> >
> > Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for
> > Cylone5.
> >
>
> I'm
Hi Clément,
On 10/09/2018 06:28 AM, Clément Péron wrote:
> Cyclone5 and Arria10 doesn't have the same memory map for UART1.
>
> Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for
> Cylone5.
>
I'm not sure the need for this patch. Are there any cyclone5 based
boards that has
Cyclone5 and Arria10 doesn't have the same memory map for UART1.
Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5.
Signed-off-by: Clément Péron
---
arch/arm/Kconfig.debug | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/a
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