On 08/11/2018 03:58 PM, Marek Vasut wrote:
> On 06/08/2018 12:58 AM, Florian Fainelli wrote:
>> Per the ARM reference manual for the Cortex-A15, The ACTLR:
>>
>> Is a read/write register.
>>
>> Common to the Secure and Non-secure states.
>>
>> Is only accessible from PL1 or higher, with access
On 08/11/2018 03:58 PM, Marek Vasut wrote:
> On 06/08/2018 12:58 AM, Florian Fainelli wrote:
>> Per the ARM reference manual for the Cortex-A15, The ACTLR:
>>
>> Is a read/write register.
>>
>> Common to the Secure and Non-secure states.
>>
>> Is only accessible from PL1 or higher, with access
On 06/08/2018 12:58 AM, Florian Fainelli wrote:
> Per the ARM reference manual for the Cortex-A15, The ACTLR:
>
> Is a read/write register.
>
> Common to the Secure and Non-secure states.
>
> Is only accessible from PL1 or higher, with access rights that depend
> on the mode:
>
> *
On 06/08/2018 12:58 AM, Florian Fainelli wrote:
> Per the ARM reference manual for the Cortex-A15, The ACTLR:
>
> Is a read/write register.
>
> Common to the Secure and Non-secure states.
>
> Is only accessible from PL1 or higher, with access rights that depend
> on the mode:
>
> *
Per the ARM reference manual for the Cortex-A15, The ACTLR:
Is a read/write register.
Common to the Secure and Non-secure states.
Is only accessible from PL1 or higher, with access rights that depend
on the mode:
* Read/write in Secure PL1 modes.
* Read-only and write-ignored in
Per the ARM reference manual for the Cortex-A15, The ACTLR:
Is a read/write register.
Common to the Secure and Non-secure states.
Is only accessible from PL1 or higher, with access rights that depend
on the mode:
* Read/write in Secure PL1 modes.
* Read-only and write-ignored in
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