Re: [alsa-devel] [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-22 Thread Ben Dooks
On Fri, Jan 17, 2014 at 10:35:10AM +, Dimitris Papastamos wrote: > > Charles (or someone else from Wolfson), you commented on previous > > versions of this - are you still OK with it? > > Looks good to me. > > Privacy & Confidentiality Notice >

Re: [alsa-devel] [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-22 Thread Ben Dooks
On Fri, Jan 17, 2014 at 10:35:10AM +, Dimitris Papastamos wrote: Charles (or someone else from Wolfson), you commented on previous versions of this - are you still OK with it? Looks good to me. Privacy Confidentiality Notice - This

Re: [alsa-devel] [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-20 Thread Daniel Matuschek
I'm sorry for this. Looks like I still had problems with some whitespaces. I will resend the patch and hope, it will work now. Daniel Am 17.01.2014 um 13:22 schrieb Mark Brown : > On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: > >> WM8804 can run with PLL frequencies of

Re: [alsa-devel] [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-20 Thread Daniel Matuschek
I'm sorry for this. Looks like I still had problems with some whitespaces. I will resend the patch and hope, it will work now. Daniel Am 17.01.2014 um 13:22 schrieb Mark Brown broo...@kernel.org: On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: WM8804 can run with PLL

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Mark Brown
On Fri, Jan 17, 2014 at 07:44:02PM +0100, Florian Meier wrote: > On 01/17/2014 07:33 PM, Mark Brown wrote: > > Setting it to false increases power consumption since the device is > > kept more powered on when idle but reduces startup time from idle. For > > digital only devices like the wm8804

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Florian Meier
On 01/17/2014 07:33 PM, Mark Brown wrote: > On Fri, Jan 17, 2014 at 07:06:24PM +0100, Florian Meier wrote: >> > Intentionally off-list? Oh no - I am sorry! >> If I remember correctly the error was >> "codec can not start from non-off bias with idle_bias_off==true" > >> I think the solution is

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Daniel Matuschek
The idle_bias_off should not be part of this patch. I will check this again. Am 17.01.2014 um 18:59 schrieb Mark Brown : > On Fri, Jan 17, 2014 at 05:43:14PM +0100, Florian Meier wrote: >> I have tested your patch. >> There is a (non blocking) error message regarding .idle_bias_off, but I >>

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Mark Brown
On Fri, Jan 17, 2014 at 05:43:14PM +0100, Florian Meier wrote: > I have tested your patch. > There is a (non blocking) error message regarding .idle_bias_off, but I > assume that should not have something to do with your patch. Can we just > set idle_bias_off to false here? What is the error

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Florian Meier
I have tested your patch. There is a (non blocking) error message regarding .idle_bias_off, but I assume that should not have something to do with your patch. Can we just set idle_bias_off to false here? Otherwise, it looks good to me. On 01/14/2014 08:34 PM, Daniel Matuschek wrote: > WM8804 can

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Mark Brown
On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: > WM8804 can run with PLL frequencies of 256xfs and 128xfs for > most sample rates. At 192kHz only 128xfs is supported. The > existing driver selects 128xfs automatically for some lower This patch doesn't apply against current

RE: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Dimitris Papastamos
> Charles (or someone else from Wolfson), you commented on previous > versions of this - are you still OK with it? Looks good to me. Privacy & Confidentiality Notice - This message and any attachments contain privileged and confidential

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Charles Keepax
On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: > WM8804 can run with PLL frequencies of 256xfs and 128xfs for > most sample rates. At 192kHz only 128xfs is supported. The > existing driver selects 128xfs automatically for some lower > samples rates. By using an additional

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Charles Keepax
On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an additional mclk_div

RE: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Dimitris Papastamos
Charles (or someone else from Wolfson), you commented on previous versions of this - are you still OK with it? Looks good to me. Privacy Confidentiality Notice - This message and any attachments contain privileged and confidential information

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Mark Brown
On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower This patch doesn't apply against current code.

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Florian Meier
I have tested your patch. There is a (non blocking) error message regarding .idle_bias_off, but I assume that should not have something to do with your patch. Can we just set idle_bias_off to false here? Otherwise, it looks good to me. On 01/14/2014 08:34 PM, Daniel Matuschek wrote: WM8804 can

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Mark Brown
On Fri, Jan 17, 2014 at 05:43:14PM +0100, Florian Meier wrote: I have tested your patch. There is a (non blocking) error message regarding .idle_bias_off, but I assume that should not have something to do with your patch. Can we just set idle_bias_off to false here? What is the error message?

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Daniel Matuschek
The idle_bias_off should not be part of this patch. I will check this again. Am 17.01.2014 um 18:59 schrieb Mark Brown broo...@kernel.org: On Fri, Jan 17, 2014 at 05:43:14PM +0100, Florian Meier wrote: I have tested your patch. There is a (non blocking) error message regarding .idle_bias_off,

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Florian Meier
On 01/17/2014 07:33 PM, Mark Brown wrote: On Fri, Jan 17, 2014 at 07:06:24PM +0100, Florian Meier wrote: Intentionally off-list? Oh no - I am sorry! If I remember correctly the error was codec can not start from non-off bias with idle_bias_off==true I think the solution is just to set

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-17 Thread Mark Brown
On Fri, Jan 17, 2014 at 07:44:02PM +0100, Florian Meier wrote: On 01/17/2014 07:33 PM, Mark Brown wrote: Setting it to false increases power consumption since the device is kept more powered on when idle but reduces startup time from idle. For digital only devices like the wm8804 there

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-16 Thread Mark Brown
On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: > WM8804 can run with PLL frequencies of 256xfs and 128xfs for > most sample rates. At 192kHz only 128xfs is supported. The > existing driver selects 128xfs automatically for some lower Charles (or someone else from Wolfson), you

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-16 Thread Mark Brown
On Tue, Jan 14, 2014 at 08:34:10PM +0100, Daniel Matuschek wrote: WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower Charles (or someone else from Wolfson), you

[PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-14 Thread Daniel Matuschek
WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an additional mclk_div divider, it is now possible to control the behaviour. This allows

[PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-14 Thread Daniel Matuschek
WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an additional mclk_div divider, it is now possible to control the behaviour. This allows

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-13 Thread Charles Keepax
On Sun, Jan 12, 2014 at 10:11:25PM +0100, Daniel Matuschek wrote: > Signed-off-by: Daniel Matuschek > > After some discussions of the patch last week, here is a new version. > Simply reducing the post_table did not work, as for some frequencies > both settings (MCLKDIV=0 and MCLKDIV=1) are

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-13 Thread Florian Meier
On 01/12/2014 10:11 PM, Daniel Matuschek wrote: > Signed-off-by: Daniel Matuschek > > After some discussions of the patch last week, here is a new version. > Simply reducing the post_table did not work, as for some frequencies > both settings (MCLKDIV=0 and MCLKDIV=1) are needed (e.g. 96 and

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-13 Thread Florian Meier
On 01/12/2014 10:11 PM, Daniel Matuschek wrote: Signed-off-by: Daniel Matuschek dan...@matuschek.net After some discussions of the patch last week, here is a new version. Simply reducing the post_table did not work, as for some frequencies both settings (MCLKDIV=0 and MCLKDIV=1) are needed

Re: [PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-13 Thread Charles Keepax
On Sun, Jan 12, 2014 at 10:11:25PM +0100, Daniel Matuschek wrote: Signed-off-by: Daniel Matuschek dan...@matuschek.net After some discussions of the patch last week, here is a new version. Simply reducing the post_table did not work, as for some frequencies both settings (MCLKDIV=0 and

[PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-12 Thread Daniel Matuschek
Signed-off-by: Daniel Matuschek After some discussions of the patch last week, here is a new version. Simply reducing the post_table did not work, as for some frequencies both settings (MCLKDIV=0 and MCLKDIV=1) are needed (e.g. 96 and 192kHz) WM8804 can run with PLL frequencies of 256xfs

[PATCH] ASoC: wm8804: Allow control of master clock divider in PLL generation

2014-01-12 Thread Daniel Matuschek
Signed-off-by: Daniel Matuschek dan...@matuschek.net After some discussions of the patch last week, here is a new version. Simply reducing the post_table did not work, as for some frequencies both settings (MCLKDIV=0 and MCLKDIV=1) are needed (e.g. 96 and 192kHz) WM8804 can run with PLL